EE251: Tuesday December 4 Memory Subsystem continued Timing requirements Adding memory beyond 4 Gbyte Time Allowing: Begin Review for Final Exam Homework #9 due Thursday at beginning of class Friday is deadline for all labs; all labs required! Practical Exam #2 is this week during lab. See website. Final Exam on Monday, Dec 10, 2:00 pm. 90 minute exam Final Review on Sunday, Dec. 9 at 6 pm in ENGR 120 Two sided sheet with handwritten notes allowed and encouraged Calculator (Hex OK) allowed and encouraged Pencils and eraser HIGHLY encouraged Lecture #28 1
Practical # 2 There are 6 different labs; each has its own different practical exam But these exams aren t very different Therefore it is critical that you not share what was on your practical with anyone else until all practicals are complete, and don t ask others to share with you There have been an few problems with this in the past, and the consequences for those sharing have been very real Do your best on your own, and depend on some partial credit for what you do accomplish on your own. Questions? Lecture #28 2
TM4C Development Board The TM4C Development Board which was provided for your use at the beginning of the semester is YOURS! Part of your course fee this semester. No need to return it to anyone--i won t be around on Friday the 7 th as I said I would. Sorry about the confusion I just learned Thursday that these were part of your course fee. Enjoy your board! Teach it lots of fun tricks! Lecture #28 3
Expanding Memory Can expand physical memory beyond what s included on chip, within processor s address space. Some Design Requirements for adding memory: Maintain unique address for each memory location (data stored only once). The data bus is properly connected to all memory chips. Control lines are routed to appropriate pins on each memory chip. External memory chips are electrically compatible with our processor. Timing: This is the most complex part of expanding memory AND you need to grasp the concept. Lecture #28 4
Memory Timing Analysis Read Cycle A valid address is placed on address lines, guaranteed by rising edge of ECLK (external version of clock) Who guarantees this? (Hint: who creates address signal?) Control signals (ECLK and R/W) are issued to provide control signals to the memory (CS,OE) while ECLK is high Who provides these control signals? Data is read from the external memory must be there before falling edge of ECLK (details soon) Who assures data is there? (Hint: from the external memory ) Lecture #28 5
Memory Read Timing Diagram ADDR[31:0] DATA[7:0] R/W* All signals are provided by the CPU, except DATA[7:0]. Lecture #28 6
Read Data Setup Time Valid data will be available on the data pins after ALL the following RAM chip timing conditions have been satisfied: t ADDR (address access time): is defined as the time delay between when a valid address is provided to memory and when valid data is provided by memory. t CS (chip select access time): is defined as the time delay between when a valid Chip Select (CS*) is provided to memory and when valid data is provided by memory. t OE (output enable access time): is defined as the time delay between when a valid Output Enable (OE*) is provided to memory and when valid data is provided by memory. When we refer to (for example) a 15 ns RAM, we usually mean the address access time, t ADDR. That is because this is usually the determining speed factor of the three above. Lecture #28 7
Read Timing Signals RAM Chip Lecture #28 8
Typical Read Timing Signals t DHR E clock low t DSR E clock high After all the control signals are asserted and data is provided by the memory, data is read by the processor. However, a proper amount of read data hold time (t DHR ) and read data set-up time (t DSR ) must be followed for a proper data read operation. Read Data Hold time (t DHR ) : Specifies how long the data must remain valid after the falling edge of ECLK. Read Data Set-up time (t DSR ) : specifies how long the data must be present before the falling edge of ECLK. Lecture #28 9
Combined Read Timing Requirements T Eclock t else t dsr E clock low E clock high Addr valid Data valid ½T Eclock All memory signals must come true during high level of E clock. Therefore: CS--must have: logic to chip select + t cs + t dsr < 1/2 CPU Cycle Time = T Eclock /2 Or: logic to chip select + t cs < t else where t else = T Eclock /2 - t dsr Address--must have: t addr < t else Output Enable--must have: t NAND + t OE < t else Lecture #28 10
Read Timing Requirements Example t else = ½T Eclock t dsr logic to chip select + t cs < t else t addr < t else t NAND + t OE < t else Assume 10 MHz Bus Clock External chip assumptions: NAND gate has 8 ns. delay 3-8 decoder takes 23 ns. from any input Assume no logic to decoder enable lines Processor: t dsr = 19 ns. Memory Chip: t cs = 17 ns. t addr = 35 ns. t OE = 22 ns. SOLUTION: 10 MHz bus clock => T Eclock = 100 ns t else = ½T Eclock t dsr t else = 50 ns 19 ns = 31 ns logic to chip select + t cs < t else 23 ns + 17 ns = 40 ns <? 31 ns NO t addr < t else 35 ns <? 31 ns NO t NAND + t OE < t else 8 ns + 22 ns = 30 ns <? 31 ns YES Lecture #28 11
Another Read Timing Example t else = ½T Eclock t dsr logic to chip select + t cs < t else t addr < t else t NAND + t OE < t else Assume 8.33 MHz Bus Clock External chip assumptions: NAND gate has 10 ns. delay 3-8 decoder takes 25 ns. from any input Assume no logic to decoder enable lines Processor: t dsr = 25 ns. Memory Chip: t cs = 20 ns. t addr = 32 ns. t OE = 24 ns. SOLUTION: 8.33 MHz bus clock => T Eclock = 120 ns t else = ½T Eclock t dsr t else = 60 ns 25ns = 35 ns logic to chip select + t cs < t else 25 ns + 20 ns = 45 ns t addr < t else 32 ns t NAND + t OE < t else 10 ns + 24 ns = 34 ns Lecture #28 12
Example Write Cycle and Timing The write cycle consists of the following: 1. Control signals are issued by the CPU before ECLK rising edge. 2. CPU places address on the address lines ADDR[15:0] by ECLK. 3. CPU places data on the Data lines DATA[15:0] after ECLK. 4. Data is written into the desired memory location. All signals are provided by the processor. Lecture #28 13
Write Cycle Timing for RAM Chip The timing constraints for the write cycle is dictated by the properties of the memory unit (RAM). Hence, the memory data sheet would specify these constraints. Below is the brief description of the constraints t AS (Address Setup Time) : The address lines must be stable for a period of t AS time before the control signals are asserted (CS and WE) t AH (Address Hold time): The address lines must be held for a period of t AH (ns) after the control lines de-asserted. t CSW (Chip Select setup): CS line must be asserted t CSW (ns) before the end of the write cycle t WP (write pulse width) :The write enable control signal must stay asserted at least this long for a proper write t DS (Data Setup time): Data input lines must be stable at least t DS ns before the write cycle ends. t DH (Data Hold Time): All data inputs must be held stable until this time after the write cycle ends. Lecture #28 14
Combined Write Timing Requirements T Eclock ½T Eclock Supplied by Processor ECLK ADDR Bus DATA Bus E clock low E clock high Addr valid Data valid R/W* t DS CS* t CSW WE* t WP More signals to analyze on write cycle vs read: T as : address setup (address true before CS* and WE* activated), usually 0 ns. T csw : chip select setup before end of WE* pulse. A key parameter T wp : width of write pulse (WE*). Also a key parameter T ds : data valid before end of write. Another key parameter T dh : data true after end of write. Usually 0 ns. Lecture #28 15
Memory Expansion The memory of the most computer architectures can be expanded BEYOND their addressable memory space. This is done using a technology called Memory Paging, and is a common technique for microprocessors (including the Intel X86 architecture). The following slides will describe how it is done in the HCS12 Architecture as an example. This processor was used in ECE 251 before the TM4C. Some ARM processors, but not ours, allow memory paging. Lecture #28 16
Memory Paging Memory paging is concept in which a portion of the large memory can be accessed through a fixed window. This is analogous to a opening a page in the book and accessing only the information contained on the page. In this case, all the words in the book constitute our whole memory, and by referring to page numbers, we can have an access to the entire book, page by page. Some versions of the HCS12 have one memory expansion window, controlled by register PPAGE(0x30) whose use is described on the following slide. Lecture #28 17
Memory Paging Diagram Up to Page 63 The HCS12 Core architecture limits the physical address space available to 64K bytes. The Program Page Index Register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits (PIX5:PIX0 of PPAGE) to page 64 16K byte blocks into the Program Page Window located between $8000 and $BFFF. Lecture #28 18
Program Page Index Register Bits These page index bits are used to select which of the 64 FLASH or ROM array pages is to be accessed in the Program Page Window as shown below: Lecture #28 19
Physical Memory Addressing Given this address space architecture, how much ROM/Flash memory can be addressed? 16K 64 = KBytes = MBytes So how many address lines must go to this physical flash memory if it is fully loaded? 2 to what power is the number above? So the physical address lines to this subsystem include 14 address lines (addr[13:0]) for each page and 6 extended address lines (Pix[5:0]). Other versions of this processor also allow mapped RAM to extend the amount of R/W memory in the system. Lecture #28 20
ECE 251 Final Exam Review Closed Book. Calculator OK. Ruler recommended. Appropriate Reference Two sides of one page handwritten notes OK. Documents will be provided. Topics Mostly Since Mid-Term Exam Ports Port Registers RCGCGPIO, DATA, DIR, DEN PUR, PDR, AFSEL Memory Mapped I/O Parallel I/O Input from Ports Output to Ports Switch Input Keypad Input LED Output 7 Segment Displays TIVA I/O Devices Buffers, esp. tristate I/O Programming Bit-Specific Addressing Delay Loops Polling vs. Interrupt Exceptions Reset Faults Interrupts Action upon Interrupt ISRs Turn on-off Interrupt Conditions Interrupt Handling Processor Action Register Stacking Programmer Action Use of Link Register (LR) Interrupt Vector Map Priority IRQ* Interrupt Line ISR Examples Fixed-point Arithmetic Floating-point Arithmetic Real-Time Module SysTick Phase Lock Loop Interrupts on fixed interval Engineering Notation Instruction Encoding/Decoding Timer Module GPTM Timer Clock Period, Frequency, Duty Cycle Input Capture Output-Compare Pulse Count I/O Pins via AFSEL Various GPTM Registers Interrupts with TIM A/D Conversion Encoding Quantization Resolution, Dynamic Range Nyquist Sampling Theorem Data Rate Sampler, Comparator Converter Methods Parallel or Flash Slope Successive Approximation TM4C A/D Functionality 12 Analog Inputs 12-bit converters Separate power connections Reference Voltage Inputs Sequencer Operation Various A/D Registers Rate, Triggers, Sequences, Channels, Power-up Configuration/Use examples Binary to BCD to 7-Segment A/D Conversion Formulas Serial I/O Synchronous Master/Slave Various Signals Nokia Display Asynchronous-UART Baud, Frames, NRZ Protocol, Parity, Signals Memory Interfacing Address, Data, Controls Electrical Compatibility Lecture #28 21
Some Review Questions Two s Complement Math & Status Bits Fixed Point (Qm.n) Data Representations Base 10 to Binary and vice-versa Signed and Unsigned Lecture #28 22
More Review Questions Floating Point Representations Floating Point to Base 10 Base 10 to Floating Point Others? Lecture #28 23
IEEE 754 Lecture #22 24
Summary Memory Read and Write Timing Expanding Memory Beyond Address Space Limits of Processor Some review of numbers today Final Lecture Review: Focused on I/O Bring Examples we can look at and work on Lecture #28 25