Logic and Computer Design Fundamentals Chapter 9 Computer Design asics Part 2 A Simple Computer Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Part Datapaths Part 2 A Simple Computer Set Architecture (ISA) Single-Cycle Hardwired Control PC Function Decoder Example Execution Part 3 Multiple Cycle Hardwired Control Chapter 9 Part 2 2
Set Architecture (ISA) for Simple Computer (SC) A programmable system uses a sequence of instructions to control its operation An typical instruction specifies: Operation to be performed Operands to use, and Where to place the result, or Which instruction to execute next s are stored in RAM or ROM as a program The addresses for instructions in a computer are provided by a program counter (PC) that can Count up Load a new address based on an instruction and, optionally, status information Chapter 9 Part 2 3 Set Architecture (ISA) (continued) The PC and associated control logic are part of the Control Unit Executing an instruction - activating the necessary sequence of operations specified by the instruction Execution is controlled by the control unit and performed: In the datapath In the control unit In external hardware such as or input/output Chapter 9 Part 2 4 2
ISA: Storage Resources The storage resources are "visible" to the programmer at the lowest software level (typically, machine or assembly language) Storage resources for the SC => Separate instruction and data memories imply "Harvard architecture" Done to permit use of single clock cycle per instruction implementation Due to use of "cache" in modern computer architectures, is a fairly realistic model 2 5 x 6 Data 2 5 x6 Program counter (PC) Register file 8 x 6 Chapter 9 Part 2 5 ISA: Format A instruction consists of a bit vector The fields of an instruction are subvectors representing specific functions and having specific binary codes defined The format of an instruction defines the subvectors and their function An ISA usually contains multiple formats The SC ISA contains the three formats presented on the next slide Chapter 9 Part 2 6 3
ISA: Format 5 9 8 6 5 3 2 0 Opcode Destination register (DR) (a) Register Source register A (SA) Source register (S) 5 9 8 6 5 3 2 0 Opcode Destination register (DR) (b) Immediate Source register A (SA) Operand (OP) 5 9 8 6 5 3 2 0 Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) (c) Jump and ranch The three formats are: Register, Immediate, and Jump and ranch All formats contain an Opcode field in bits 9 through 5. The Opcode specifies the operation to be performed More details on each format are provided on the next three slides Chapter 9 Part 2 7 ISA: Format (continued) 5 9 8 6 5 3 2 0 Opcode Destination register (DR) Source register A (SA) Source register (S) (a) Register This format supports instructions represented by: R R2 + R3 R sl R2 There are three 3-bit register fields: DR - specifies destination register (R in the examples) SA - specifies the A source register (R2 in the first example) S - specifies the source register (R3 in the first example and R2 in the second example) Why is R2 in the second example S instead of SA? The source for the shifter in our datapath to be used in implementation is us rather than us A Chapter 9 Part 2 8 4
ISA: Format (continued) 5 9 8 6 5 3 2 0 Opcode Destination register (DR) Source register A (SA) Operand (OP) (b) Immediate This format supports instructions described by: R R2 + 3 The Source Register field is replaced by an Operand field OP which specifies a constant. The Operand: 3-bit constant Values from 0 to 7 The constant: ero-fill (on the left of) the Operand to form 6-bit constant 6-bit representation for values 0 through 7 Chapter 9 Part 2 9 ISA: Format (continued) 5 9 8 6 5 3 2 0 Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) (c) Jump and ranch This instruction supports changes in the sequence of instruction execution by adding an extended, 6-bit, signed 2s-complement address offset to the PC value The 6-bit Address (AD) field replaces the DR and S fields Example: Suppose that a jump is specified by the Opcode and the PC contains 45 (0 000) and Address contains 2 (000). Then the new PC value will be: 0 000 + ( 000) = 0 00000 (45 + ( 2) = 33) The SA field is retained to permit jumps and branches on N or based on the contents of Source register A Chapter 9 Part 2 0 5
ISA: Specifications The specifications provide: The name of the instruction The instruction's opcode A shorthand name for the opcode called a mnemonic A specification for the instruction format A register transfer description of the instruction, and A listing of the status bits that are meaningful during an instruction's execution (not used in the architectures defined in this chapter) Chapter 9 Part 2 ISA: Specifications (continued) TALE 9-8 Speci cations for the Simple Computer Opcode Mnemonic Format Description Status its MoveA 0000000 MOVA RD, RA R[DR] R[SA]* N, Increment 000000 INC RD, RA R[DR] R[SA] + * N, Add 000000 ADD RD, RA, R R[DR] R[SA] + R[S]* N, Subtract 00000 SU RD, RA, R R[DR] R[SA] R[S]* N, Decrement 00000 DEC RD, RA R[DR] R[SA] * N, AND 000000 AND RD, RA, R R[DR] R[SA] R[S]* N, OR 00000 OR RD, RA, R R[DR] R[SA] R[S]* N, Exclusive OR 00000 XOR RD, RA, R R[DR] R[SA] R[S]* N, NOT 0000 NOT RD, RA R[DR] RSA [ ]* N, Move 00000 MOV RD, R R[DR] R[S]* Shift Right 0000 SHR RD, R R[DR] sr R[S]* Shift Left 0000 SHL RD, R R[DR] sl R[S]* Load Immediate 0000 LDI RD, OP R[DR] zf OP* Add Immediate 00000 ADI RD, RA, OP R[DR] R[SA] + zf OP* N, Load 000000 LD RD, RA R[DR] M[SA]* Store 000000 ST RA, R M[SA] R[S]* ranch on ero 00000 R RA, AD if (R[SA] = 0) PC PC + sead, N, if (R[SA] 0) PC PC + ranch on 0000 RN RA,AD if (R[SA] < 0) PC PC + sead, N, Negative if (R[SA] 0) PC PC + Jump 0000 JMP RA PC R[SA] * For all of theseinstructions, PC PC+ is alsoexecutedto prepareforthenextcycle. Chapter 9 Part 2 2 6
ISA:Example s and Data in Memory Memory Representation of s and Data Deciimal Address Memory Contents Decimal Opcode Other Fields Operation 25 00000 00 00 0 5 (Subtract) DR:, SA:2, S:3 R R2 R3 35 000000 000 00 0 32 (Store) SA:4, S:5 M[R4] R5 45 00000 00 0 66 (Add Immediate) DR:2, SA:7, OP:3 R2 R7 + 3 55 00000 0 0 00 96 (ranch on ero) AD: 44, SA:6 If R6 = 0, PC PC 20 70 000000000000000 Data = 92. After execution ofinstruction in35, Data = 80. Chapter 9 Part 2 3 Single-Cycle Hardwired Control ased on the ISA defined, design a computer architecture to support the ISA The architecture is to fetch and execute each instruction in a single clock cycle The datapath from Figure 0- will be used The control unit will be defined as a part of the design The block diagram is shown on the next slide Chapter 9 Part 2 4 7
V C N ranch Control IR(8:6) IR(2:0) Extend PC Jump Address J L P C D A A A A Address decoder M F S IR(2:0) M R M D W W L P J ero fill C CONTROL RW DA AA Constant in FS V C N us A D Register file A A 0 MUX us Function unit F A M Address out Data out MW Data in Address Data Data out Data in MD us D 0 MUX D DATAPATH Chapter 9 Part 2 5 The Control Unit The Data Memory has been attached to the Address Out and Data Out and Data In lines of the Datapath. The MW input to the Data Memory is the Memory Write signal from the Control Unit. For convenience, the Memory, which is not usually a part of the Control Unit is shown within it. The Memory address input is provided by the PC and its instruction output feeds the Decoder. ero-filled IR(2:0) becomes Constant In Extended IR(8:6) IR(2:0) and us A are address inputs to the PC. The PC is controlled by ranch Control logic Chapter 9 Part 2 6 8
PC Function PC function is based on instruction specifications involving jumps and branches taken from Slide 3: ranchon ero R if (R[SA] = 0) PC PC+ se AD ranch on Negative RN if (R[SA] < 0) PC PC+ se AD Jump JMP PC R[SA] In addition to the above register transfers, the PC must also implement: PC PC + The first two transfers above require addition to the PC of: Address Offset = Extended IR(8:6) IR(2:0) The third transfer requires that the PC be loaded with: Jump Address = us A = R[SA] The counting function of the PC requires addition to the PC of Chapter 9 Part 2 7 PC Function (continued) ranch Control determines the PC transfers based on five of its inputs defined as follows: N, negative and zero status bits PL load enable for the PC J Jump/ranch select: If J =, Jump, else ranch C ranch Condition select: If C =, branch for N =, else branch for =. The above is summarize by the following table: PC Operation Count Up Jump ranch on Negative (else Count Up) ranch on ero (else Count Up) Sufficient information is provided here to design the PC PL 0 J X 0 0 C X X 0 Chapter 9 Part 2 8 9
Decoder The combinational instruction decoder converts the instruction into the signals necessary to control all parts of the computer during the single cycle execution The input is the 6-bit The outputs are control signals: Register file addresses DA, AA, and A, Function Unit Select FS Multiplexer Select Controls M and MD, Register file and Data Memory Write Controls RW and MW, and PC Controls PL, J, and C The register file outputs are simply pass-through signals: DA = DR, AA = SA, and A = S Determination of the remaining signals is more complex. Chapter 9 Part 2 9 Decoder (continued) The remaining control signals do not depend on the addresses, so must be a function of IR(3:9) Formulation requires examining relationships between the outputs and the opcodes given in Slides 2 and 3. Observe that for other than branches and jumps, FS = IR(2:9) This implies that the other control signals should depend as much as possible on IR(5:3) (which actually were assigned with decoding in mind!) To make some sense of this, we divide instructions into types as shown in the table on the next page Chapter 9 Part 2 20 0
Decoder (continued) Truth Table for Decoder Logic its Control Word its Function Type 5 4 3 9 M MD RW MW PL J C Function unit operations using 0 0 0 X 0 0 0 0 X X registers Memory read 0 0 X 0 0 0 X X Memory write 0 0 X 0 X 0 0 X X Function unit operations using 0 0 X 0 0 0 X X register and constant Conditional branch on zero () 0 0 X X 0 0 0 0 Conditional branch on negative (N) 0 X X 0 0 0 Unconditional Jump X X X 0 0 X Chapter 9 Part 2 2 Decoder (continued) The types are based on the blocks controlled and the seven signals to be generated; types can be divided into two groups: Datapath and Memory Control (First 4 types) PC Control (Last 3 types) In Datapath and Memory Control blocks controlled are considered: Mux (st and 4th types) Memory and Mux D (2nd and 3rd types) y assigning codes with no or only one for these, implementation of M, MD, RW and MW are simplified. In Control Unit more of a bit setting approach was used: it 5 = it 4 = were assigned to generate PL it 3 values were assigned to generate J. it 9 was use as C which contradicts FS = 0000 needed for branches. To force FS(6) to 0 for branches, it 9 into FS(6) is disabled by PL. Also, useful bit correlations between values in the two groups were exploited in assigning the codes. Chapter 9 Part 2 22
Decoder (continued) The end result by use of the types, careful assignment of codes, and use of don't cares, yields very simple logic: This completes the Opcode DR SA S design of most of the 5 4 3 2 0 9 8 6 5 3 2 0 essential parts of the single-cycle simple computer 9 7 6 4 3 0 9 6 5 4 3 2 0 DA AA A M FS MD RW MW PL J C Control word Chapter 9 Part 2 23 Example Execution Six s for the Single-Cycle Computer Operation Symbol ic code name Format Description Function MMD RW MW PL J C 00000 ADI Immediate Add immediate R[ DR] R[ SA] + zf I(2:0) 0 0 0 0 0 operand 000000 LD Register Load R[ DR] M [ R [ SA] ] 0 0 0 0 content into register 000000 ST Register Store register M [ R[ SA] ] R[ S] 0 0 0 0 0 content in 0000 SL Register Shift left R[ DR] sl R[ S] 0 0 0 0 0 0000 NOT Register Complement R[ DR] R[ SA] 0 0 0 0 0 register 00000 R Jump/ranch If R[SA] = 0, branch If R[SA] = 0, 0 0 0 0 0 to PC + se AD PC PC + se AD, If R[SA] 0, PC PC + Decoding, control inputs and paths shown for ADI, RD and R on next 6 slides Chapter 9 Part 2 24 2
Decoding for ADI 0 0 0 0 0 Opcode DR SA S 5 4 3 2 0 9 8 6 5 3 2 0 9 7 DA 6 4 AA 3 A 0 9 6 5 4 3 2 0 0 0 0 0 0 0 0 0 M FS MD RW MW PL J C Control word Chapter 9 Part 2 25 V CN ranch Control PC IR(8:6) IR(2:0) Extend Control Inputs and Paths for ADI J L P C 0 00 Increment PC D A A A A Address decoder ero fill IR(2:0) M F M R M J S D W W L P C 0 CONTROL 0 0 0 0 0 0 0 RW DA AA Constant in 0 0 0 FS V C N us A D Register file A A 0 MUX us + Function unit F A M Address out Data out 0 MW Data in Address Data Data out Data in No Write 0MD us D 0 MUX D DATAPATH Chapter 9 Part 2 26 3
Decoding for LD 0 0 0 0 0 0 Opcode DR SA S 5 4 3 2 0 9 8 6 5 3 2 0 9 7 DA 6 4 AA 3 A 0 9 6 5 4 3 2 0 0 0 0 0 0 0 0 0 M FS MD RW MW PL J C Control word Chapter 9 Part 2 27 V CN ranch Control PC IR(8:6) IR(2:0) Extend Control Inputs and Paths for LD J L P C 0 0 Increment PC D A A A A Address decoder ero fill IR(2:0) M F M R M J S D W W L P C 0 CONTROL 0 0 0 0 0 0 0 RW DA AA Constant in 0 0 0 0 FS V C N us A D Register file A A 0 MUX us Function unit F A M 0 Address out Data out 0 MW Data in Address Data Data out Data in No Write MD us D 0 MUX D DATAPATH Chapter 9 Part 2 28 4
Decoding for R 0 0 0 0 0 Opcode DR SA S 5 4 3 2 0 9 8 6 5 3 2 0 9 7 DA 6 4 AA 3 A 0 9 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 M FS MD RW MW PL J C Control word Chapter 9 Part 2 29 V CN ranch Control J L P C 0 0 ranch on D A A A A Address IR(8:6) IR(2:0) Extend decoder ero fill IR(2:0) M F M R M J S D W W L P C 0 0 CONTROL 0 0 0 0 0 0 0 PC 0 RW DA AA Constant in 0 0 0 0 FS V C N Control Inputs and Paths for R us A No Write D Register file A A 0 MUX us Function unit F A M Address out Data out 0 MW Data in Address Data Data out No Write Data in 0MD us D 0 MUX D DATAPATH Chapter 9 Part 2 30 5
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