The Engine & DRAM Endurance and Speed with STT MRAM Les Crudele / Andrew J. Walker PhD August 2018 1
Contents The Leaking Creaking Pyramid STT-MRAM: A Compelling Replacement STT-MRAM: A Unique Endurance Conundrum The ENGINE for & DRAM Endurance and Speed The Physics of the ENGINE ENGINE Emulation Data from Emulated ENGINE ENGINE Benefits Takes MRAM Mainstream! The Performance, Energy and Cost Advantage Conclusions August 2018 2
Nonvolatile Volatile The Leaking Creaking Pyramid (1) Leakage Current (ma) CPU Gap DRAM Mind the Gap NAND DISK Cell Area in F 2 FinFET Inefficient Scaling* Planar CMOS Technology Node F (nm) Fundamental Leakage** 1000 Mb 200 Mb 100 Mb 50 Mb 20 Mb 10 Mb * R. de Werdt et al., IEDM87; R.D.J. Verhaar et al., IEDM90; S.H. Kang et al., IEDM17 Temperature ( o C) August 2018 ** Simulations/estimates from 7nm transistor data in IEDM 2017 3
The Leaking Creaking Pyramid (2) Energy per Operation (pj) GigaOperations per Joule CPU On-chip data access Keep Data Local! On-chip data access Operation Off-chip data access * What We Get for a Joule * Gap DRAM Off-chip data access Operation Memory access energy grows as the length of the wire * > 60% of system energy used is in data movements to and from DRAM ** * A. Pedram et al., Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era, IEEE Design & Test, vol.34, April 2017 ** A. Boroumand et al., Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks, ASPLOS 18, March 2018 August 2018 4
STT-MRAM : A Compelling Replacement Size : Dramatic bitcell reduction Leakage : No array leakage Persistence : Data retained On-chip : Reduces DRAM accesses Rad-Hard Cell Area in F 2 MRAM FinFET Planar But: Limiting Endurance Conundrum Non-symmetric R/W CMOS Technology Node F (nm) Disturbs with fast read August 2018 5
Write Error Rate STT-MRAM: A Unique Endurance Conundrum Magnetic Tunnel Junction (MTJ) Free layer Tunnel barrier Reference layer CoFeB MgO CoPt The Stochastic Top Hat Pulse width Low Write Error Rate needs large tunnel current Limits endurance due to oxide wear out mechanism High endurance with low Write Error Rate needs reduced tunnel current Make Free Layer magnetically less stiff Reduce MTJ area Use special design techniques - The ENGINE MTJ Voltage (V) August 2018 6
Write Error Rate Log(Write Error Rate) The Physics of the ENGINE The Stochastic Top Hat Pulse width Increased WER Reduced electrical stress MTJ Voltage (V) MTJ Voltage (V) Proprietary Circuit Design allows reduced electrical stress Results in large endurance increase (~ 6 orders of magnitude) Circuit Deals with resultant Write Error Rate increase Managed transparently to the user No change in latency Allows for faster pulses at high endurance August 2018 7
ENGINE Emulation Emulation Board (FPGA emulation of Engine) Front Panel (Control timing, address, patterns, W/R ops etc.) Daughter Board (Contains SPIN s own 4Mb STT-MRAMs) Logic Analyzer (Verify addresses, timing, patterns, W/R etc.) August 2018 8
Write Error Rate Cycles to Breakdown Data from Emulated ENGINE 20ns Engine OFF Engine ON 380 mv Voltage (V) Voltage (V) ~ 6 orders of magnitude endurance boost August 2018 9
ENGINE Benefits Takes MRAM Mainstream! /DRAM-like Endurance ~ 6 orders of magnitude improvement with circuitry alone Symmetric R/W 10ns capable Random R/W Looks and feels like an Corrects Read Disturbs allowing Fast Reads No user visible errors August 2018 10
Macro Area Impact versus (%) The Performance, Energy and Cost Advantage 7nm CMOS node Macro Capacity MRAM Cell Cell 140F 2 560F 2 Dramatic area impact Maximize large on-chip cache and memory capacity Allows persistence on-chip Reduces DRAM accesses ~ Zero array leakage Symmetric Read/Write August 2018 11
Conclusions The ENGINE takes MRAM into the mainstream Provides a path for MRAM as /DRAM replacement Uses evolving ecosystem for embedded NV MRAM as a foundation Combines low Write Error Rates with /DRAM-like endurance resulting in zero user-visible errors Achieves fast and symmetric read and write Makes MRAM the most likely candidate for replacement and, eventually, DRAM August 2018 12