Design of FPGA Based Radix 4 FFT Processor using CORDIC

Design of FPGA Based Radix 4 FFT Processor using CORDIC Chetan Korde 1, Dr. P. Malathi 2, Sudhir N. Shelke 3, Dr. Manish Sharma 4 1,2,4 Department of Electronics and Telecommunication Engineering, DYPCOE, Akurdi, Pune, India 3 Research Division, JDM Design Technology, Nagpur, India chetan.cik@gmail.com 1, malathijesudason@ymail.com 2, sudhirshelke1976@gmail.com 3, manishsharma.mitm@gmail.com 4 Abstract - The Fast Fourier Transform (FFT) is an efficient algorithm for computing the Discrete Fourier Transform and requires less number of computations than that of direct evaluation of Discrete Fourier Transform (DFT). It has several applications in signal processing. But, because of the complexity of the processing algorithm of FFT, recently various radix-r FFT algorithms have been proposed to meet real-time processing requirements and reduce hardware complexity. The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment. The main requirement of these systems is low power FFT architectures. This work proposes design of FFT processor using Coordinate Rotation Digital Computer (CORDIC) algorithm to reduce complexity of hardware and improve performance of processing, which will be synthesized on Field Programmable Gate Array. The purpose of this work is to obtain an area efficient description of FFT processor. Keywords - FFT, Radix 4, Radix 2, CORDIC, VHDL, FPGA. 1. INTRODUCTION The Digital signal processing has been dominated by microprocessors, because of some design feature enhancements in microprocessor like Special addressing modes and single cycle multiply-accumulate instructions. Though microprocessors are more flexible with low cost, but they are not fast enough for Digital Signal Processing (DSP) tasks. The arrival of reconfigurable logic computers offers hardware solutions for higher speed at cost which are less than traditional software approach. Unfortunately, algorithms used for these microprocessor based systems cannot be mapped into hardware. In such hardware efficient algorithms, there is a class of solutions for trigonometric functions that uses shifts and additions in its operation. The trigonometric functions are calculated by using vector rotations, while other functions like square root are realized by using an incremental expression. So, implementation of all these function in the hardware is difficult. In digital signal processing and communication systems, Discrete Fourier Transform (DFT) is one of the core operations. Many fundamental algorithms can be realized by DFT, such as spectrum estimation, correlation and convolution etc. Furthermore, DFT is widely used in standard embedded system applications such as wireless communication protocols requiring Orthogonal Frequency Division Multiplexing, Radar image processing using Synthetic Aperture Radar and Software Defined Radio etc. But, because of computational complexity of DFT it is difficult to implement. In practice, Fast Fourier transform (FFT) is used for reducing the complexity of computations. For FFT processors, butterfly operation is the most computationally demanding stage. Traditionally, a butterfly unit is composed of complex adders and multipliers. These multipliers are usually the speedup bottleneck in the pipeline of the FFT processor. The CORDIC algorithm is an alternative method to realize the butterfly operation without using any dedicated multiplier hardware. The CORDIC algorithm is versatile and hardware efficient since it requires only addition and shift operations, which makes FFT's butterfly operations more suitable. This CORDIC algorithm is further used in Radix-4 FFT for faster computation. While converting samples taken in real time into equivalent frequency domain samples, FFT computation is used in which twiddle factor computation is done using CORDIC algorithm. By the use of this CORDIC-based FFT processor, only twiddle factor angles of butterfly operation will store in a ROM and no need to store actual twiddle factors in a ROM, so memory requirement will be reduced automatically. Vol. 5(1), Jan June 2015@ ISSN 2249-9946 56

The Coordinate Rotation Digital Computer algorithm is a well-known technique to perform various basic arithmetic operations including trigonometric function computation, vector magnitude estimation, polar to rectangular conversions etc. Also for so many applications CORDIC processing units is used to deliver superior performance when compared with more conventional approaches. This is due to the fact that many advanced algorithms can be interpreted as generalized computation, for which CORDIC is especially suited to. So, the CORDIC algorithm is used to realize butterfly operation of FFT, which eliminates the need for storing twiddle factors and only need to store its angle, which helps to save a lot of hardware compared to its counterparts employing other techniques. It is preferred due to its simple operations, low cost and less complexity. Conventional CORDIC-based FFT processor needs a dedicated memory bank to store the necessary twiddle factor angles for the rotation. This study proposes a modified CORDIC algorithm for FFT processors which eliminates the need for storing the twiddle factor angles. With this approach, memory requirements of an FFT processor can be reduced. Memory reduction improves with the increased radix size. Furthermore, the angle generation circuit consumes less power consumption than angle memory access. Hence, system throughput will not change by using modified CORDIC angle calculation. Fig. 1 16 point Radix-4 FFT DIT algorithm [9] 2. RADIX-4 FFT ALGORITHM Radix-4 algorithm makes use of 4 as their base. They can be seen to be special case of Radix-2 algorithms. With Radix-4 algorithms, the number of computations involved gets reduced considerably, compared with the Radix-2 algorithm. Figure (1) shows an example of Radix-4 Decimation in Time (DIT) method used for N=16 points FFT algorithm. As shown in FFT flow-graph inputs are in normal order while the outputs are in digit-reversed order. At input side the samples are taken from time domain which are processed with Radix-4 FFT and get equivalent components in frequency domain. The numbers over flow lines indicates the twiddle factor to be multiplied with the samples. A Radix-r FFT uses N/r Radix-r butterflies for each stage and has log r (N) stages. For example, in this case for 16 point Radix-4 FFT requires k=2 stages. Fig. 2 The basic butterfly operations for stage 1 Radix-4 FFT algorithm. Figure (2) (a) and (b) shows the basic butterfly structure of Radix-4 which have four inputs and four outputs, inputs are as x(n), x(n + N/4), x(n + N/2) and x(n + 3N/4) outputs are in digit reversed order X(k). The signal flow graph of Radix-4 DIT butterfly operation is illustrated in figure (3). Radix-4 algorithms have a computational advantage over Radix-2 algorithms because one Radix-4 butterfly does the work of four Radix-2 butterflies and Radix-4 butterflies requires only three complex multipliers compared to four complex multipliers of four Radix-2 butterflies. The arithmetic kernel of Radix- 4 DIT FFT is the buttery operation defined as Vol. 5(1), Jan June 2015@ ISSN 2249-9946 57

X 0 = P0 +W 1 +W 2 +W 3. (1) X 1 = P0 - jw 1 - W 2 + jw 3. (2) X 2 = P0 - W 1 + W 2 - W 3. (3) X 3 = P 0 + jw 1 - W 2 - jw 3. (4) implementations, CORDIC enables most of the code and data to be shared between routines for trigonometric and hyperbolic functions, helping to conserve memory. CORDIC algorithm is often used to implement rotations needed in modulators and demodulators. Here, CORDIC is used to calculate sine and cosine term of twiddle factor. CORDIC works by rotating the coordinate system through constant angles until the angle is reduces to zero. The angle offsets are selected such that the operations on X and Y are only shifts and adds. CORDIC algorithm performs a planar rotation. Graphically, planar rotation means transforming a vector (Xi, Yi) into a new vector (Xj, Yj). [11] Figure (3): Signal flow graph of Radix-4 DIT butterfly 3. CORDIC In 1959, Jack E. Volder introduces The CORDIC algorithm for implementing a real-time navigation computer for aeronautical applications. The algorithm was initially formulated for computing the values of trigonometric functions. In early 1970s the CORDIC techniques were extended to exponential, logarithmic, forward and inverse circular and hyperbolic functions, ratios and square roots etc., (Walther 1971). Its concepts have also been developed to include calculation of the Discrete Fourier Transform (Despain 1974). More recently (Bajard 1994) efficient hardware technique known as BKM for computing complex exponentials and trigonometric functions was proposed and has since been very widely applied.[7] In contrast, CORDIC algorithms need only adders, shifters and comparators for computing a wide range of elementary functions. The method is especially efficient when fixed point implementations of signal processing algorithms on hardware are considered. For example, CORDIC is extremely popular in hardware accelerators and also in SIMD realizations. Furthermore, almost all functional calculators employ CORDIC. Also, CORDIC is a good choice for hardware solutions such as FPGA in which cost (gate count) minimization is more important than throughput maximization. In software Figure (4): Rotate vector (Xi, Yi) to (Xj, Yj) Using a matrix form, a planar rotation for a vector of (Xi, Yi) is defined as (5) The angle rotation can be executed in several steps, using an iterative process. Each step completes a small part of the rotation. Many steps will compose one planar rotation.[11] A single step is defined by the following equation (6) Equation (6) can be modified by eliminating the factor (7) Equation (7) requires three multiplies, compared to the four needed in equation 6. Additional multipliers can be eliminated by selecting the angle steps such that the tangent of a step is a power of 2. [11] Multiplying or dividing by a power of 2 can be implemented using a Vol. 5(1), Jan June 2015@ ISSN 2249-9946 58

simple shift operation. The angle for each step is given by (8) All iteration-angles summed must equal the rotation angle. Where, (9) (10) (16) At this point a new variable called 'Z' is introduced. Z represents the part of the angle which has not been rotated yet. (17) For every step of the rotation Sn is computed as a sign of Zn. (18) This results in the following equation for Combining equation (7) and (11) results in (11) (12) By combining equations (9) and (18) results in a system which reduces the not rotated part of angle to zero. Sine and Cosine can be calculated using the first CORDIC scheme which calculates By using the following values as inputs (19) Besides for the coefficient, the algorithm has been reduced to a few simple shifts and additions. The coefficient can be eliminated by pre-computing the final result. The first step is to rewrite the coefficient. (13) The second step is to compute equation (13) for all values of 'n' and multiplying the results, which we will refer to as K. (14) is constant for all initial vectors and for all values of the rotation angle. It is normally referred to as the congregate constant. The derivative P (approx. 1.64676) is defined here because it is also commonly used. We can now formulate the exact calculation the CORDIC performs. [11] (15) Because the coefficient K is pre-computed and taken into account at a later stage, equation 12 may be written as (20) Y i = 0 (21) Z i = 0 (22) Then, the core calculates (23) The input Z takes values from -180degrees to +180 degrees where, 0x8000 = -180 degrees 0xEFFF = +180 degrees But the core only converges in the range -90 degrees to +90 degrees. The other inputs and the outputs are all in the range of -1 to +1. The congregate constant P represented in this format results in: (24) For example, calculate sine and cosine term for 45 degrees. First the angle has to be calculated 360 o = 2 26 (For 360 degree rotaion) So for, 1 = 24 2 360 Vol. 5(1), Jan June 2015@ ISSN 2249-9946 59

Therefore for 45 o, Then, core will calculates the following sine and cosine values for Zi = 8192, Sin: 23170 (dec) = 5A82 (hex) Cos: 23171 (dec) = 5A83 (hex) Table (2): List of IO Ports for Sine/Cosine CORDIC Core PORT WIDTH DIRECTION DESCRIPTION CLK 1 INPUT SYSTEM CLOCK ENA 1 INPUT CLOCK ENABLE SIGNAL AIN 16 INPUT ANGLE INPUT COS 16 OUTPUT COSINE OUTPUT SIN 16 OUTPUT SINE OUTPUT The outputs represent values in the -1 to +1 range. The results can be derived as follows 2 15 = 1.0 Table (1) shows angle calculation for some common values of degree. Although the core is very accurate small errors can be introduced by the algorithm (see example and results table). This should be only a problem when using the core over the entire output range, because the difference between +1 (0x7FFF) and -1 (0x8000) is only 1bit.[11] Table 1: Sin/Cos outputs for some common angles 0 30 45 60 90 SIN 0X01CC 0X3FFC 0X5A82 0X6EDC 0X8000 COS 0X8000 0X6EDD 0X5A83 0X4000 0X01CC SIN 0.01403 0.49998 0.70709 0.86609 1.00000 COS 1.00000 0.86612 0.70712 0.50000 0.01403 Fig. 6 RTL view of sine and cosine generation unit of CORDIC 1.1 CORDIC simulation 4. SIMULATION RESULT By using VHDL, CORDIC is synthesize and simulated on Altera cyclone II FPGA development board. So, proposed CORDIC is shown as Fig. 5 PIN diagram of Sine/Cosine CORDIC Core Fig. 7 Compilation report of CORDIC 1. For Angle 0 degree, Sin and Cos shows the desired results at the 15th clock pulse. Timeline shows the span of 15 clock pulses. Vol. 5(1), Jan June 2015@ ISSN 2249-9946 60

Fig. 8 Simulation result for 0 Degree. 2. Angle 30 degrees. (1555 Hex) Fig. 9 Simulation result for 30 Degree Now angles are provided at every clock pulse to show the pipeline strategy. So the output for the 45 degrees angle will take 15 clock pulses and then the output changes at every next pulse for the next four input angles. Fig. 11 RTL view of Radix 4 FFT using CORDIC 4.3 Result Summary From above simulation results this work concluded in the following table Table 3 : Summary of FPGA implementations of Radix 4 FFT using CORDIC algorithm. Fig. 10 Simulation result for all Degree values (0, 30, 45, 60, and 90) 4.2 Simulation of Radix 4 FFT using CORDIC Parameter Number of used memory Slices/Area Core Dynamic Power Static Power Clock Frequency Throughput Throughput/Area = Xilinx ISE 14.7 Value 32/3360 (1%) 1092/12480 (8%) 0.010 W 0.321 W 364.679 M Hz 1.717 GB/sec 0.1 MB/sec From above Table, can concluded that the Radix 4 FFT using CORDIC on Xilinx xc5vlx20t-2ff323 of Vertex 5 family gives optimized area of 1092(8%) slices, Core dynamic power 0.010 w, 1.717 Gb/sec of throughput and clock frequency of 364.679 MHz. 5. APPLICATIONS Fig. 11: Summary report of Radix 4 FFT using CORDIC 1. Television terrestrial broadcasting systems. 2. Phase correlation system. 3. Mobile receiver. Vol. 5(1), Jan June 2015@ ISSN 2249-9946 61

4. Implementation of digital communication system. 4. Fault characterization and classification. 6. Radar. 7. Medical Imaging a. X-ray computed tomography (CT). b. Magnetic Resonance Imaging (MRI). 6. CONCLUSION Radix-4 FFT processor using CORDIC architecture is proposed. For generation of twiddle factor CORDIC algorithm is used which helps to reduce memory size. Various parts of FFT architecture such as Butterfly unit, CORDIC model are discussed. Proposed research work emphasize on the use of techniques to reduce the computational complexity of processor design and algorithm used which result into improvement of the design significantly. REFERENCES [1] Yasodai A., Ramprasad A. V., "A new memory reduced Radix-4 CORDIC processor for FFT operation", IOSR Journal of VLSI and Signal Processing, Volume 2, Issue 5, May-Jun 2013. [2] V. Charishma, K. Sreekanth Yadav, Neelima koppala. "Design and simulation of 64 Point FFT using Radix 4 algorithm for FPGA implementation", International Journal of Engineering Trends and Technology, Volume 4, Issue 2, 2013. [3] M. Vidya, M. Vijaya kumar, G. Sriramulu. "Design and VLSI implementation of a radix-4 64-point FFT processor", International Journal of Research in Computer and Communication technology, Volume 1, Issue 7, December 2012. [4] A. S. Padekar, S. S. Belsare, "Design of a CORDIC based radix-4 FFT processor", International Journal of Computer Science and Information Technologies, Volume 5, 2014. [5] Hsi-Chin, Hsin Tze-Yun Sung, Lu-Ting Ko, "Reconfigurable VLSI architecture for FFT processor", WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Volume 8, Issue 6, June 2009. [6] Javier Valls, "The use of CORDIC in software defined radios: A tutorial", Sep 2006. [7] J. E. Volder. "The CORDIC trigonometric computing technique", IEEE Communications Magazine, Volume 8, 1959. [8] Erdal Oruklu, Xin Xiao and Jafar Saniie, "Reduced memory and low power architectures for CORDICbased FFT processors", Springer Science and Business Media, pp. 129-134, 16 April 2011. [9] Ajay S. Padekar, Prof. S. S. Belsare, "Radix-4 FFT Architecture", International Journal of Advanced Research in Computer Science and Software Engineering, Volume 4, Issue 5, May 2014. [10] Wang Mingxing, Shi Jiangi, Tian Yinghui, Yang Zhe, "A Novel design of 1024-point pipelined FFT processor based on CORDIC algorithm", Intelligent System Design And engineering Application (ISDEA) 2012 second International Conference on Digital Object Identifier, pp. 80-83, 2012 [11] Richard Herveille, "Cordic Core Specification", Rev. 0.3, 11-June-15. Vol. 5(1), Jan June 2015@ ISSN 2249-9946 62