Grades: 20% of the final grade. CDA 3103 Computer Organization Exam 2 Solution Set Name: USF ID: Problem Points Your Points 1 10 2 10 3 20 4 10 5 15 6 15 Total 80 Exam Rules Close book, notes and HW. Only the exam paper is allowed. All electronics must be turned o. Show all work to get partial credits except yes/no problems. Use the back of the exam paper as necessary. But indicate clearly which problems that the answers on the back correspond to. Make sure that your writing is legible; otherwise you grades may be adversely a ected. Additional information that might be necessary is shown at the end of the exam paper. 1
Problem 1 (10 pts) Consider the following logic circuit. 1. Find the corresponding Boolean expression in a simplified form. F = (xy + z 0 )(y + z) 0 = (xy + z 0 )y 0 z 0 = y 0 z 0 2. Implement the simplified Boolean expression from the previous step using 2-inputs NOR gates only. Show the circuit diagram. Since y 0 z 0 =(y + z) 0, the circuit consists of a single 2-input NOR gate with inputs y and z and the output F. Problem 2 (10 pts) Consider the following sequential circuit with the characteristic table for JK flip flop is shown on the right. X Y Clock J K Q(t +1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q 0 (t) The following table shows a sequence of inputs for the above sequential circuit in each clock cycle. Complete the table. Q =0intheinitialstate. X Y Q(t) Q(t +1) 1 1 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 2
Problem 3 (20 pts) Suppose that a 4K 32 memory is given. 1. What is the word size of this memory? 32 bits 2. If this memory is word-addressable, how many address bits are required? What is the highest address? There are 4K words, so the total number of address lines is 12 bits. The highest address is 2 12 1. 3. If the memory is byte-addressable, how many address bits are required? what is the highest address? There are 4K 4 bytes, so the total number of address lines is 14 bits. The highest address is 2 14 1. 4. Suppose this memory is word-addressable, and it is constructed by connecting 512 32 RAM chips. Also suppose that this memory organization uses the high-order interleaving, which bits, among all address bits, are used for chip selection? Which bits, among all address bits, are used for o set on a chip? 8512 32 RAM chips are needed to build the 4K 32 memory. 3 address lines are used to select chips. Since each RAM chip has 512 addressable words, 9 address lines are needed for chip o set (selecting a word from a RAM chip. In case that the memory is organized using high-order interleaving, address bits 11 9areusedaschipselect,andaddressbits8 0areusedaschipo set. Problem 4 (10 pts) Consider the following instruction that appears at memory address 102 in an assembly program. After this instruction is executed, Hex Address Instruction... 102 JnS 10C... (a) What is the value of PC? (b) What is stored at memory location 10C? 10D 103 3
Problem 5 (15 pts) Execute the following program, and fill in the blanks for registers PC and AC, and the memory location M[A] andm[one] aftereachinstructionisexecuted. Their initial values are filled in the first row of the table. Address Label Instruction PC AC M[A] M[One] 100 23 1 100 Load A 101 23 23 1 101 Add One 102 24 23 1 102 Jump S1 106 24 23 1 103 S2, Add One 107 47 23 1 104 Store A 103 47 23 1 105 Halt 104 48 23 1 106 S1, Add A 105 48 48 1 107 Jump S2 106 48 48 1 108 A, DEC 23 108 One, DEC 1 Problem 6 (10 pts) Translate the following high-level program to the MARIE assembly program. Assume that X, Y, and Z are memory locations where some data are stored. Also assume that the first instruction of your assembly program is stored at memory address 100. if X <= Y then Z = X - Y; else Z = Z+1; endif; Load X Subt Y Skipcond 400 Jump Else Jump End Else, Load Z Add One End, Store Z Halt One, DEC 1 4
MARIE s Instruction Set Opcode Binary Hexdecimal Instruction RTN 00010 0 JnS X MBR PC MAR X M[MAR] MBR MBR X AC 1 AC AC + MBR PC AC 0001 1 Load X MAR X AC MBR 0010 2 Store X MAR X MBR AC M[MAR] MBR 0011 3 Add X MAR X AC AC + MBR 0100 4 Subt X MAR X AC AC MBR 0101 5 Input AC InReg 0110 6 Output OutReg AC 0111 7 Halt 1000 8 Skipcond X if IR[11 10] =00then if AC < 0thenPC PC +1 if IR[11 10] =01then if AC =0thenPC PC +1 if IR[11 10] =10then if AC > 0thenPC PC +1 1001 9 Jump X PC IR[11 0] 1010 A Clear AC 0 1011 B AddI X MAR X MAR MBR AC AC + MBR To be continued on the next page 5
MARIE s Instruction Set (continued) Opcode Binary Hexdecimal Instruction RTN 1100 C JumpI X MAR X PC MBR 1101 D LoadI X MAR X MAR MBR AC MBR 1110 E StoreI X MAR X MAR MBR MBR AC M[MAR] MBR 6
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