RAiO 128x33 Dot Matrix LCD Driver Specification Version 1.1 March 2, 2006 RAiO Technology nc. Copyright RAiO Technology nc. 2005, 2006 RAiO TECHNOLOGY NC. 1/6 www.raio.com.tw
1. General Description The is a Dot-Matrix LCD Driver. The embedded 528Byte display RAM supports up to 128x33 dots LCD panel. The also provides a scrolling buffer memory for scrolling functions. t supports up, down, left and right scrolling features, and all of the scrolling functions are execute by hardware. The integrates many powerful hardware that including Contrast adjustment, 4x5 Key-Scan, eight General Purpose /O and EL Backlight signals for EL driver. The is a high integration chip of LCD ler. t reduce a lot of time for system develop, and save much cost for hardware system that due to it provides many features for related LCD display application. 2. Feature Support 8080/6800 8/4-bit Parallel nterface and 3-wire/4-wire Serial nterface Support Maximum 128Seg x 33Com LCD Panel. Built-in 528 Bytes Display RAM and 354Byte Scrolling Buffer Built-in 2X~3X(Voltage Booster), Voltage Regulator, Voltage Follower Support 1/33 Duty, 1/6~1/4 Bias Panel Eight General Purpose /O Built-in 4x5 Key Scan Circuit Support Horizontal/Vertical Scrolling Functions Provide Signals for EL Driver Provide 32-Steps Contrast Adjust Build-in RC Oscillator Voltage Operation : 2.6~3.6V Package : Gold Bump Die 3. System Block Diagram MPU LCD Panel GPO EL Back Light Driver 4 x 5 Key Scan 4. Pad and Package con 128x32 COG FPC #N #1 COG Module RAiO TECHNOLOGY NC. 2/6 www.raio.com.tw
258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 COM4 COM3 COM2 COM1 COM0 COMS_A1 COMS_A0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 1 2 3 4 5 6 7 8 9 10 11 Logo P1 Top View (8758µm x 1148 µm ) Y (0, 0) X P2 116 COM23 115 COM24 114 COM25 113 COM26 112 COM27 111 COM28 110 COM29 109 COM30 108 COM31 107 COMS_B0 106 COMS_B1 C2M C2M C2P C2P C1M C1M C1P C1P P P P S1 FG S0 VREF VREF DB7, SMOD1 DB6, SMOD0 DB5 DB4 DB3, CS DB2, RS, SD DB1, SDA, SDO DB0, SCL RD, EN WR, R/W D/C, RS CS C86 BT4 P/S NT EXT_CLK CLK_SEL KST3 KST2 KST1 KST0 KN4 KN3 KN2 KN1 KN0 O7 O6 O5 O4 O3 O2 O1 O0 EL_CHRG EL_DCHG RST TEST2 TEST1 TEST0 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 5. Block Diagram The consists of Display RAM, Command Registers, LCD ler, LCD Driver, Voltage Booster, Voltage Regulator, MPU nterface and Key-Scan circuit. DB[0:7] RD(EN) WR(R/W) CS D/C(RS) MPU /F Block 528bytes Display RAM + Buffer C86 BT4 LCDC Block P/S KST[3..0] KN[4..0] NT Key Scan Block & NT Register Block Cursor Scroll Driver /F Scan O[7..0] EL_CHRG GPO EL_DCHG CLK_SEL EXT_CLK RC Oscillator Voltage Voltage Regulator Voltage Follower VREF RST Booster TEST[2..0] FG S[1:0] Test & Power Circuit 128 Segment Drivers 33 Common Drivers C[2:1]P C[2:1]M ~ SEG0~SEG127 COM0~COM31 COMS_A[1:0] COMS_B[1:0] RAiO TECHNOLOGY NC. 3/6 www.raio.com.tw
6. Pin Definition 5-1 MPU nterface Pin Name /O Description Data Bus When the MPU use parallel mode and 8-bit then all of the DB[7:0] are valid. When use 4-bit then only DB[4:0] are valid, and DB[7:4] have to keep floating. When P/ S is 0, then the interface between MPU and is Serial Mode. The pins DB[7:6](SMOD[1:0]) are used to select which serial mode: DB[7..0] DB0: SCK DB1: SDA/SDO DB2: RS/SD DB3: CS DB[7:6]: SMOD R/ EN D/ RS CS /O O SMOD : Serial Mode ----------------------------------------------------------------- 0 X : 3-Wire, SCK, SDA, are used. 1 0 : 4-Wire, SCK, SDA, RS, are used. 1 1 : 4-Wire, SCK, SDO, SD, CS are used. n serial mode, all of the related signals are defined by DB[3:0]: SCK(DB0) : Serial Clock. SDA(DB1) : Bi-direction Mode Serial Data. SDO(DB1) : Data Out. RS(DB2) : Memory/Register Cycle Select. SD(DB2) : Serial Data n. CS (DB3) : Chip Select, active low. The unused pin must keep NC for serial mode. Read or Enable When use 8080 series interface, is the read signal and active low. When use 6800 series interface, EN is the Enable signal and active high. Connect this pin to for serial mode. Write or Read-Write When use 8080 series interface, is the write signal and active low. When use 6800 series interface, this pin is R/, active high for read cycle and active low for write cycle. Connect this pin to for serial mode. Data/Command Select or Register Select) When use 8080 series interface, this is Data or Command signal. When D/ C is 0, means Register Cycle(or Command Cycle). When D/ C is 1, means Data Access Cycle(Data Cycle). When use 6800 series interface, this is the RS signal. When RS is 0, means Register Cycle and 1 means Data Access Cycle. Connect this pin to for serial mode. Chip Select This is a chip enable for. Connect this pin to for serial mode. nterrupt Signal This is an interrupt output for MPU. Active low RAiO TECHNOLOGY NC. 4/6 www.raio.com.tw
MPU Select BT4 P/ S C 86 = 0 The MPU interface is 8080 series. C 86 = 1 The MPU interface is 6800 series(default). Connect this pin to for serial mode. Data Bit Select BT4 = 0 The parallel mode is use 8-bit data bus. BT4 = 1 The parallel mode is use 4-bit data bus(default). Connect this pin to for serial mode. Parallel/Serial Select P/ S = 0 The MPU interface is serial mode(default). See the setting of DB[7:6]. P/ S = 1 The MPU interface is parallel mode. 5-2 LCD Panel nterface Pin Name /O Description SEG0 ~ SEG127 O Segment Signals for Panel COM0 ~ COM31 O Common Signals for Panel COMS_A[1:0] COMS_B[1:0] O con Common Signals for Panel 5-.3 Clock and Power Pin Name /O Description ~ O Voltage Source of LCD Driver The relationship of the power is > VSS These pins have to add external 0.1uF~1uF capacitor to. C1P, C1M Capacitor nput These are used to connect a capacitor for internal Booster. C2P, C2M Capacitor nput These are used to connect a capacitor for internal Booster. O Booster Output VREF Reference Voltage nput This is the refeence voltage input when use an external regulator. Normally keep this pin floating, if connect this signal to FPC then have to add a 0.1uF capacitor to. CLK_SEL EXT_CLK Clock Select This pin is used to select the clock source. When CLK_SEL 1, the clock is generated by internal RC oscillator. When CLK_SEL is 0, the system clock is drive by external pin - EXT_CLK. External Clock When CLK_SEL is 0, this pin is the external clock input. When CLK_SEL is 1, this pin do not used and has to connect or. RAiO TECHNOLOGY NC. 5/6 www.raio.com.tw
P P P P Power Ground 5-4 Misc. Pin Name /O Description KST[3..0] O Key Strobe Output KN[4..0] Key Data nput Connect these pins to for unused. O[7..0] /O General Purpose /O EL_CHRG O EL Charge Signal EL_DCHG O EL Discharge Signal RST TEST[2..0] S[1:0], FG Reset This is Reset signal and active low, Test Pins These pins must contact to for normal mode. Test Pins These pins must keep NC for normal mode. RAiO TECHNOLOGY NC. 6/6 www.raio.com.tw