High Speed 10-bits LVDS Transmitter EP103 User Guide V0.6 Revised: Feb 16, 2007 Original Release Date: Oct 31, 2003, Taiwan reserves the right to make changes without further notice to any products herein to improve reliability, function or design. does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Explore Microelectronics product could create a situation where personal injury or death may occur. Should Buyer purchase or use products for any such unintended or unauthorized application, Buyer shall indemnify and hold Explore Microelectronics and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that was negligent regarding the design or manufacture of the part. 1
Revision History Version Number Revision Date Author 0.1 Oct/31/2003 -- Initial Version 0.2 Jan/09/2004 Ether Lai Fill Power Consumption 0.3 Oct/18/2004 Ether Lai Add "R_F" Pin Description 0.4 Oct/21/2004 George Lien Add LQFP64 package footprint Description of Changes 0.5 Dec/14/2004 Ether Lai Add EP LOGO to Package; Add Power Consumption (Worst Case) 0.6 Feb/16/2007 Ether Lai add the missing pin number in pin definition 2
Section 1 Introduction 1.1 Overview The EP103 LVDS transmitter supports transmission between the host and the flat panel display up to SXGA+ resolutions. The transmitter converts 32 bits (10-bits/color, 2 dummy bits) of CMOS/TTL data and 3 control bits into 5 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of 4.7Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin. 1.2 Features The EP103 includes the following distinctive features: Support 8MHz to 135MHz clock rates for NTSC to SXGA+ resolution Up to 4.7Gbps bandwidth PLL requires no external components Cycle-to-cycle jitter rejection Programmable data and control strobe select Reduced swing LVDS supported Power down mode supported Compatible with THine THC63LVD103 Single 3.3V CMOS design 64-pin LQFP (Pb Free, compliant to JEDEC/IPC J-STD-006) 3
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Section 2 Overview 2.1 Block Diagram Figure 2-1 Block Diagram of LVDS Transmitter EP103 TA0 - TA6 TB0 - TB6 TC0 - TC6 TD0 - TD6 TE0 - TE6 R_F TTL INPUT LATCH 35 DATA SERIALIZER TA+/- TB+/- TC+/- TD+/- TE+/- PWR_UP CLKIN PLL CLK+/- RS 5
2.2 Pin Diagram Figure 2-2 Pin Diagram of EP103 TB6 49 TC0 50 VDD 51 TC1 52 TC2 53 TC3 54 TC4 55 VSS 56 TC5 57 TC6 58 TD0 59 R_F 60 TD1 61 TD2 62 TD3 63 TD4 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 LVSS TA- TA+ TB- TB+ LVDD LVSS TC- TC+ TCLK- TCLK+ TD- TD+ TE- TE+ LVSS TD5 1 VSS 2 TD6 3 TE0 4 TE1 5 TE2 6 VDD 7 TE3 8 TE4 9 VSS 10 TE5 11 DCLK 12 PWR_UP 13 PVSS 14 PVDD 15 TE6 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TB5 VSS TB4 TB3 TB2 RS TB1 TB0 TA6 VSS TA5 TA4 TA3 TA2 TA1 TA0 6
2.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 2-1 Input Control/Data/CLK Pins NAME PIN # IN/OUT DESCRIPTION TA0~TA6 TB0~TB6 TC0~TC6 TD0~TD6 TE0~TE6 33~38, 40 41~42, 44~46, 48~49 50, 52~55, 57~58 59, 61~64, 1, 3 4~6, 8~9, 11, 16 IN Pixel Data Inputs DCLK 12 IN Data Clock Input. PWR_UP 13 IN Power Up. RS 43 IN LVDS Swing Mode, Input Reference Voltage R_F 60 IN Input data latching Edge. 1: DCLK Rising Edge; 0: DCLK Falling Edge. Table 2-2 LVDS Output Pins NAME PIN # IN/OUT DESCRIPTION TA- 31 OUT Negative LVDS differential data output. TA+ 30 OUT Positive LVDS differential data output. TB- 29 OUT Negative LVDS differential data output. TB+ 28 OUT Positive LVDS differential data output. TC- 25 OUT Negative LVDS differential data output. TC+ 24 OUT Positive LVDS differential data output. TCLK- 23 OUT Negative LVDS differential clock output. TCLK+ 22 OUT Positive LVDS differential clock output. TD- 21 OUT Negative LVDS differential data output. TD+ 20 OUT Positive LVDS differential data output. TE- 19 OUT Negative LVDS differential data output. TE+ 18 OUT Positive LVDS differential data output. Table 2-3 Power and Ground Pins NAME PIN # IN/OUT DESCRIPTION VDD 7, 51 PWR Digital VDD, 3.3V VSS 2, 10, 39, 47, 56 GND Digital Ground. LVDD 27 PWR Analog VDD, 3.3V LVSS 17, 26, 32 GND Analog Ground. PVDD 15 PWR PLL VDD, 3.3V PVSS 14 GND PLL Ground. 7
2.4 Electrical Characteristics Absolute Maximum Conditions Symbol Parameter Min Typ Max Units Vcc Supply Voltage -0.3 4.0 V V I Input Voltage -0.3 V cc + 0.3 V V O Output Voltage -0.3 V cc + 0.3 V V OD LVDS Driver Output Voltage -0.3 V cc + 0.3 V T J Junction Temperature -25 125 C T STG Storage Temperature -65 150 C θ JA Thermal Resistance (Junction to Ambient) 49 C/W 1. Permanent device damage may occur if absolute maximum conditions are exceeded. 2. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Normal Operating Conditions Symbol Parameter Min Typ Max Units Vcc Supply Voltage 3.0 3.3 3.6 V V CCN Supply Voltage Noise 100 mv p-p T A Ambient Temperature (with power applied) -10 25 70 C CMOS/TTL DC Specifications (under normal operating conditions unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units V IH High-level Input Voltage 2.0 Vcc V V IL Low-level Input Voltage GND 0.8 V V 1 DDQ Small Swing Voltage 1 1.8 V V REF Input Reference Voltage Small Swing (RS = V DDQ / 2) V DDQ / 2 CMOS (RS = VDD or GND) Vcc V SH 2 Small Swing High Level Input Voltage V REF = V DDQ / 2 V DDQ / 2 + 100mV V V SL 2 Small Swing Low Level Input Voltage V REF = V DDQ / 2 V DDQ / 2-100mV V 8
I INC Input Current 0 <= V IN <= Vcc +/- 10 ua NOTES: 1. V DDQ voltage defines max voltage of small swing input. It is not an actual input voltage. 2. Small swing signal is applied to Tx0 -- Tx6, where x = A, B, C, D, E LVDS Transmitter DC Specifications (under normal operating conditions unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units V OD Differential Output Voltage R L = 100 Ω, Normal Swing (RS = VCC) R L = 100 Ω, Reduced Swing (RS = GND or RS = V DDQ / 2) 200 280 360 mv 100 200 300 V OD Change in V OD between complimentary output states 35 mv V OC Common Mode Voltage R L = 100 Ω 1.125 1.25 1.375 V V OC Change in V OC between complimentary output states 35 mv I OS Output Short Circuit Current V OUT = 0V, R L = 100 Ω -7.5-15 ma I OZ Output Tri-State Current PWR_UP = 0V, V OUT = 0V or VCC +/- 1 +/- 10 ua 9
Supply Current (under normal operating conditions unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units I TCCG Transmitter Supply Current Worst Case Transmitter Supply Current Grayscale R L = 100 Ω, C L = 5 pf, Worst Case Pattern, RS = VCC R L = 100 Ω, C L = 5 pf, Grayscale Pattern, RS = VCC F = 65 MHz 50 70 ma F = 108 MHz 65 90 ma F = 135 MHz 72 100 ma F = 65 MHz 43 58 ma F = 108 MHz 52 70 ma F = 135 MHz 58 80 ma I TCCZ Transmitter Supply Current Power Down PWR_UP = 0; Input Pins = LOW 5 250 ua Figure 2-3 Worst Case Pattern DCLK Tx0,Tx2,Tx4,Tx6 x = A ~ E Tx1,Tx3,Tx5 x = A ~ E Figure 2-4 Grayscale Pattern Frequency DCLK f Tx0, x = A ~ E f/2 Tx1, x = A ~ E f/4 Tx2, x = A ~ E f/8 Tx3, x = A ~ E f/16 Tx4, x = A ~ E f/32 Tx5, x = A ~ E f/64 Tx6, x = A ~ E f/128 10
Recommended Transmitter Input Characteristics Symbol Parameter Conditions Min Typ Max Units T CIT DCLK IN Transition Time 3.0 ns T CIP DCLK IN Period 7.4 125 ns T TCH DCLK IN High Time 0.35T 0.5T 0.65T ns T TCL DCLK IN Low Time 0.35T 0.5T 0.65T ns Transmitter AC Specifications (under normal operating conditions unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units T LHT LVDS Transition Time 0.7 1.5 ns T TS TTL Data Setup to DCLK IN 3.0 ns T TH TTL Data Hold from DCLK IN 0 ns T PLLS PLL Set Time 10 ms T PDO Power Down Delay 100 ns 11
2.5 Timing Diagrams V diff = (TA+) - (TA-) Figure 2-5 LVDS Output Timing Definition 80% 80% TA+ 5pF 100Ω V diff 20% 20% TA- T LHT T LHT Figure 2-6 TTL Input Timing Definition 90% 90% 3V DCLK IN 10% 10% 0V T CIT T CIT Figure 2-7 Setup/Hold and High/Low Timing Definition (Falling Edge Strobe) T TCH T TCL DCLK IN 2.0V 2.0V 2.0V 0.8V 0.8V T CIP T TS T TH Tx0 ~Tx6, x=a~e 1.5V 1.5V Figure 2-8 Phase Lock Loop Set Time Definition PWR_UP 3.0V VCC 3.0V T PLLS DCLK IN CLK +/- TRI-STATE Vdiff = 0V 12
Figure 2-9 Power Down Delay Timing Definition User Guide EP103_UG V0.6 PWR_UP 1.5V DCLK IN T PDO Tx+, Tx- TRI_STATE 13
2.6 LVDS Outputs / TTL Data Inputs Mapping The LVDS Clock waveshape is shown in the following figure. Note that the rising edge of the LVDS clock occurs two LVDS sub symbols before the current cycle of data. The clock is composed of a 4 LVDS sub symbol HIGH time and a 3 LVDS sub symbol LOW time. The respective pin names are shown in the figure and these names are not the color mapping information but pin names only. Figure 2-10 LVDS Outputs / TTL Inputs Data Mapping CLK1 +/- Previous Cycle Current Cycle TA +/- TA1 TA0 TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB +/- TB1 TB0 TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC +/- TC1 TC0 TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD +/- TD1 TD0 TD6 TD5 TD4 TD3 TD2 TD1 TD0 TE +/- TE1 TE0 TE6 TE5 TE4 TE3 TE2 TE1 TE0 Following table shows the data mapping for the 10-bits/8-bits/6-bits input application. Table 2-4 Input Data Assignment 10-bits 8-bits 6-bits TA0 R4 R4 R4 TA1 R5 R5 R5 TA2 R6 R6 R6 TA3 R7 R7 R7 TA4 R8 R8 R8 TA5 R9 R9 R9 TA6 G4 G4 G4 TB0 G5 G5 G5 TB1 G6 G6 G6 TB2 G7 G7 G7 TB3 G8 G8 G8 TB4 G9 G9 G9 TB5 B4 B4 B4 TB6 B5 B5 B5 TC0 B6 B6 B6 TC1 B7 B7 B7 TC2 B8 B8 B8 14
Table 2-4 Input Data Assignment 10-bits 8-bits 6-bits TC3 B9 B9 B9 TC4 HSYNC HSYNC HSYNC TC5 VSYNC VSYNC VSYNC TC6 DE DE DE TD0 R2 R2 - TD1 R3 R3 - TD2 G2 G2 - TD3 G3 G3 - TD4 B2 B2 - TD5 B3 B3 - TD6 N/A N/A - TE0 R0 - - TE1 R1 - - TE2 G0 - - TE3 G1 - - TE4 B0 - - TE5 B1 - - TE6 N/A - - 15
2.7 Package 64 Pin LQFP (Pb Free, compliant to JEDEC/IPC J-STD-006) UNITS: mm EP103PB date code 10.0 TYP IDENT PIN1 12.0 TYP 64 1.4 TYP 1.6 MAX 0.5 TYP 0.22 TYP 16
User Guide End Sheet 17
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