Chapter 8 Memory Management

1 Chapter 8 Memory Management The technique we will describe are: 1. Single continuous memory management 2. Partitioned memory management 3. Relocatable partitioned memory management 4. Paged memory management 5. Demand-paged memory management 6. Segmented memory management 7. Segmented and demand-paged memory management 8. Other memory management schemes swapping overlays Single Contiguous Memory Management O.S. used by job wasted Available Hardware Support: no special hardware is required Advantage: - small O.S. - easy to understand or use such a system Disadvantage: poorly memory utilization - some memory is not being used at all (wasted area) - no multiprogramming (poor CPU utilization) - load entire program even some portions have information that is never accessed, e.g. error routine - job need memory more than available can not be run

2 Partitioned Memory Management O.S. Job1 Job2 Job 3 partition 1 partition 2 partition 3 unassigned space Hardware Support: little special hardware is needed to prevent one job from disrupting either O.S. or other jobs. Twos bound registers may be used to bracket the partition being used. If the job tried to access memory outside the partition, a protection interrupt would occur. Software Algorithm: 1. Static Partition, memory is divided into partitions prior to the processing of a jobs. Example. partition number size location status 1 8K 312K in use 2 32K 320K in use 3 32K 352K not in use 4 120K 384K not in use 5 520K 504K in use

3 0 O.S. 312K Job 1 (1K) 8K 320K Job 2 (9K) 32K 352K 32K 384K separated free area 120K 504K Job 3 (121K) 520K wasted space partition number size job size wasted space 1 8K 1K 7K 2 32K 9K 23K 3 32K - 32K 4 120K - 120K 5 520K 121K 399K 712K 131K 581K Only 131K of available 712K is actually used. Thus, over 81 percent of the available memory is wasted. 2. Dynamic Partition, partitions are created during job processing so as to match partition size to job sizes. Example. allocated partition status table partition number size location status 1 8K 312K allocated 2 32K 320K allocated 3 - - empty entry 4 120K 384K allocated 5 - - empty entry

4 unallocated area status table free area size location status 1 32K 352K available 2 520K 504K available 3 - - empty entry 4 - - empty entry Job4 0 (24K) 0 0 O.S. O.S. O.S. Job 5 312K (128K) 312K 312K Job 1 Job 1 Job 1 (8K) Job 6 (8K) (8K) 320K (256K) 320K 320K Job 2 Job 2 free (32K) (32K) (32K) 352K 352K 352K Free Job 4 (24K) Job 4 (24K) (32K) 376K free (8K) 376K 384K 384K Job 3 Job 3 free (120K) (120K) (128K) 504K 504K 504K free Job 5 Job 5 (520K) (128K) (128K) 632K 632K Job 6 Job 6 (256K) (256K) 888K 888K free free (136K) (136K) 1024K 1024K 1024K a) initial state b) jobs 4, 5, and 6 allocated c) jobs 2, and 3 terminated

5 Various algorithms are available to accomplish the allocation and deallocation functions. 1. First Fit Partition Algorithm Free table is kept sorted by location. When it is necessary to allocate a partition, we start at the free area at the lowest memory address and keep looking until finding the first free area big enough for the partition to fit. There are two major advantages: - the question Is partition adjacent to any free area? In the deallocation algorithm can usually be answered by searching only half the table. - using free areas at low memory address tends to allow a large free area to form at the high memory address. There is a good chances of finding a large enough free area. 2. Best Fit Partition Algorithm Free table is kept sorted by size (small-> large). The first free area that large enough for desired partition is the best fit. There are three major advantages: - free area can be found by searching only half the table - if there is a free area of exactly the desired size, it will be selected. This is not necessary true for first fit. - if there is no free area of exactly the desired size, the partition is carved out of the smallest possible free area and does not destroy a large free area. However, there is a major disadvantage. If the free area is usually not exactly the right size and must be split into two pieces. The free area is often quite small, almost worthless. 3. Worst Fit Partition Algorithm Free table is kept sorted by size from large to small. Allocated the largest hole first. Conclusion of Partitioned Memory Management Advantage: 1. support multiprogramming, more memory, I/O, and CPU utilization 2. requires no special costly hardware 3. simple and easy to implement Disadvantage: 1. fragmentation can be a significant problem. Fragmentation is the development of a large number of separate free areas (i.e. the total free memory is fragmented into small pieces). 2. even if memory is not fragmented, the single free area may not be large enough for a partition. 3. it does require more memory than a single contiguous memory management (as well as a more complex O.S.) in order to hold more than one job. 4. memory may contain information that is never used such as error routine. 5. a partition size is limited to the size of physical memory.

6 Relocatable Partitioned Memory Management An obvious solution to the fragmentation problem is to periodically combine all free areas into one contiguous area. This can be done by moving the contents of all allocated partitions. So that they become contiguous. This process is called compaction (or recompaction, since it is done many times). Example. Job 7 256K 0 0 0 O.S. O.S. O.S. 312K 312K 312K Job 1 (8K) Job 1 (8K) Job 1 (8K) 320K 320K 320K free (32K) Job 4 (24K) Job 4 (24K) 344K 344K 352K Job 4 (24K) Job 5 (128K) Job 5 (128K) 376K free (128K) 472K 472K 504K Job 5 (128K) Job 6 (256K) Job 6 (256K) 632K Job 6 (256K) 728K 728K 888K free (296K) Job 7 (256K) free (136K) 984K free (40K) 1024K 1024K 1024K a) initial state b) after compaction c) after allocating partition for job 7 Although it is conceptually simple, moving a job s partition doesn t guarantee that the job will still run correctly at its new location. Several hardware techniques have been developed to cope with this relocation problem. Most of them are based on the concept of a mapped memory, that is, the address space seen by a job is not necessarily the same as the physical memory address used. Hardware Support: use base-bounds relocation registers (base relocation and bound register) to do dynamic relocation (relocation at execution time)

7 Example. 352K O.S. 352K effective relocation 360800 load 1,370248 address register 360800 load 1,370248 00000 370248 3720248 015571 + 370248 015571 376K Job s 4 address space a) before relocation 376K 1024K Physical Memory 320K O.S. 352K effective relocation 328032 load 1,370248 address register 360800 load 1,370248-32768 370248 3720248 015571 + 337480 015571 376K Job s 4 address space b) after relocation 344K 1024K Physical Memory Since the starting point of a job s address space is unrelated to the physical location of the partition. It is useful to start the address space at location 0. If this convention is used. All relocation

8 registers values will be positive. Furthermore, protection is accomplished, since the hardware will detect any effective address that is negative or exceeds the value of the bounds register. Example. bound O.S. register 352K 24K 0 effective relocation 360800 load 1,9800 address register 352 load 1,9800 352K 9800 9800 015571 + 370248 015571 24K 376K address space 1024K Physical Memory Advantage: - eliminates fragmentation - increase degree of multiprogramming, increase memory and CPU utilization Disadvantage: - relocation hardware increases the cost of the computer and may slow down the speed - compaction time may be substantial - some memory will still be unused because even through it is compacted. The amount of free area may be less than the needed partition size - memory may contain information that is never used such as error routine - a job s partition size is limited to the size of physical memory Page Memory Management Another possible solution to the external fragmentation problem is to permit the logical address space of a process to be noncontiguous, thus allowing a process to be allocated physical memory wherever the latter is available. Each job s address space is divided into equal pieces, called pages, and, likewise, physical memory is divided into pieces of the same size, called blocks or frames. Then, by providing a suitable hardware mapping facility, any page can be placed into any block. The pages remain

9 logically contiguous (i.e., to the user program) but the corresponding block are not necessarily contiguous. Hardware Support: For the hardware to perform the mapping from address space to physical memory, there must be a separate register for each page; these registers are often called page maps or Page Map Table (PMTs). They may be either special hardware registers or a reserved section of memory. Every address generated by the CPU is divided into two parts: a page number (p) and a page offset (d). The page number is used as an index into a page table. The page table contains the block number which is the base address of each page in physical memory. This base address is combined with the page offset to define the physical memory address that is sent to the memory unit. Example. logical address physical address CPU p d f d p physical memory f Page Map Table The size of a page is typically a power of 2. The selection of a power of 2 as a page size makes the translation of a logical address into a page number and page offset particularly easy. If the size of logical address space is 2 m, and a page size is 2 n addressing units (bytes or words), then the highorder m n bits of a logical address designate the page number, and the n low-order bits designate the page offset. m n bits n bits page number page offset p d Example.

10 1 10 0-1 0 1023 0 1 m = 11, n = 10 0 2 n = 2 10 1022 1023 1024 1025 1 2 n = 2 10 2047 2048 Example. 0 page block 0 0 5 O.S. 1000 1000 1 6 2000 2000 Job 1 PMT 2518 load 1,2108 Job 2 page 0 3000 0 free 518 load 1,2108 0 2 4000 1000 Job 2 page 1 1 4 5000 2000 Job 1 page 0 2108 015571 2 7 6000 3000 Job 1 page 1 Job 2 PMT 7000 0 7108 015571 Job 2 page 2 0 8 8000 1000 Job 3 page 0 Job 3 PMT 9000 free 10000

11 PMT The hardware implementation of the page table can be done in a number of different ways: - as a set of dedicated registers if the page table is reasonably small (for example 256 entries) Since only one job is running at a time, only one set of hardware page mapping registers will be needed. These registers must be saved and reset whenever the processor is switched to a new job. CPU dispatcher reloads these registers just as it reloads the other registers. - kept in main memory, and use a Page Map Table Address Register (PMTAR) points to the page table. So, changing page table requires only changing this one register. Example. Job Table job number size location of PMT status 1 8K 3600 allocated 2 12K 4160 allocated 3 4K 3820 allocated 4 - - empty entry page number block number 0 5 0 2 0 8 1 6 1 4 job 3 s PMT job 1 s PMT 2 7 Memory Block Table job 2 s PMT block status 0 os 1 os 2 job 2 3 available 4 job 2 5 job 1 6 job 1 7 job2 8 job 3 9 available

12 PMTAR 0 3 4160 3600 5 job 1 s PMT length address 6 block 0 3820 8 job 3 s PMT 4K job 2 s PMT 4160 2 job 2 s PMT 4162 4 block 1 4164 7 0 518 load 1,8300 8K block 2 (job 2, page 0) 4K 8710 load 1,8300 8K 12K block 3 8300 015571 12K 16K block 4 (job 2, page 1) job 2 s address space 20K block 5 24K block 6 28K block 7 (job2, page 3) 28780 015571 32K block 8 36K block 9 40K physical memory - hybrid page map table is the standard solution. It use a special, small, fast-lookup hardware cache, called associative registers or Translation Look-aside Buffer (TLB). Each associative register consists of two parts: a key and a value. When the associative registers are presented with an item, it is compared with all keys simultaneously. If the item is found, the corresponding value field is output. The search is fast. However the

13 hardware is expensive. Typically, the number of entries in a TLB varies between 8 and 2048. The TLB contains only a few of the page-table entries. When a logical address is generated by the CPU, its page number is presented to a set of TLB that contain page numbers and their corresponding block numbers. If the page number is found in the TLB, its frame number is immediately available and used to access memory. If the page number is not in the TLB, a memory reference to the page table must be made. When the block number is obtained, we can use it to access memory. In addition, we add the page number and frame number to the TLB, so that they will be found quickly on the next reference. If the TLB is already full of entries, the operating system must select one for replacement. logical address CPU p d page # block #. TLB hit TLB f d miss p f physical memory PMT Note! Every time a new page table is selected (for instance, for each context switch), the TLB must be flushed (erased) to ensure that the next execution process doesn t use the wrong information. Advantage: - eliminates external fragmentation - increased memory and CPU utilization - compaction overhead require for the relocatable partition scheme is also eliminated Disadvantage - page address mapping hardware increase the cost of computer and slow down the processor

14 - processor overhead time must be expended to maintain and update PMT and various table - still have internal fragmentation problem - some memory will still be unused if the number of available blocks is not sufficient for the address space of the jobs to be run - memory contains information that is seldom used such as error routine - job s address space is limited to the size of physical memory Demand-Paged Memory Management In all the previous schemes a job could not be run until there was sufficient available memory to load its entire address space. These problems could be resolved by using extremely large main memories. At present this approach, althrough simple, is not usually economically feasible. Another approach is to use the operating system to produce the illusion of an extremely large memory. Since this large memory is merely an illusion, it is called virtual memory. Example. page status block 0 0 0 y 5 1000 O.S. 1000 1 y 6 2000 job 2 page 0 2000 3000 job 4 page 0 job 1 4000 job 2 page1 0 0 y 2 5000 job 1 page 0 1000 1 y 4 6000 job 1 page 1 2000 2 y 7 7000 job 2 page 2 3000 8000 job 3 page 0 job 2 9000 job 4 page 1 0 0 y 8 10000 1000 physical memory job 3 0 0 y 3 1000 1 y 9 2000 2 n - 3000 3 n - 4000 job 4 PMT

15 If the address mapping hardware encounters a page table entry with status = N, it generates a page interrupt (or page fault). The operating system must process this interrupt by loading the required page and adjusting the page table entries correspondingly. Once memory has become filled with pages it is possible to load another page only by first removing one of the pages presently in memory. This requires a technique called variously page swapping, page removal, page replacement, page turning, or page cannibalizing. The replaced page is copied back onto the secondary storage device before the new page is loaded (i.e., the two pages swap places between memory and secondary storage). Removing a page from memory and then immediately needing it again due to a page fault referencing that page would be very unfortunate. The phenomenon of excessively moving pages back and forth between memory and secondary storage has been called trashing, since it consumes a lot of the computer s energy but accomplishes very little useful results. Hardware Support: The address mapping hardware via Page Map Table, as described in Page Memory Management. Three key additions to the hardware are required: 1. A status bit in the PMT to indicate whether the page is in main memory or secondary storage. 2. Interrupt action to transfer control to the operating system if the job attempts to access a page not in main memory. 3. Record of individual page usage to assist the operating system in determining which page to remove, if necessary. Software Algorithm: Demand-Paged Memory Management must interact with information (file) management to access and store copies of the job s address space on secondary storage. The relationship of File Map Table to the Page Map Table and the Memory Block Table is illustrated below:

16 Page Map Table Memory Block Table Address Register block status 0 0 os os 1 os 4K 2 job 2, page 0 3 available 8K 4 job 2, page 1 8710 load 1,8300 (job 2, page 0) 5 job 1, page 0 12K 6 job 1, page 1 (available) 7 available 16K 8 job 3, page 0 (job 2, page 1) 9 available 20K File Map Table Page Map Table (job 1, page 0) (job 2) (job 2) 24K page file address page block I (job 1, page 1) 0 0 2 0 28K 1 1 4 0 available 2 2-1 32K (job 3, page 0) 36K 0 (available) 518 load 1,8300 page 0 40K 4K physical memory page 1 8K 8300 015571 page 2 12K secondary storage device

17 start processing instruction generate data address compute page no. advance to next instruction Hardware Is Yes fetch data that page and complete in memory the instruction No page interrupt Is No Software there a free select page to block remove Yes adjust block/page tables get page no. needed Was page changed No Yes Write page back onto disk get disk address from file map read page in adjust block and page tables restart interrupt instruction

18 Multilevel Page Map Tables The secret to the multilevel page map table method is to avoid keeping all the page tables in memory all the time. In particular, those that are not needed should not be kept around. In figure below, we see how the two-level page table works in this example. second-level page map table virtual address 0 10 10 12 frame # PMT1 PMT2 offset top-level page map table... 1023 0 PMT...... 0 1023... 1023 PMT As an example, consider the 32-bit virtual address 0x00403004. This address corresponds to PMT1 = 1, PMT2 = 3, and offset = 4. The memory map first uses PMT1 to index into the top-level page table and obtain entry 1. It then uses PMT2 to index into the second-level page table just found and extract entry 3. This entry contains the frame number Inverted Page Map Tables Traditional page map tables of the type described so far require one entry per virtual page, since they are indexed by virtual page. If the address space consists of 2 32 bytes, with 4096 bytes per page, then over 1 million page table entries are needed. As a bare minimum, the page map table will have to be at least 4 megabytes. On larger systems, this size is probably doable. However, as 64-bit computers become more common, the situation changes drastically. If the address space is now 2 64 bytes, with 4K page size, we need over 10 15 bytes for the page map table. Typing up 1 million gigabytes just for the page map table is not doable, not now and not for decades to come, if ever. One solution is the inverted page map table. In this design, there is one entry per frame in physical memory, rather than one entry per page of virtual address space. For example, with 64-bit virtual addresses, a 4K page, and 32 MB of RAM, an inverted page map table only requires 8192 entries. The entry keeps track of which (process,page) is located in which frame. However they have

19 a serious downside: memory mapping becomes much harder. When process n references page p, the hardware can no longer find frame number by using p as index into the page map table. Instead, it must search the entire inverted page map table for an entry (n,p). Furthermore, this search must be done on every memory reference, not just on page faults. The way out of this dilemma is to use the TLB. If the TLB can hold all of the heavily used pages, memory map can happen just as fast as with regular page map tables. Page-Replacement Algorithms How do we select a particular replacement algorithm? In general, we want the one with the lowest page-fault rate. Let F = failure function (number of page faults) S = success function If P is the number of page references in the page trace, then S + F = \ P. Performance: Success frequency function s = S / P Failure frequency function f = F / P Note! f = 1 - s 1. First in First Out (FIFO) Removes the page that has been in memory for the longest time. Example Page Reference 4 3 2 1 4 3 5 4 3 2 1 5 4 3 2 1 4 3 5 5 5 2 1 1 Number of blocks = 3 4 3 2 1 4 3 3 3 5 2 2 4 3 2 1 4 4 4 3 5 5 Page fault + + + + + + + + + F = 9 S = 3 f = 9/12 * 100 = 75% In practical systems with many more memory blocks and much longer page traces, f is usually below 1%. FIFO Anomaly: Under certain circumstances adding more physical memory can result in poorer performance (Belady s anomaly). Example

20 Page Reference 4 3 2 1 4 3 5 4 3 2 1 5 4 3 2 1 1 1 5 4 3 2 1 5 Number of blocks = 4 4 3 2 2 2 1 5 4 3 2 1 4 3 3 3 2 1 5 4 3 2 4 4 4 3 2 1 5 4 3 Page fault + + + + + + + + + + F = 10 S = 2 f = 10/12 * 100 = 83% 2. Optimal Algorithm Replace the page that will not be used for the longest period of time. It guarantees the lowest possible page fault rate for a fixed number of blocks. Unfortunately, the algorithm is difficult to implement, because it requires future knowledge of the reference page. As a result, it is used mainly for comparison studies. Example Page Reference 4 3 2 1 4 3 5 4 3 2 1 5 4 3 2 1 1 1 5 5 5 5 5 5 Number of blocks = 3 4 3 3 3 3 3 3 3 2 2 2 4 4 4 4 4 4 4 4 1 1 Page fault + + + + + + + F = 7 S = 5 f = 7/12 * 100 = 58.33% 3. Least Recently Used (LRU) If the optimal algorithm is not feasible, perhaps an approximation to the optimal algorithm is possible. If we use the recent past as an approximation of the near future, then we will replace the page that has not been used for the longest period of time. This approach is the least recently used algorithm. This strategy is the optimal algorithm looking backward in time, rather than forward. Example Page Reference 4 3 2 1 4 3 5 4 3 2 1 5 4 3 2 2 2 3 3 3 3 3 3 5 Number of blocks = 3 4 3 3 4 4 4 4 4 4 1 1 4 1 1 1 5 5 5 2 2 2 Page fault + + + + + + + + + + F = 10 S = 2 f = 10/12 * 100 = 83.33%

21 Neither optimal algorithm or LRU suffers from Belady s anomaly. The major problem is how to implement? Two implementation are feasible:. Counters: We associate with each page-table entry a time-of-use field, and add to the CPU a logical clock or counter. The clock is incremented for every memory reference. Whenever a reference to a page is made, the contents of the clock register are copied to the time-of-use field in the page table for that page. We replace the page with the smallest time-of-use value. Overflow of clock may be possible.. Stack: Whenever a page is referenceed, it is removed from the stack and put on the top. In this way, the top of the stack is always the most recently used page and the bottom is the LRU page. Because entries must be removed from the middle of the stack, it is best implemented by a doubly linked list, with a head and tail pointer. Note that neither implementation would be conceivable without hardware assistance. The updating of the clock fields or stack must be done for every memory reference. If we were to use an interrupt for every reference, to allow software to update such data structures, it would slow every memory reference by a factor of at least 10, hence slowing every user process by a factor of 10. Few systems could tolerate that level of overhead for memory management. 4. LRU Approximation Few computer systems provide sufficient hardware support for true LRU. Some systems provide no hardware support, and other algorithms such as FIFO must be used. Many systems provide some help, however, in the form of a reference bit. The reference bit for a page is set whenever that page is referenced. We do not know the order of use, but we know which pages were used and which were not used. This partial ordering information leads to many page-replacement algorithms that approximate LRU. We will discuss only Second-Chance Algorithm. The basic algorithm of second-chance replacement is a FIFO. When a page has been selected, however, we inspect its reference bit. If the value is 0, we proceed to replace this page. If the reference bit is 1, however we give that page a second chance and move on to select the next FIFO page. When a page gets a second chance, its reference bit is cleared. In addition, if a page is used often enough to keep its reference bit set, it will never be replaced. One way to implement the second-chance algorithm is as a circular queue. A pointer indicates which page is to be replaced next. When a block is needed, the pointer advances until it find a page with a 0 reference bit. As it advances, it clears the reference bits. Once a victim page is found, the page is replaced and the new page is inserted in the circular queue in that position. Notice that, in the worst case, when all bits are set, the pointer cycles through the whole queue, giving each page a second chance. It clears all the reference bits before selecting, the next page for replacement. Second-chance replacement degenerates to FIFO if all bits are set.

22 reference bits pages reference bits pages 0 0 1 1 0 0 0 0 0 0 The Working Set Model The set of pages that a process is currently using is called its working set. If the entire working set is in memory, the process will run without causing many faults until it moves into another execution phase (e.g., the next pass of the compiler). If the available memory is too small to hold the entire working set, the process will cause many page faults and run slowly since executing an instruction often takes a few nanoseconds and reading in a page from the disk typically takes tens of milliseconds. A program causing page faults every few instruction is said to be thrashing. Efficient operation of a virtual memory system is dependent upon the degree of locality of reference in programs. Locality can be divided into two classes: temporal locality and spatial locality. Temporal locality refers to an observed property of most programs, i.e., once a location data or instruction is referenced, it is often referenced again very soon. This behavior can be rationalized by program constructs such as loops, frequently used variables, and sunroutines. Spatial locality refers to the probability that once a location is referenced, a nearby location will be referenced soon. This behavior can be rationalized by program constructs such as sequencing, linear data structures (e.g., array), and the tendency of programmers to put commonly used variables near one another. Advantage : - large virtual memory, a job s address space is no longer constrained by the size of physical memory. - more efficient use of memory - unconstrained multiprogramming Disadvantage : - the number of tables and amount of processor overhead for handling page interrupts are greater than in the case of the simple paged management technique.

23 - due to the lack of an explicit constraint on a job s address space size or amount of multiprogramming, it is necessary to develop approaches to prevent thrashing SEGMENTED MEMORY MANAGEMENT A segment can be defined as a logical grouping of information, such as a subroutine, array, or data area. The major difference between the page and segment is that a segment is a logical unit of information visible to the user s program and is of arbitrary size. A page is a physical unit of information invisible to the user s program and is of a fixed size. Example. [MAIN] = 0 0 CALL [X] <Y> C = A(6) Operating System 160 [X] = 3 0 Segment Map Table. size access status location 3460 120 Y: 0 160 E Y 4000 [x]. 1 340 2 3580 Y: [A] = 5 3 340 E Y 3460 0 4 3800 1 5 160 R Y 3800 [A]. 6 60 RW N - 100 Access field 3900 [B] = 6 E = executable - allowed 0 R = read - allowed 4000. W = write allowed [MAIN] C: Status field 4160. Y = in memory 60 N = not in memory segmented address space physical memory

24 Segmented memory management can offer several advantages: 1. Eliminate fragmentation, by moving segments around. 2. Provide virtual memory, by keeping only the actively used segments in main memory, the job s total address space size may exceed the physical memory size. 3. Allow dynamically growing segments or automatic bounds checking. If a segment s size must be increased during execution, the out-of-range reference can be detected by the size component of each entry in the Segment Map Table. 4. Dynamic linking and loading, by deferring the linking until the segment is explicitly referenced, unnecessary linking is avoided. 5. Facilitate shared segmented (data areas and procedures). If two jobs are using a square root routine, it is wasteful to have two separate copies exist in main memory. 6. Enforced controlled access. Access to each segment should be control (see access field). Hardware Support : Have two separate address fields in each instruction, such as 64 opcode segment number byte number Register 24 24 index register for byte number This allows easy formulation of instructions, such as LOAD 1,[5] <8> where 5 is the segment number and 8 is the byte within the segment. Another approach is to generate the effective address, using linear address formation techniques, and to interpret certain bits of the resulting effective address as a segment number and the remaining bits as the byte number. For example, the IBM System/370 can interpret the 24-bite effective address as an 8-bit segment number and a 16-bit byte number as follows: 32 24 segment number byte number 0 8 16 31 The segment address mapping hardware required is similar to the page mapping hardware. However, several differences arise from the differences between segments and pages. Because

25 segments are of arbitrary size, it is necessary to check that the reference byte address is within the segment s range. Since segments may be removed from main memory and placed on secondary storage, it is necessary to indicate whether the segment is currently in memory. If it is not, an interrupt to the operating system must occur. Advantage : As mention above. Disadvantage : - Considerable compaction overhead is incurred in order to support dynamic segment growth and eliminate fragmentation - There is difficult in management variable size segments on secondary storage. - The maximum size of a segment is limited by the size of main memory. - It is necessary to develop techniques or constraints to prevent segment thrashing Segmented and Demand-Paged Memory Management One way to gain the logical benefits of segmentation and remove many of the disavtages is to combine the segmentation and paging mechanisms. For more information, see text book. Other Memory Management Schemes Swapping The early M.I.T. Compatible Time-Sharing System, CTSS, used a basic single contiguous allocation memory management scheme only one job was in memory at a time. After running for a short period, the current job s address space was swapped onto secondary storage (roll-out) to allow another job to run in main memory (rool-in). In a similar manner the partitions of a partitioned or relocatable partitioned memory management system can be swapped. Overlays A more refined form of the above swapping technique, which swaps only portions of the job s address space, is called overlay management. Overlays, normally used in conjunction with single contiguous, partitioned, or relocatable partitioned memory management, provide essentially an approximation to segmentation but without the segment address mapping hardware. Example.

26 A (20K) B (50K) C (30K) F(30K) D(20K) E (40K) total address 190 bytes 0 0 A 20K 20K C 50K B 50K 50K 70K 90K F D 90K E 100K physical memory overlay assignment