Heuristic Minimization of Boolean Relations Using Testing Techniques

Heuristic Minimization of Boolean Relations Using Testing Techniques Abhijit Ghosh Srinivas Devadas A. Richard Newton Department of Electrical Engineering and Coniputer Sciences University of California, Berkeley Abstract A Boolean relation is a one-to-many multi-output boolean mapping. Boolean relations are a generalization of incompletely specified logic functions, where for each output, a set of input values is given for which that output can be either 0 or ; a don t care. Boolean relations arise in several contexts. For instance, in a finite state machine with sets of equivalent states. Another is where one combinational logic block feeds another and the second maps two inputs J: and y into the same output pattern; thus for the first block, outputs x and yare equivalent. In general, we want to implement one of the logic functions compatible with the boolean relation, generally the one with the least cost. Minimization of boolean relations is important from the point of view of synthesis, especially in synthesis for testability. In this paper we describe a very fast heuristic procedure for finding an optimal sum-of-products representation for a boolean relation. Starting with a function compatible with the relation, a process of iterative logic improvement based on test generation techniques is used to derive a minimal function compatible with the boolean relation. INTRODUCTION Boolean relations are a generalization of incompletely specified logic functions. Typically, for such functions, a set of input values is specified for which one or more outputs can be either 0 or, i.e. a don t care. Logic minimizers like ESPRESSO [l] can utilize this information to obtain smaller sum-of-products representations of functions. However, not all aspects of incomplete specification can be captured using don t cares, especially for multi-level logic networks. Consider the example shown in Figure. In this figure, there are two PLA s, with PLAl driving PLA2. The logic function of PLAl is represented by the truth table shown in Figure 2. If fl and f2 are intermediate variables i.e. they are used only as inputs to PLA2, then it does not matter whether PLAl produces 00 instead of because PLA2 maps both 00 and to the same value 0 at its output. Similarly, PLAl could produce either 0 or 0. The output. patterns 00 and are equivalent, and so are 0 and 0. This kind of incomplete specification cannot be represented as output don t cares [3], but only as a boolean relation as shown in Figure 3. In this representation, for every minterm in the input space, there is a set of outputs and any output from the corresponding set of outputs can be chosen for that minterm to form a function compatible with the boolean relation. Note that don t cares can be easily represented using boolean relations, as illustrated with the example in Figure 4. If the function shown in Figure 2 is minimized, the minimized function is fl = ab +?is A = a However, if we choose a different function with the output 0 for the first and third input minterms and the output 00 for the second and fourth, the minimized function becomes - fi = 6 f2 = 0 and the overall behavior of the PLA network remains unchanged. As is evident from this example, significant savings in network size may be obtained by exploiting boolean relations for the minimization of PLA. Boolean relations arise in several contexts. One of them is the situation described above where one PLA drives another and the driven PLA maps two input patterns x and y to the same output, and therefore for the driver PLA, I and y are equivalent outputs. The other situation is a finite state machine with sets of equivalent states. For each present Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge m, Figure : PLA driving PLA Figure 2: Truth Table of PLAl state and input, the machine can go to any one of the states in the set of next states. This situation can be easily represented using boolean relations. Minimization of boolean relations helps in deriving smaller logic networks, and also in synthesizing circuits for testability [4]. As has been mentioned before, in a boolean relation, for each minterm in the input space, any one of the patterns from the set of output patterns for that minterm, can be chosen. For each choice of outputs, a boolean function [l] is obtained. In applications we want to implement one of the functions, generally the one with the least cost. Thus the problem of minimization is two-fold. A function with the least cost has to be identified first, and then minimized. In this paper we focus on two level sum-of-product representations of functions. In [2] an exact procedure for the minimization of boolean relations was given. The problem was formulated as a linear integer 0- program, and a branch and bound covering method was given to find the minimum cover. The problem with this approach is its exponential complexity, both in terms of CPU time and memory required to generate and store all the e-primes. Thus it can be applied only to small examples. To date, no other method for minimization of boolean relations have been developed. In the sequel, a very fast heuristic minimization algorithm is presented. This procedure makes use of test generation techniques to determine i. prim- -,,A irredundant (minimal) implementation of boolean relations. This paper is organized as follows. Definitions are presented in Section 2. In Sections 3 and 4, the minimization and network formation procedures are described. The expansion algorithm is presented in Section 5, followed by the irredundant cover algorithm in section 6. In section 7, the reduction algorithm is described. Due to space constraints, the make-sparse algorithm is not described in this paper. Initial results presented in Section 8 demonstrate the viability of this approach and its superiority over exact minimization approaches for large circuits. 2 DEFINITIONS Throughout the paper, it is assumed that the reader is familiar with the terminology of [l] and [3]. Figure 3: Boolean Relation for PLAl CH2909-0/90/0000/0277$0.OO 0 990 IEEE 2

Figure 4: Representation of Don't Cares Definition 2. A boolean relation [3] is a one-lo-many multi-output boolean mapping, R : BP - Bn, where B = {0,). Thus R(x) C B" is a set. For a boolean relation, for each input minterm (or cube) c E B', a set of primary output vectors can be asserted by that minterm (cube). The set of primary output vectors corresponding to that minterm (cube) c of the relation is called the equivalence class for the minterm (cube) and is denoted by OE(C). The cover of a boolean relation is a set of cubes and their corresponding equivalence classes (clo~(c)). Definition 2.2 A multi-output boolean function f is a mapping compatible with R if for a mintem z, f(z) E OE(Z), Vz E B'. A set of cubes (cly), where c E Br and y E OE(C), constitute the cover of a boolean function. The cover is said to be valid if the function corresponding to the cover is compatible with the relation R. Definition 2.3 Two implementations fl and f2 of a boolean relation R are equivalent if fl and f2 are mappings compatible with R. Thus for any mintem z, fi(z) and fi(z) must be elements of the set OE(Z). Definition 2.4 A cube of a function f which is compatible with a boolean relation R is said to be prime if raising any literal causes the resulting function to be non-equivalent to f. Definition 2.5 A cube of a function f which is compatible with a boolean relation R is said to be irredundant if on removal of the cube from the cover, the resulting function is not equivalent to f. Definition 2.6 A cover of a function f which is compatible with a boolean relation R is said to be prime and irredundant if every cube in the cover is prime and irredundant. 3 MINIMIZATION ALGORITHM Minimization of a boolean relation can be viewed as a two-step process. The first step is the choice of function and the second step is the minimization of the function. The objective in the first step is to choose the function which when minimized will have the optimum implementation. An optimum implementation is characterized by minimum number of product terms in the cover minimum number of literals in the cube minimum number of literals in the output part A cost function is defined in terms of the above three factors, and the minimization procedure tries to minimize the cost function. A naive approach to minimization would be to form all possible functions compatible with the boolean relation and minimize them using logic optimizers like ESPRESSO. This approach is a modified exact minimization approach, and is not suitable for real examples due to the huge number of minimizations required. The approach described in this paper starts with an initial function compatible with the boolean relation and through a series of iterations involving the procedures EXPAND, IRREDCOVER and REDUCE (like ESPRESSO) obtains a function with a smaller cost. In each of these steps, the initial function is implicitly changed to a function equivalent to it but with a smaller cost. Since the problem of minimization is NP-complete [3] the worst case complexity of this approach is exponential. However, with clever heuristics, a solution is found within reasonable amounts of CPU time in the average case. The procedures make extensive use of test pattern generation techniques. To make the use of such techniques feasible, the first step in the main minimization procedure (Figure 5) is to build a network of gates called the interconnected network. The procedure receives as its input the cover of a boolean relation and an initial function compatible with the boolean relation is chosen using Choose-Function(). Then the interconnected network is built using Buildhterconnected-Network(). Having derived the network, a gate-level automatic test pattern generator is used for the various steps in the main loop. In the EXPAND procedure, each cube in the cover is expanded to the maximum possible extent while keeping the function compatible MIXIhIIZE(RelationCover) /* The optimization loop */ /* First choose a particular function compatible with relation */ Functioncover = Choose-F'unction(ReationCover); Build-Interconnected_"twork(); while (qualit.) of solution keeps on improving){ EXPAND (Functioncover); IRREDCOVER (Functioncover); if (latest cover bet.ter than previous cover){ save latest cover; REDUCE (FunctionCover); I Functioncover = best cover; MAKESPARSE (Functioncover); ret urn (Function Cover) ; Figure 5: Main Minimization Procedure 0 Figure 6: Truth Table for PLA2 with the boolean relation. After expansion, each cube is p r i L:. ~... necessarily irredundant. IRREDCOVER identifies a set of cubes that can be removed from the cover without affecting compatibility. Thus the cardinality of the cover is reduced after this step, and all cubes in the cover are necessary. In an attempt to get out of the local minima, REDUCE reduces the size of each cube as much as possible while maintaining compatibility with the boolean relation. The reduced cubes can possibly re-expand to cover more cubes and reduce the cardinality of the cover. After reduction, the operations in the loop are repeated. Iteration continues as long as the quality of the solution keeps on improving. When the quality of the solution does not improve any more, the loop is exited and MAKESPARSE is applied to make the cover as sparse as possible. At all stages, various heuristics are used to guide the algorithm in order to obtain the best possible solution. Each of these steps except MAKESPARSE will be described in detail in the following sections. 4 NETWORK FORMATION To enable the use of a test pattern generator, it is necessary to build a network of gates from the cover of the function. Since we are interested in two level sum-of-product representations, PLA's are the obvious choice for building such a network. The cover of the initial function can be easily translated to a PLA where each product term corresponds to an AND gate with the inputs to the gate denoting the input literals for the product term. This PLA is called the driver PLA. Following that, another PLA driven by the driver PLA is constructed so that the boolean relations derived from this interconnection of PLA's (as illustrated in Section ) is the same as the original boolean relation. The second PLA is called the driven PLA. This step is performed in two different ways, depending on the initial boolean relation. Firstly, all unique equivalence classes are identified. If a particular output pattern never occurs in more than one equivalence class then the driven PLA maps only the outputs of the driver PLA in the same equivalence class to a single output. For example, for the boolean relation shown in Figure 3, the condition described above is satisfied. There are only two unique equivalence classes {Ol, 0) and (,OO). The truth table of the second PLA is shown in Figure 6, and with the initial function chosen as shown in Figure 2, the interconnected network is shown in Figure 7. If a particular output pattern occurs in more than one equivalence class, then the inputs to the driver PLA also have to be considered as inputs to the driven PLA. In this case, the driven PLA maps the outputs of the driver PLA in the same equivalence class, under the corresponding input conditions, to the same output. For the boolean relation shown in Figure 8, there are four unique equivalence classes and the pattern 0 occurs in two of them. The truth table of the second PLA and the interconnected network (with the initial function obtained 278

a b a lo Figure 7: Interconnected PLA Network Figure 0: Interconnected PLA Network Figure 6: Example Boolean Relation Figure : Function Cover after EXPAND by choosing 0 as the output for both the first and second minterm) is shown in Figure 9 and Figure 0 respectively. Note that under the input condition 00, output 00 and 0 of PLAl are mapped to the same output of PLA2. It is easy to show that the boolean relation that can be derived from the iuterconnected network is the same as the original one. 5 EXPAND In this section, the EXPAND procedure is described. This procedure has two goals. It tries to identify a function with a smaller cost and simultaneously minimizes that function. It is well known for two level AND-OR logic networks that if the function being implemented is prime and irredundant, then it is testable for all single stuck-at faults in the network. If a cube in the cover is prime, all input stuck-at- faults for the corresponding AND gate are testable. Conversely, if a cube is not prime, then for certain inputs to the corresponding AND gate, stuck-at- faults are not detectable. These inputs are therefore redundant and can be removed to make the cube prime. Given a boolean relation and an initial function compatible with the relation, a cube in that function is prime if and only if raising a literal in the input part produces a function that is not equivalent to the original function. To determine whether a cube is prime or not, it is necessary to raise all the literals in the input part of the cube, one at a time and check if the resulting function is compatible with the boolean relation. Looking at this from the point of view of test pattern generation, a literal in a cube is redundant if for all stuck-at- fault tests for the literal, the response of the fault-free network and the network with the stuck-at- fault are in the same equivalence class which is the equivalence class for the test pattern). Since the driven PCA maps patterns in the same equivalence class to a single output, this means that the effect of the fault will not be observable at the outputs of the driven PLA. This gives rise to simple criterion for determining whether a literal is redundant or not. If a stuck-at- fault for that literal in the interconnected network is undetectable, then the literal is redundant and can be removed. For AND gates fanning out to -v more than one OR gate, stuck-at-0 faults on individual fanout stems are considered, and for all undetectable faults, the corresponding fanout stem is removed. To illustrate the procedure with an example, consider the boolean relation of Figure 3. The initial function chosen is shown in Figure 2 0 0 0 0 0 0 Figure 9: Truth Table for PLAz and the resulting interconnected network is shown in Figure 7. Consider the second AND gate and the input a. The only input vector that can excite the fault is a = 0 and b =. For this vector, the response of the fault-free driver PLA is 00 and the faulty driver PLA is. The equivalence class of 0 contains both the responses. From the point of view of test pattern generation, it can be easily determined that a stuckat- fault on that input is undetectable in the interconnected network, and therefore the corresponding literal can be removed from the cube. The driver PLA now implements the function shown in Figure and this function is different from the initial function. Thus a new function with a smaller cost has been implicitly chosen. Also note that the cube after expansion is a prime of the current function, indicating that simultaneously the chosen function has been minimized. The EXPAND procedure is based on the aforementioned principles. The AND gates in the driver PLA are ordered and all literals in each gate are checked for redundancy. Also, fanout stems of AND gates fanning out to more than one output are considered. All redundant inputs and fanout stems are removed as soon as they are detected. The process continues until there are no more redundant literals or fanout stems. It can be easily shown that in the resultant circuit, all cubes are prime. For test pattern generation and efficient identification of undetectable faults, the test pattern generation algorithm PODEM [6] is used with modifications suggested in [5] and [7]. The result of EXPAND depends strongly on the order in which the cubes are expanded. Cubes are ordered in decreasing size of their equivalence class. The rationale behind this choice is that a cube with a larger equivalence class can possibly expand more and cover other cubes in the cover. The input variables in the cube are also ordered before exp- - Variables are ordered according to the number of gates they fanout to. Variables fanning out to a larger number of AND gates are considered first. This greedy strategy tries to produce PLA s with better folding characteristics and works better in the average case. 6 IRREDCOVER After expansion, each cube in the cover is prime. However there may be some cubes in the cover that are redundant, i.e. the cardinality of the cover may be decreased by deleting these cubes. Like the EXPAND procedure, the objective of this procedure is to identify a function with a lower cost and minimize that function simultaneously. The principles used are very similar to the ones used in the previous section. For a two-level AND-OR logic network, a cube is redundant if a stuck-at-0 fault at the output of the corresponding AND gate is undetectable. For a boolean relation, the condition for being redundant can be expressed in the following manner. In the interconnected network, if a stuck-at-0 fault at the output of an AND gate in the driver PLA is undetectable, then the corresponding cube is redundant and can be removed from the cover. In this procedure, the AND gates in the driver PLA are ordered and then tests are generated for output stuck-at-0 faults. As soon as a redundant cube is detected, it is removed from the cover. The procedure iterates over all cubes in the cover until no cubes are redundant. To see how the procedure implicitly changes the function chosen, consider the example used in the previous section. The cover of the function 279

a a- b ---..------ PLA PLA 2 Figure 2: Network after EXPAND b Figure 4: Network after EXPAND-IRREDCOVER Figure 3: FLinction Cover after IRREDCOVER Figure 5: PLAl after EXPAND and IRREDCOVER after expansion is shown in Figure and the corresponding network is shown in Figure 2. A stuck-at-0 fault at the output of the second AND gate is redundant, and therefore the cube can be removed from the cover. This new cover corresponds to the function shown in Figure 3 and is different from the function shown in Figure. Once again, the function is implicitly changed and the new function is minimized simultaneously. The number of cubes removed depends on the order in which they are considered. A greedy ordering strategy is employed to reduce the number of literals in the final function. Cubes that have a larger number of literals are considered before cubes with smaller number of literals. 7 REDUCE After EXPAND and IRREDCOVER, the cover is prime and irredundant. No more literals can be raised, nor can any more cubes be deleted from the cover. This is an optimal solution, but may be a poor optimal solution. To move from a local optimum to a better local optimum, it is necessary to start with a different function of (possibly) higher cost. Reduction is the operation that transforms a prime cover F into a new (in general, non-prime) cover F, by replacing each cube by a (smaller) cube contained in it. Like the two previous procedures, this operation implicitly changes the function of the driver PLA without destroying compatibility with the boolean relation. However, unlike those procedures, it increases the cost of the resulting function. The reduced function acts as a new starting point for the EXPAND and IRREDCOVER operations from where a better local optimum might be reachable. In fact, since some of the cubes of F are not prime, EXPAND can be applied to F to yield a different prime cover that may have a fewer number of cubes than F. In order to convert the cover from a prime cover to a non-prime cover, cubes in the cover have to be made non-prime. A non-prime cube has redundant literals and this suggests the use of test generation techniques for reduction. In this procedure, all inputs not connected to an AND gate under consideration are connected to it, one by one. If a stuck-at- fault on the connector is undetectable, it is retained. If not, the connector is removed. Thus literals are added to each cube, one literal at a time. Also, for each AND gate not connected to an OR gate, a connection is made and if a stuck-at-0 fault on the connector is undetectable, it is kept. The procedure continues as long as redundant literals or fanout stems can be added to the circuit. Note that an ESPRESSO-style reduce can only reduce the cubes while keeping the function of the driver PLA the same. In this procedure, each cube could be reduced further and a different function for the driver PLA may be chosen during reduction. The procedure is illustrated with the help of an example. Consider the boolean relation shown in Figure 8 and the interconnected network after expansion and irredundant cover operation shown in Figure 4. The function of the driver PLA is shown in Figure 5. If input b is connected to the second AND gate (dotted line), a stuck-at- fault on the connector is undetectable, and the connection is kept. The resultant function for the driver PLA is shown in Figure 6 and is different from the one shown in Figure 5. The choice of cubes to be reduced and the method of reduction have a crucial effect, on solution improvement. The heuristic used here is similx to the one used in ESPRESSO. Cubes in F are processed sequentially, maximally reducing each one without destroying compatibility. A crude heuristic ordering strategy is used before reducing cubes. Cubes are ordered in decreasing order of size. 8 RESULTS The algorithms described in this paper has been implemented in a system called HERB. The test generation algorithm used is a variation of the PODEM [6] test generation algorithm with modifications suggested in [7]. In this paper, we present twelve examples, some of which have been taken from [Y] and the rest from various industrial and university sources. For each example in Table, the number of inputs and the number of outputs and the final number of product terms Z P ~ I l:+n-- - in the sum-of-product representations after minimization is preszilw,. The final column indicates the total minimization time on a DECstation 300. The results were obtained using an initial implementation of the algorithms described in this paper. In Table 2, the results are compared with the results obtained from an etact minimizer for boolean relations described in 2. Though in some cases the number of literals obtained by the heuristic method is double the exact minimum, the time required for heuristic minimization is significantly smaller. In all cases, the number of product terms obtained via the heuristic approach is close to the exact minimizers results. For all the large examples, the exact minimization approach ran out of memory after running for several hours. The heuristic approach was successful in minimizing all the relations in reasonable amounts of time. The memory requirements for all examples were very small as this approach is not at all memory intensive. 9 CONCLUSIONS Minimization of boolean relations is very important from the point of view of logic synthesis and synthesis for testability. We have presented a very fast and memory efficient, heuristic test generation based algorithm for the minimization of boolean relations. This algorithm uses iterative logic improvement to derive a function of minimal cost that is compatible with the boolean relation. Experimental results indicate that the quality of results are comparable to the exact minimum, while a b n 0 0 Figure 6: PL.4 fl f2 T--r 0 0 after REDUCE 280

[5] Hideo Fujiwara and Talteshi Shimono. On the Acceleration of Test Generation Algorithms. In IEEE Transactzons on Compufers, pages 37-44. December 983. [Ci] P. Goel..4n Implicit Enumeration Algorithm to generate tests for combinational logic circuits. In IEEE Transactzons on Computers, pages 25-222, March 98. [7] Michael Schulz, Erwin Trischler, and Thomas Sarfert. SOCRATES : 4 Highly Efficient Automatic Test Pattern Generation System. In IEEE Transadtons on Conipuier-Aided Desdgn, pages 2G-37, January 988. Table : Experimental Results CKT #terms I #Iits I ' ime I #terms I #hts I 'lime Table 2: Comparison with Exact Minimization the time taken for minimization is significantly smaller. Using our approach, it is possible to minimize larger circuits than with the exact minimization approach. This approach suffers from some obvious drawbacks. Firstly, since redundant literals and cubes are removed sequentially, the ordering of the literals and cubes becomes very critical for obtaining better quality results. Also, only the removal of one literal or cube is considered at a time. Considering the removal of more than one literal or cube at a time (as in ESPRESSO) could give better results. This implies the use of multiple faults instead of single faults during the minimization process. Since the number of multiple faults is very large (exponential in the number of wires in the circuit), the time required for minimization could be very large. The entire space of functions is not explored, and thus given enough time, this approach might not be able to find the exact minimum function compatible with the boolean relation. However, results indicate that in most cases the size of the function found is comparable to the minimum in terms of the cost defined in this paper. 0 ACKNOWLEDGEMENTS The interesting discussions with Bob Brayton and Fabio Somenzi on boolean relations are acknowledged. This research was supported in part by the Defense Advanced Research Projects Agency under contracts N0004-87-K-0825 and N00039-87-C-082, Digital Equipment Corporation, AT&T Bell Laboratories and Semiconductor Research Corporation. Their support is gratefully acknowledged. References R. K. Brayton, G. D. Hachtel, Curt McMullen, and A. Sangiovanni- Vincentelli. Logic Minimization Algoethms for VLSI Synthesis. Kluwer Academic Publishers, 984. R. K. Brayton and F. Somenzi. An Exact Minimizer for Boolean Relations. In PTOC. IEEE Int. Conf. on C.4D (ICCAD), pages 36-39, 989. R. K. Brayton and Fabio Somenzi. Boolean Relations and the Incomplete Specification of Logic Networks. In Proe. VLSI-89, Munich, August 989. S. Devadas, H-K. T. Ma, A. R. Newton, and A. Sangiovanni- Vincentelli. Irredundant sequential machines via optimal logic synthesis. In IEEE TTQnSQCtiOnS on Computer Aided Design, pages 6-7, January 990. 28