1. (a) Pin configuration of 8085 X 1 X 2 CLKOUT TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SID SOD RESET IN RESET OUT T.E. Sem. V [EXTC] Microprocessors and Microcontrollers I Prelim Question Paper Solution V CC (+5 V) 8 0 8 5 V SS (GND) Description : 1. X 1, X 2 : These are crystal input lines for the internal clock generator circuit. Since internally the microprocessor requires 3 MHz clock signal and the clock generator divides the frequency by 2, the crystal oscillator connected externally should have the frequency of 6 MHz. 2. CLK OUT : (Clock out) The 3 MHz clock which is used by the microprocessor for its internal operations is available as output on this pin. It is used for synchronization between microprocessor and peripheral device. 3. AD 0 AD 7 : These are lower order multiplexed addr and data lines. These carry address during the initial part of the read/write cycle and data during the rest of the read/write cycle. These lines are demultiplexed with the external latch which will be controlled by ALE. ALE RD WR IO/ M S 1 S 0 Ready HOLD HLDA AD 0 AD 7 A 8 A 15 4. A 8 A 15 : These are higher order, non-multiplexed buffered output lines. These are unidirectional. These lines act as address lines during the entire read/write cycle. 5. ALE : (address latch enable) It is an output pin which is high when AD 0 to AD 7 carries address and low when they carry data. It is used to enable (strobe) an external latch that holds the lower order address from the 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 1
: T.E. MPMC_I multiplexed address-data bus for every read/write cycle. It is used to demultiplex the address/data bus. 1. (b) 6. RD : (read) It is an active low, control output line. It is used with IO/ M to activate the contents of memory or I/O module for read operation. 7. WR : (write) It is an active low, control output line which is used with IO/ M to activate the memory module or I/O module for write operation. Timing Diagram for Memory Write CLK ALE AD 0 AD 7 A 8 A 15 IO / M RD S 0 S 1 1 0 WR T 1 T 2 T 3 lower byte of address Higher byte of address from p to memory BYTE During T 1 p sends the address to memory. 1) ALE goes high since ADo AD7 will carry address. 2) ADo AD7 will carry lower byte of address and A 8 A 15 will carry higher byte of address from any 16 bit register pair except PC. 3) IO / M, S o, S 1 i.e., 0 1 0 to indicate memory write machine cycle. 4) RD and WR remains inactivated. During T 2 p activates the memory chip for write operation. Tristate never appears in write signals because address and data both are driven by P only. 1) ALE remains low throughout the rest of machine since ADo AD7 will carry data to be written. 2) ADo AD7 carries the byte to be written in memory. 3) A 8 A 15 continues to drive higher byte of address throughout rest of machine. 4) IO / M, S o, S 1 remains 0 1 0 throughout the cycle to indicate memory write and RD also remains inactivated. 5) WR is activated so that the memory chip starts performing the write operation. During T 3, the data sent by p is written in memory and hence p inactivates WR signal and stops driving the data byte on ADo AD7 lines and hence address data bus is tristated. 2 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution 1. (c) Modes of operation of timer: COUNTER i) MODE 0 : In this mode, only 13 bits are used for counting i.e. 8 bits in THX and 5 bits in TLX. If we load 0000H initially, then timer flag will set when 1FFF become 0000 (after 8192 pulses). Maximum delay produced in MODE 0 = 8192 12 f. ii) MODE 1: In this mode, 16 bits are used for counting. If we load 0000 initially, then timer flag will set when FFFF becomes 0000 (after 65536 pulses) Maximum delay produced in Mode 1 = 65536 12 f. iii) MODE 2: 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 3
: T.E. MPMC_I 1. (d) Setting the mode bits to (10) 2 in TMOD configures the timer to use only the TLX counter as a 8 bit counter. THX is used to hold a value from FFh to 00h. The timer flag is also set when TLX overflows. This mode exhibits an auto reload feature. TLX will count up from the number in THX, overflow and be reinitialized with contents of THX. So, main program is interrupted at regular intervals continuously. maximum delay produced in Mode 2 = 256 12 f. This mode is used to produce desired frequency by using Timer flag. iv) MODE 3: internal or external Timer 0 in MODE 3 becomes two completely separate 8 bit counters. TL0 is controlled by gate arrangement and sets Timer flag TF0 whenever it overflows from FFh to 00h. TH0 receives the timer clock under the control of TR1 only and sets the TF1 Flag when it overflows. Timer 1 may still be used in modes 0, 1, and 2 while Timer 0 is in mode 3 with one important exception that no interrupt is generated by timer 1 while timer 0 is using the TF1 overflow flag. Switching timer1 to mode 3 will stop it and hold whatever count is in timer 1. i) LHLD addr [L] [addr] [H] [addr + 1] It means to move the contents of memory location whose address is specified in the instruction into L register and the contents of next memory location into H register. e.g. LHLD 4000 H Before execution HL XX XX After execution [L] [4000 H] [H] [4001 H] 4000H 4001H 30H 10H H L 4000H 30H 10H 30H 4001H 10H Width : 3 byte Addressing : direct addressing. Flags affected : none. Machine cycle : 5 (op code fetch, operand fetch, operand fetch, memory read, memory read) T states : 16 (4 + 3 + 3 + 3 + 3) 4 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution ii) MVI M, data 8 [[HL]] data 8 It moves the data specified in the instruction into the memory location whose address is stored in HL register pair. e.g. MVI M, 60 H [[HL]] 60 H This instruction moves 60 H into memory location whose address is stored in HL register pair. Width : 2 bytes Addressing : immediate/indirect addressing. Flags affected : none. Machine cycle : 3 (op code fetch, operand fetch, memory write) T states : 10 (4 + 3 + 3) iii) STAX r p (rp HL) [ MOV M, A performs similar operation] [[r p ]] [A] It moves the contents of accumulator into the memory location whose address is stored in the specified register pair. e.g. STAX B [[BC]] [A] This instruction moves the contents of accumulator into memory location whose address is stored in BC register pair. Width : 1 byte Addressing : indirect addressing. Flags affected : none. iv) ACI 50H [A] [A] + 50H + [CF] It adds the 8 bit data specified in the instruction to accumulator along with carry flag and the result is stored in accumulator. Width : 2 byte Addressing : immediate addressing. Flags affected : all. Machine cycle : 2 (op code fetch, operand fetch) T states : 7 (4 + 3) v) DAA (Decimal Adjustment Accumulator) This instruction is used for BCD addition, after an ADD instruction (any, add operation). If both the data are valid BCD numbers, then after adding them, using any of the add instructions the answer will be in hexadecimal form, since the internal operation would be in hex (binary). If the result is an invalid BCD number, then it has to be modified so as to obtain a proper BCD result. In order to do that, the DAA instruction is to be given after the "add" instruction so as to adjust the hexadecimal answer to a BCD. To perform this operation, the DAA instruction works as follows : (i) If the lower nibble of accumulator (result) is greater than 9 or the auxiliary flag is set, then 6 is added to the lower nibble. (ii) If higher nibble or accumulator (result) is greater than 9 or the carry flag is set then add 6 to the higher nibble. e.g. 1. 03 H 2. 05 H 3. 08 H 4. 50 H + 02 H + 06 H + 09 H + 60 H 05 H 0B H 11 H B0 H +00 H + 06 H + 06 H + 60 H 05H 11H 17 H 10 H (carry = 1) 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 5
: T.E. MPMC_I 2. (a) Special Function Registers: SFR S Address range from 80 to FF H are given to special function registers. Not all of the addresses from 80 to FF H are used for SFRs, and attempting to use an address that is not defined, results in unpredictable results. Following are the SFRs with their internal RAM addresses and utility. i) A Accumulator, Address 0E0 H. ii) B Address iii) DPTR DPH DPL iv) PSW Address Arithmetic, 0F0 H External data pointer, 83 H 82 H Program status word, 0D0H v) SP Stack pointer, Address 81 H vi) SBUF Serial port data buffer, Address 99 H. Utility: It is used to hold data byte which is to be transmitted serially hold the data byte received. vii) TMOD Timer/Counter mode control, Address 89 H viii) TCON Timer/Counter control, Address 88 H ix) SCON Address Serial port control, 98 H x) IE Interrupt enable control, Address 0A8 H EA - ET2 ES ET1 EX1 ET0 EX0 EA: Enable interrupt bits. Cleared to 0 by program to disable all interrupts. Set to 1 to enable interrupts. ET2: Reserved for future use. ES: Enable serial port interrupt, 1: enable 0: disable. ETX: Enable timer X overflow interrupt, 1: enable 0: disable. 6 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution EX1/0:Enable external interrupt 1/0, 1: enable 0: disable. 2. (b) xi) IP register: ( Address 0B8 H) - - PT2 PS PT1 PX1 PT0 PX0 xii) PT2: Reserved for future use. PS: Priority of serial port interrupts. Set/ cleared by program. PTX: Priority of timer X overflow interrupts. PX1/0:Priority of external interrupts 1/0. P0 80 H PORT 0 P1 90 H PORT 1 P2 0A0 H PORT 2 P3 0B0 H PORT 3 xiii) Some of the SFRs are bit addressable also. E.g. CLR A ( byte operation) SETB 0E3 H ( bit operation) Set only bit 3 of accumulator. Other bits are not affected. i) Baud rate in the 8051 The 8051 transfers and receives data serially at many different baud rates. The baud rate in the 8051 is programmable. This is done with the help of Timer 1. Before we discuss how to do that, we will look at the relationship between the crystal frequency and the baud rate in the 8051. As discussed in previous chapters, the 8051 divides the crystal frequency by 12 to get the machine cycle frequency. In the case of XTAL = 11.0592 MHz, the machine cycle frequency is 921.6 khz (11.0592 MHz /12 = 921.6 khz). The 8051's serial communication UART circuitry divides the machine cycle frequency of 921.6 khz by 32 once more before it is used by Timer l to set the baud rate. Therefore, 921.6 khz divided by 32 gives 28,800 Hz. This is the number we will use throughout this section to find the Timer l value to set the baud rate. When Timer l is used to set the baud rate it must be programmed in mode 2, that is 8-bit, auto-reload. To get baud rates compatible with the PC, we must load TH l with the values shown in Table 2. Example 4 shows how to verify the data in Table 2. Table 2 : Timer 1 TH1 Register Values for Various Baud Rates Baud Rate TH1 (Decimal) TH1 (Hex) 9600 3 FD 4800 6 FA 2400 12 F4 1200 24 E8 Note: XTAL = 11.0592 MHz. 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 7
: T.E. MPMC_I ii) Command word register (CWR) in 8155 There are 2 formats for CWR which is descriminated by bit D 7 of CWR. (i) CWR format for BSR mode (when bit D 7 = 0). D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 X X X BSR mode 0 0 0 PC 0 0 0 1 PC 1 0 1 0 PC 2 0 1 1 PC 3 1 0 0 PC 4 1 0 1 PC 5 1 1 0 PC 6 1 1 1 PC 7 This mode is available to Port C only. Individual bits of Port C can be set on reset by writing appropriate command in CWR. D 3, D 2 and D 1 bits position of the command identifies the Port C bit which is to be affected and the D 0 bit of command specifies whether to set or reset the bit selected by D 3, D 2 & D 1. ii) CWR format for I/O mode (D 7 = 1). D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 I/O mode Not used generally set to 0 Select the Port C bit D 3 D 2 D 1 Port C bit 0 Reset 1 Set Port C lower (PC o PC 3 ) 0 output 1 input Port B (PB o PB 7 ) 0 output 1 input Mode of Port B 0 mode 0 1 mode 1 Port C upper (PC 4 PC 7 ) 0 output 1 input Port A (PA 0 PA 7 ) 0 output 1 input Mode for Port A 00 mode 0 01 mode 1 1X mode 2 8 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution 3. (a) MOV A, M Assumptions : i) Opcode of MOV A, M is XX. ii) The instruction is placed in the memory at 1250 H (PC = 1250) iii) H L contains 2500 H. (4) Memory location of 2500 H contains 39 H. (5) Accumulator contains some data say 15 H. Before execution : A H L PC 15 H 25 00 1250 1250 2500 Memory XX 39 H MOV A, M After execution : A H L PC 39 25 00 1251 CLK ALE AD 0 AD 7 A 8 A 15 IO/M S 0 S 1 RD WR PCL 50 H 12 H PCH Timing Diagram : M 1 M 2 T 1 T 2 T 3 T 4 T 1 T 2 T 3 From mem to IR OPCODE BYTE XX L 00 H H 25 H From mem. to acc. 39 H 1 PC = PC + 1 = 1251 This instruction requires 2 machine (opcode fetch + mem.read) M 1 : Opcode fetch T 1 : Load PC on address bus T 2 : Activate RD and PC = PC + 1. T 3 : Read opcode byte into IR. 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 9
: T.E. MPMC_I T 4 : Decode the opcode byte. M 2 : Memory Read T 1 : Load HL on address bus T 2 : Activate RD signal. T 3 : Read the byte from memory and load it in accumulator. 3. (b) Interrupt Structure of 8085 : Description : The interrupt enable flip-flop gets set when user given an EI instruction and gets reset by the gate G8 under following conditions : a) User gives DI instruction or b) Any interrupt gets acknowledged c) When p is reset. This flip flop when reset disables all the maskable interrupts through the 4 AND gates (G1, G2, G3 & G4) since 1 input of these gates is zero, the output remains zero. Priority Triggering Level 1 D 2 RST 7.5 Q G1 3 4 1 5 RST 7.5 internally ACK Reset7.5 (through SIM) RESET IN RESET IN RST 6.5 RST 5.5 Trap Trap ack DI Any interrupt ACK RESET IN INTR 1 D G6 G5 CLR G8 Q EI G7 S Q Interrupt Enable F/F R INTA M 7.5 M 6.5 M 5.5 Get RST Code From External Hardware 003CH (RST 7.5) 0038H (RST 7) 0034H (RST 6.5) 0030H (RST 6) 002CH (RST 5.5) 0028H (RST 5) 0024H (Trap) 0020H (RST 4) 0018H (RST 3) G4 G2 G3 0010H (RST 2) 0008H (RST 1) 0000H (RST 0) 10 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution 4. (a) Since RST 7.5 is edge triggered the interrupt is internally stored in a +ve edge triggered D type Latch. This latch gets set on rising edge of RST 7.5 which acts as clock to the latch. This latch stores the interrupt till one of the following condition occurs : (a) When RST 7.5 is internally acknowledged by p. (b) When the p is Reset. (c) When RESET RST 7.5 command through SIM instruction (i.e., with D 4 bit = 1). Any of the above conditions when appear set one of the inputs of the gate G5 which provides an output zero to clear the RST 7.5 latch. I./O Since TRAP is also edge triggered it also requires Device INTR an internal +ve edge triggered D-type Latch which gets cleared when trap is internally 8 +V acknowledged or when p is reset by gate G6. CC 0 The TRAP line is also level triggered i.e., level D 7 sensitive so as to eliminate noise. It means that D 6 8 D TRAP must maintain high level for some 5 D 4 5 duration so as to be considered. A spike is not D 3 allowed to trigger a TRAP interrupt by providing D 2 an AND gate G7 at output of the latch. D 1 D After TRAP is triggered if it remains high for 0 INTA the time delay of the flip flop only then the output of AND gate can be 1. EN Since INTR is non-vectored P in response to INTR activates INTA. This INTA signal enables an external buffer which is programmed to provide to opcode of an RST n instructions (RST 0 to RST 7). Block diagram of 8259 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 11
: T.E. MPMC_I 4. (b) It includes 8 blocks : 1) Read / write logic : when A 0 = 0 the controller is selected to write a command or read a status. The CS & A 0 determine the port address of the controller 2) Control Logic : It has two pins (INT : OutPut; INTA : Input) INT & INTA is connected to INTR & of microprocessor. 3) Interrupt Registers : IRR, ISR and IMR. a) IRR : Interrupt Request Register has 8 input lines (IR 0 IR 7 ) for interrupt corresponding to input, the respective bit is set and the request is saved in this register. b) ISR : Inservice register : it stores all the levels that are currently being serviced. c) IMR Interrupt Mask Register: It stores the masking bits of the interrupt lines to be masked. 4) Priority Resolver : This examines the IRR, ISR & IMR and determines whether INT should be sent to p. 5) CASCADE BUFFER / COMPARATOR : This block is used to expand the no. of interrupt levels by cascading two / more 8259s. Stepper motors A stepper motor is a widely used device that translates electrical pulses into mechanical movement. In applications such as disk drives, dot matrix printers, and robotics, the stepper motor is used for position control. Stepper motors commonly have a permanent magnet rotor (also called the shaft) surrounded by a stator (see Figure 1). There are also steppers called variable reluctance stepper motors that do not have a PM rotor. The most common stepper motors have four stator windings that are paired with a center-tapped common as shown in figure 2. The stepper motor discussed here has a total of 6 leads: 4 leads representing the four stator windings and 2 commons for the center-tapped leads. As the sequence of power is applied to each stator winding, the rotor will rotate. There are several widely used sequences where each has a different degree of precision. Table (i) shows a 2- phase, 4-step stepping sequence. It must be noted that although we can start with any of the sequences in Table, once we start we must continue in the proper order. For example, if we start with step 3 (0110), we must continue in the sequence of steps 4, 1, 2, etc. Fig. 2: Stator Windings Configuration Fig. 1 : Rotor Alignment 12 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
5. (a) Clockwise Step # Winding A Winding B Winding C Winding D 1 1 0 0 1 2 1 1 0 0 3 0 1 1 0 4 0 0 1 1 Prelim Question Paper Solution Step angle How much movement is associated with a single step? This depends on the internal construction of the motor, in particular the number of teeth on the-stator and the rotor. The step angle is the minimum degree of rotation associated with a single step. Various motors have different step angles. Table (j) shows some step angles for various motors. In Table (j), notice the term steps per revolution. This is the total number of steps needed to rotate one complete rotation or 360 degrees (e.g., 180 steps x 2 degrees = 360). Table (j) : Stepper Motor Step Angle Step Angle Step per Revolution 0.72 500 1.8 200 2.0 180 2.5 144 5.0 72 7.5 48 15 24 It must be noted that perhaps contrary to one's initial impression, a stepper motor does not need more terminal leads for the stator to achieve smaller steps. All the stepper motors discussed in this section have 4 leads for the stator winding and 2 COM wires for the center tap. Although some manufacturers set aside only one lead for the common signal instead of two, they always have 4 leads for the stators. Next we discuss some associated terminology in order to understand the stepper motor further. Step I : Total EPROM required = 8 KB Chip size available = 2 KB No. of chips required = 4 Chip 1 : Starting address = 0000 H Chip size = 2 kb = 07 FF H Endign address = 07FF H Chip 2 : Starting address = 0800 H Chip size = 2 kb = 07FFH Ending address = 0 F F F H Chip 3 : Starting address = 1000 H Chip size = 2 kb = 07FF H Ending address = 17FF H Chip 4 : Starting address = 1800 H Chip size = 07FF H Ending address = 1FFF H Table (i) : Normal 4-Step Sequence Step II : Total RAM required = 16 kb Chip size = 2 kb No. of chips requied = 8 Counterclockwise 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 13
: T.E. MPMC_I Chip 1 : Starting address = 2000 H Chip size = 07FF H Ending address = 27FF H Chip 2 : Starting address = 2800 H Chip size = 07FF H Ending address = 2FFF H Chip 3 : Starting address = 3000 H Chip size = 07FF H Ending address = 37FF H Chip 4 : Starting address = 3800 H Chip size = 07FF H Ending address = 3FFF H Chip 5 : Starting address = 4000 H Chip size = 07FF H Ending address = 47FF H Chip 6 : Starting address = 4800 H Chip size = 07FF H Ending address = 4FFF H Chip 7 : Starting address = 5000 H Chip size = 07FF H Ending address = 57FF H Chip 8 : Starting address = 5800 H Chip size = 07FF H Ending address = 5FFF H 14 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution Step III : Memory MAP A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 EPROM y 0 SA = 0000 H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chip 1 EA = 07FF H 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 EPROM y 1 SA = 0800 H 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Chip 2 EA = 0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 EPROM y 2 SA = 1000 H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Chip 3 EA = 17FF H 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 EPROM y 3 SA = 1800 H 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Chip 4 EA = 1FFF H 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 RAM y 4 SA = 2080 H 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Chip 1 EA = 27FF H 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 RAM y 5 SA = 2800 H 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Chip 2 EA = 2FFF H 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 RAM y 6 SA = 3000 H 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Chip 3 EA = 37FF H 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 RAM y 7 SA = 3800 H 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Chip 4 EA = 3FFF H 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RAM y 8 SA = 4000 H 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chip 5 EA = 47FF H 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RAM y 9 SA = 4800 H 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Chip 6 EA = 4FFF H 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 RAM y 10 SA = 5000 H 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Chip 7 EA = 57FF H 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 RAM y 11 SA = 5800 H 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Chip 8 EA = 5FFF H 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 15
: T.E. MPMC_I 5. (b) Fig. 1 Step I : Total RAM required (data) = 16 kb Chip size available = 16 kb (assume) No. of chips required = 1 Chip 1 : Starting address = 0000 H Chip size = 16 kb 3FFF H Ending address = 3FFF H Step II : Total RAM required (program) = 16 kb Chip size available = 16 kb (assume) No. of chips requierd = 1 Chip 1 : Starting address = 0000 H 16 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Step III : Step IV : Chip size = 16 kb 3FFF H Ending address = 3FFF H Prelim Question Paper Solution Memory Map a) Data Memory A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IM SA = 0000 H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ip EA = 3FFF H 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b) Program Memory A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IM SA = 0000 H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ip EA = 3FFF H 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Final Implementation + 5 V CC V CC X 1 X 2 RESET EA GND P 2 A 18 A 15 AD 0 AD 7 8051 PSEN (P 3 7 ) RD (P 3 6 ) WR P 0 74373 OE WE A 0 A 7 OE A 0 A 13 D 0 D 7 27128 CS A 0 A 13 D 0 D 7 62128 CS A 0 A 15 D 0 D 7 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 17
: T.E. MPMC_I a) Interfacing ADC 0804 to MCS - 51 family. 6. (b) 8051 6. (a) LXI SP, XXXX H LXI H, 4000 H MVI C, 00H (counter for zero) MOV D, C (counter for +ve) MOV E, C (counter for ve) MOV B, M UP INX H MOV A, M ANA A JNZ DN 1 INR C JMP DN DN 1 JP DN 2 INR E JMP DN DN 2 INR D DN DCR B JNZ UP LXI H 5000 H MOV M, C INX H MOV M, D INX H MOV M, E HLT Rotate Instructions 1. RAL (Rotate Accumulator Left with carry) D P2.5 P2.6 P 1.0 P 1.7 P2.7 CF RD WR D 0 D 7 INTR 7 D6 D5 D4 D3 D2 D1 D0 V CC A D C 0 8 0 4 CLK R CLK IN V ref 2 V in (+) V in ( ) GND CS AGND 18 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution This instruction rotates the contents of accumulator left by one bit position including carry. The D 0 th bit enters into D 1 th bit position, D 1 into D 2, D 2 into D 3 and so on D 6 into D 7, the D 7 th bit enters into carry flag and the carry flag enters into D 0 th bit. Width : 1 byte Addressing : implied addressing. Flags affected : only carry Machine cycle : 1 (op code fetch) T states : 4 2. RLC (rotate accumulator left without carry) CF D 7 D6 D5 D4 D3 D2 D1 D0 This instruction rotates the contents of accumulator left by one bit position without including carry. The D 0 th bit enters into D 1 th bit position, D 1 into D 2, D 2 into D 3 and so on D 6 into D 7, the D 7 th bit enters into D 0 th bit and also in carry flag. Width : 1 byte Addressing : implied addressing. Flags affected : only carry. Machine cycle : 1 (op code fetch) T states : 4 3. RAR (Rotate accumulator right with carry) CF D 7 D6 D5 D4 D3 D2 D1 D0 This instruction rotates the contents of accumulator right by one bit position including carry. The D 7 th bit enters into D 6 th bit position, D 6 into D 5, D 5 into D 4 and so on D 1 into D 0, the D 0 th bit enters into carry flag and the carry flag enters into D 7 th bit. Width : 1 byte Addressing : implied addressing. Flags affected : only carry. Machine cycle : 1 (op code fetch) T states : 4 4. RRC. (Rotate accumulator right without carry) D 7 D6 D5 D4 D3 D2 D1 D0 CF This instruction rotates the contents of accumulator right by one bit position without including carry. The D 7 th bit enters into D 6 th bit position, D 6 into D 5, D 5 into D 4 and so on D 1 into D 0, the D 0 th bit enters into D 7 th bit and also into carry flag. 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 19
: T.E. MPMC_I Width : 1 byte Addressing : implied addressing. Flags affected : only carry. Machine cycle : 1 (op code fetch) T states : 4 7. (a) 7. (a) i) 1 machine cycle 6 states = 12 clk pulses. For 4 machine cycles, we need to count 12 4 = 48 clock pulses. Count in HEX is 30H Count to be loaded in Timer is 2 s compliment of 30H i.e. CFH + 01H = D0H i.e. FFD0H 16 bits : ii) Memory Mapped I/O 1) Instead of memory, I/O device is connected in the memory map. 2) All 20 address lines of 8086 are used in this technique. Hence upto 2 20 = 1 MB devices can be connected. 3) Memory related control signals like memory read, memory write are used for interacting with I/O devices. 4) All instructions related to memory access are used for accessing data from I/O device. 5) All memory related addressing modes can be used 6) Some memory space is used for connecting I/O devices. Hence effective memory capacity is less than 1 MB. 7) Efficiency of I/O access is less as memory related instructions are used for accessing I/O devices. I/O mapped I/O (Isolated I/O) 1) Separate I/O space is utilised in this technique. 2) Only 16 address lines are active in I/O mapped I/O. Hence upto 2 16 = 64K devices can be connected. 3) I/O related control signals like I/O read and I/O write are used for interacting with I/O devices. 4) Dedicated instructions, IN and OUT are used for accessing data from I/O devices. 5) Only I/O related addressing modes are available (direct I/O, Indirect I/O) 6) Separate address space is used for connecting I/O devices. Hence effective memory capacity is 1 MB. 7) IN and OUT instructions are designed for high throughput. Hence accessing I/O is efficient. 20 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I
Prelim Question Paper Solution 7. (b) 8051 has four I/O ports: port 0, port 1, port2, port 3. Latch is used to control each port. Different opcode is used to access latch and port. The contents of latch is different from content of port. PORT 0: It can function as input or output port for data. To use Port 0 as input port, then logic 1 is written in every latch. Now, upper buffer is disabled, lower buffer enabled. Due to control logic both FETs are off and so pin is connected to internal bus through lower buffer i.e. 8051 reads data. To use Port 0 as output port, data is written into the latches. In this case, both buffers are disabled. The latch which was written 0 will make lower FET on so that pin is grounded.the latch which has written 1 will make both FET off and so that pin will be floating i.e. logic 1. Port 0 is also used during memory expansion. Initially it transfer lower byte address then it is used to transfer data. PORT 1: It can function as input or output port for data. To use Port 1 as input port, then logic 1 is written in every latch due to this FET is off. Now, upper buffer is disabled, lower buffer enabled. So pin is connected to internal bus through lower buffer i.e. 8051 reads data. If we want Port 1 as output port, data is written into the latches. In this case, both buffers are disabled. The latch which was written 0 makes FET on so that pin is grounded i.e 0 is available at pin. The latch which has written 1 will make FET off and so that pin will be floating i.e. logic 1. The upper buffer is enabled to read contents of latch. Fig B Fig A 1113/Engg/TE/Pre Pap/2013/EXTC/Soln/MPMC_I 21