Multi-Site Parallel Testing with the S535 Wafer Acceptance Test System
In semiconductor wafer production, minimizing the cost of test has been identified as the number one challenge. The biggest factor in the cost of test, as well as in the cost of test system ownership, is throughput of the tester/prober combination. Multi-site parallel testing, regardless of the specific application, offers the greatest improvement to throughput for on-wafer test. This is because the majority of the overhead costs relate to the combination of test time plus moving the probe pins to the next test site. Increasing the throughput of this tester/prober combination can result in a significantly reduced cost of test and faster production ramp-up. Fig 1. The S535 system (show to the right) is configured for multi-site parallel testing, which is ideal for applications such as: Multi-site, small-scale analog/mixed signal functional testing Multi-site parametric die sort Multi-site wafer level reliability (WLR) testing The Multi-site Parallel Test Concept The device under test (DUT) or test element group (TEG) on the wafer includes a number of elements that require testing. In a sequential test regime (Figure 2), the testing of each element, no matter how simple, adds to the overall test time. If two identical elements on different sites can be tested in parallel (Figure 3), the total test throughput can be doubled. In addition, the number of prober moves is cut in half, resulting in a significant improvement in test system throughput improvement. Figure 1. S535 Multi-Site Test System. PROBER MOVEMENT PARALLEL TEST PROBER MOVEMENT Figure 2. Traditional Single-Site prober movement and test sequence. Figure 3. Multi-Site prober movement and test sequence. 2 WWW.TEK.COM/KEITHLEY
The multi-site parallel test concept has throughput advantages over traditional parallel test methods. Traditional parallel testing is performed on multiple devices on the same site. Once all testing on one site is completed, the prober indexes to the next site. By contrast, the multi-site parallel testing method is performed on multiple devices on different (multiple) sites at the same time. This eliminates all dead time between tests, and means there is no waiting for any one test to complete before the prober indexes to the next site. The test program is written so that similar devices are tested at the same time. Considerations It is important to take possible parasitic interactions between devices into consideration. The coupling through the wafer substrate or the common terminal on vertical devices may require executing certain low current tests sequentially. For example, when measuring device leakage levels of a few pico-amps, there can be interaction between devices. In such cases, the test plan would consist of a combination of singlesite sequential tests and multi-site parallel tests. Fortunately, most testing of small-scale analog/mixed signal devices does not require measuring leakage currents this low. Another key is managing the limitations of the probing technology. If the distances between sites that are to be probed simultaneously are too far away, the probe station can suffer from alignment errors, which can result in inconsistent test results and poor yields. Be sure to check with the prober vendor to determine the maximum distance between test sites. System Architecture A multi-site tester can be thought of as a system of multi-group testers. Each group consists of all the resources needed to execute a suite of tests on a single site. Figures 5 and 6 illustrate two types of multi-group testers. Each group has several source-measure units (SMUs) for DC testing. The TSP (Test Script Processor) master unit is unique Keithley technology that enables each group to operate autonomously, independent from the other group. Tektronix/Keithley has two types of multisite system solutions, which are defined by software. The first solution is based on Keithley Test Environment (KTE) software, which runs on a Linux controller (Figure 5). The second solution is based on Automated Characterization Suite (ACS) software, which runs on a Windows controller (Figure 6). Linux Controller TSP Master GROUP 1 GROUP 2 Matrix Probe Card SITE 2 SITE 1 Figure 5. S535 KTE multi-site system architecture. GROUP 1 SITE 1 Windows Controller GROUP 2 Matrix Probe Card SITE 1 SITE 2 SITE 2 Figure 6. S500 ACS multi-site system architecture. Figure 4. Multi-site probing example with acceptable distance between test sites. WWW.TEK.COM/KEITHLEY 3
S535 KTE Multi-Site System Features The Linux-based S535 KTE system architecture is illustrated in Figure 5. Note the TSP master unit on the left-hand side, which handles all communications traffic and enhances throughput. This single master unit concept ensures accurate time synchronization for all the instruments under its control All LAN communications and the new TSP Master feature enhance overall speed improvement 2636B, 2461 SMU, and 7510 DMM available Max 200V @ 100mA (with the Model 2636B SMU) Max 100V @ 1A (with the Model 2461 SMU) Max dual 32 output pins with three SMUs and GND unit per site, or quad 16 output pins with one SMU and GND unit per site Linux-operated workstation S500 ACS Multi-Site System Features The Windows-based S500 ACS system architecture is illustrated in Figure 6. Each group has its own TSP master unit, which supports independent operation of the group. Also, ACS allows for creating a flexible configuration: Supports most instruments as options, including C-V meter, DMM, etc. Customized hardware configuration available No limit on the number of output pins High throughput performance Customized test module available Windows-operated workstation Benchmark Examples Wafer Acceptance Test (WAT) of an RF Amplifier 1. DC functional testing is performed directly on the device. A total of 2,000 devices (sites) are tested on each wafer. 2. A typical single-site, sequential tester requires 4 seconds per site for all measurements, and 0.2 seconds for each prober movement between sites. The total wafer test time is 8,400 seconds or 2.34 hours. 3. The S535 Multi-Site Parallel Tester also takes 4 seconds to perform all measurements, however it tests 2 sites at the same time, therefore taking an equivalent time of 2 seconds per site. movement time remains 0.2 seconds, however since the devices are tested in parallel, there are half as many moves to make to cover the entire wafer. Total wafer test time is 4200 seconds or 1.17 hours. SINGLE-SITE OPERATION Site01: Site02: 4 sec. 0.2 sec. 4 sec. 0.2 sec. X 2000 sites = 8400 sec./wafer = 2.34 hrs./wafer MULTI-SITE OPERATION Site01: Site02: 0.2 sec. 0.2 sec. Site101: Site102: 4 sec./2 = 2 equivalent seconds 4 sec./2 = 2 equivalent seconds X 2000 sites = 4200 sec./wafer = 1.17 hrs./wafer Conclusion: By reducing WAT time from 2.34 hrs/wafer to 1.17 hrs/wafer, an additional 3.4 wafers are able to be processed per 8 hour shift. Projecting this to 24/7/365 operation, the use of multi-site parallel test enables an additional 3700 wafers to be processed per year, which is an incremental output of 7.4 million devices. 4 WWW.TEK.COM/KEITHLEY
TEG Testing of an Image Sensor 1. DC parametric testing is performed on two TEGs per test site. A total of 50 sites are tested on each wafer. 2. A typical single-site, sequential tester requires 2.8 seconds per site for all measurements, and two 0.2 second prober movements per site. The total wafer test time is 160 seconds or 2.67 minutes. 3. The S535 Multi-Site Parallel Tester also takes 2.8 seconds to perform all measurements, however it tests 2 sites at the same time, therefore taking an equivalent time of 1.4 seconds per site. movement time remains 0.2 seconds, however since the TEGs are tested in parallel, there are half as many moves to make to cover the entire wafer. Total wafer test time is 80 seconds or 1.34 minutes. SINGLE-SITE OPERATION TEST SITE #1 Site01: TEG01 Site01: TEG02 2.8 sec. 0.2 sec. 2.8 sec. 0.2 sec. X 50 sites = 160 sec./wafer = 2.67 min./wafer MULTI-SITE OPERATION TEST SITE #1 and #11 Site01: TEG01 Site11: TEG02 Site11: TEG01 Site01: TEG02 2.8 sec./2 = 1.4 equivalent seconds 2.8 sec./2 = 1.4 equivalent seconds 0.2 sec. 0.2 sec. X 25 sites = 80 sec./wafer = 1.34 min./wafer Conclusion: By testing two TEGs in parallel, the S535 Multi-Site Parallel Tester doubles the throughput of the tester/prober combination compared to the single-site, sequential tester. By comparison, increasing the measurement speed of the single-site sequential tester by 30% results in a total wafer test time of 118 seconds or 1.97 minutes. In this case, the multi-site parallel tester is 32% faster due to the impact of reduced prober index time. Conclusion Reducing the cost of test and the cost of ownership are significant challenges in the semiconductor production market. Throughput of the tester/prober combination is the largest factor in both cases. Single-site, sequential test stations. Multi-site, parallel test station. Figure 7. Using a multi-site parallel test system can cut the total cost of ownership in half by doubling production throughput while reducing the number of probers, freeing up fab floor space, and reducing maintenance requirements. WWW.TEK.COM/KEITHLEY 5
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