Design Architecture Implementation Realization Architecture defines the functional appearance of a system to its user (what?) Implementation provides the logic structure and practical means for accomplishing something (how?) Realization is a concrete version of an implementation; components, their interconnections, positions, shielding, packaging, components reliability, etc. Compare (a) a sand hour glass, (b) a pocket mechanical watch (c) a wrist quartz watch and (d) the Big Ben from the architecture, implementation and realization points of views. CHALMERS Lindholmen 1
Simplified Block Diagram of a MC68HC11D0 ROM RAM EEPROM Timer& Counter system CPU core Serial I/O Handshake I/O Port A Port B Port C Port D Address/Data bus CHALMERS Lindholmen 2
Development tools Evaluation boards are simple systems build upon the same microprocessor/microcontroller as the target system used to evaluate the performance of specific processors and provide external RAM, ROM or PROM input and output ports and serial communication interface monitor programs ( a simple operating environment/system. tools for program debugging (tracing, breakpoints settings, modification of register content, reading/modifying memory content, etc. CHALMERS Lindholmen 3
Implementation of a complete single-chip system Figure 1: Pin assignment of MC68HC11D3Pin CHALMERS Lindholmen 4
Features The MC68HC711D0 has 4kB ROM, often containing a monitor program. In single chip mode, RESET signal forces the MC to execute the monitor program. SCI can practically use any terminal program available. Information to be sent to the processor should be commands that the monitor understands and data it needs. To sent program code to the monitor, the program source file should be assembled or compiled (by other programs such as assemblers or compilers ) to program code (hex code) the processor understand. A EVB could integrate the above jobs in a single user-friendly environment CHALMERS Lindholmen 5
Interfacing SCI with a terminal MC68HC11 TxD 16 15 12 MAX232 11 T1IN T1OUT 14 13 DB9F connector 5 3 Sg Tx R1OUT RxD R1IN 2 Rx GND CHALMERS Lindholmen 6
MCS in expanded mode Address bus (A15--A0) MCU Data bus (D7--D0) Control bus (AS,R/W) RAM PROM I/O PORT Figure 2: Generic bus system and its interface with various devices CHALMERS Lindholmen 7
CHALMERS Lindholmen 8 Many of the members of the MC68HC11 family have multiplexed address/data bus The control bus is unidirectional, with output signals R/W, AS, and E. (AS,R/W,E) A15 A8 AS (A7-A0) (A15-A8) MCU AD7 AD0 Latch (D7-D0) Bus Demultiplexing
Timing diagrams E Clock R/W A7-A0 write(w)/ read(r) cycles w r Address available Data available A15-A8 AS Figure 3: Time diagram of read/write cycles (expanded mode) CHALMERS Lindholmen 9
Decoding of E and RW signals for Memory Interface R/W OE E WE Figure 4: WE and OE (or RD) signals used to interface with some typical memories When the E signal is low both WE and OE signals become high, independently of the input R/W signal. When the E signal is high then OE = R/W = R/W and WE = R/W (R OE and W WE). CHALMERS Lindholmen 10
Tristate bus I0 O0 devices Two devices should not be allowed to simultaneously sent signals on the same data line. A bus conflict or bus contention happens when two signals are propagated concurrently on the same line. The devices connected to the bus should be able to permit or prohibit issuing signals on the bus. Tristate technology provides support for avoiding bus conflicts. of communication of the MCU with other The processor bus provides the highway R Tristate line Tristate output I1 I2 I3 I4 I5 I6 I7 OE Bus line V DD TTL input Enable (a) 5V (b) (c) O1 O2 O3 O4 O5 O6 O7 GND GND CHALMERS Lindholmen 11
Address Decoding/Definitions 0000 2000 1FFF To individually address various devices we give them specific addresses. The available address space size S is dictated by bus width M, namely S = 2 M. In case of 16 bits bus S = 2 16 = 65535 (64K). The address space spans the region $0000 $FFFF or 0 65535. Each device is allocated (maps to) a specific region on the address space. Memory map diagram displays allocated regions on the address space 4000 6000 8000 A000 C000 E000 3FFF 5FFF 7FFF 9FFF BFFF DFFF FFFF CHALMERS Lindholmen 12
MC68HCA1/A8 Memory Map $0000 $00FF $1000 $103F N/A N/A External External 256-Byte RAM 64-Byte Register Block $B600 $B7FF 512-Byte EEPROM $E000 $FFFF N/A External Single Chip Expanded Multiplexed 8-KB ROM Shaded surfaces are memory regions occupied by on-chip memories. In expanded mode, external memories can be mapped onto remaining address space (unshaded surfaces). In single-chip mode these regions are not available. CHALMERS Lindholmen 13
Mapping devices onto memory map Assume that a MC system has two memory ICs of 32KB each. Memory chips of these size have 15 address pins (2 15 = 32K) A14 A0, eight data pins D7 D0, and few control pins, such as OE, WE,and CS 1. Bus address lines A14 A0 should be connected to the pins A14 A0 of the memory ICs. The address line A15 could then be used to generate chip select (CS) signals for the two memories CS1 =A15 and CS2 =A15. When a CS is low memory s data pins connects to the data bus, otherwise they are disconnected. 1 PROMs might have additional control pins for programming CHALMERS Lindholmen 14
A14--A0 RAM 32K EEPROM 32K CS CS A15 A15 (CS_1) (CS_2) In general we need to construct a digital circuit (decoder) that monitors the address bus and generates chip select signals to memory chips according to memory map. The process is called address decoding. The same decoding scheme could be applied to two smaller sizes memories; The later case is referred to as partial decoding, does not use the whole available address space. Some of upper addresses lines would be left unconnected. CHALMERS Lindholmen 15
Binary Address Mapping: Examples Address bus lines N = 16. Address space 2 N = 64 kb i Address lines on memory chip M = 10 ii Size of memory partitions 2 M = 2 10 = 1 kb iii Number of partitions 2 N /2 M = 2 N M = 2 6 = 64 i Address lines on memory chip M = 8 ii Size of memory partitions M = 256B = 1 4 kb iii Number of partitions 64/ 1 4 = 256 i Size of memory partitions M = 16KB ii Number of partitions 4 iii Lines for CS select signal 2 iv Address lines on memory chips M = 14 CHALMERS Lindholmen 16
Partial decoding Assume that an MCS needs 4KB RAM, 16KB EEPROM and two I/O ports respectively with three and eight registers. We could make a binary partition as in Section of the address space to 2, 4, 8, and or more regions. Let us locate the RAM on the memory map at addresses $8000 $8FFF. Note that $8000 + $1000 -$0001 =$8FFF, where $1000 = 4096. Only in this this address interval we should enable the external RAM chip. Let s display the address range in the binary format as shown in the following table. symbol x denotes an address line which can be either 0 or 1. Address A15 A14 A13 A12 A11 A10... A0 $8000 1 0 0 0 0 0... 0 $8001 1 0 0 0 0 0... 1 $8xxx 1 0 0 0 x x... x.... $8FFE 1 0 0 0 1 1... 0 $8FFF 1 0 0 0 1 1... 1..... CHALMERS Lindholmen 17
From this table (consider particularly the third row), we can generate the chip enable signal(cs) by the Boolean expression: CS = A15 A14 A13 A12 Two more examples. EXAMPLE 1 Map an I/O port with three registers from address $4000. Design the address decoding circuit. The address range is $4000 $4002 is defined by address range 01000000000000xx where xx can takes values 00,01,10,11. To generate a CS signal for (only) the above locations would required to decode 14 address lines, from A15 to A2. CS =A15 A14 A13 A12 A11... A2 Note that the scheme includes also the address $4003 although no register is located there. As expected, the decoding circuit gets quite large. As mentioned earlier, when we need not consume all the available address space we can make a partial decoding, i.e. allocate a larger address range to the I/O port, or other devices, although they do not need or use it. The address decoding circuit simplifies considerably. CHALMERS Lindholmen 18
EXAMPLE 2 Assigning the range $4000 $43FF to the I/O port above we can generate CS signals by Boolean expression CS = A15 A14 A13 A12 A11 A10 Note that all addresses with binary patterns 010000xx... x, as tabulated below, will generate a single CS signal, i.e select the same I/O port. The lower two bits of address bus determine which registers to be accessed. $4000 $4003, $4004 $4007, $4008 $400B, $400C $400F, $4010 $4013, $4014 $4017, $4018 $401B, $401C $401F, $4020 $4023, $4024 $4027, $4028 $402B, $402C $402F,... $4100 $4103, $4104 $4107, $4108 $410B, $410C $410F, $4110 $4113, $4114 $4117, $4118 $411B, $411C $411F,... $4200 $4104, $4104 $4107, $4108 $410B, $410C $410F,... $42F0 $42F3, $42F4 $42F7, $42F8 $42FB, $42FC $42FF,... CHALMERS Lindholmen 19
$43F0 $43F3, $43F4 $43F7, $43F8 $43FB, $43FC $43FF The addresses $4000, $4001 $4002 (and $4003) can be used to assess registers. The remaining I/O space contains replica of these registers and can not be used by other devices. The following VHDL could be used to program a PLD (programmable logic device). e.g. a PAL device (programmable array logic) for address decoding. library ieee; use ieee.std_logic_1164.all; entity address_decoder is port( A15,A14,A13,A12,A11,A10 :in std_logic; CS_L: out std_logic); end address_decoder architecture decoder_arch of address_decoder is begin CS_L <= A15 and not(a14) and A13 and A12 and A11 and A11; end decoder_arch; CHALMERS Lindholmen 20
Memory map of MC68HC11D0 $0000 $003F $0040 $00FF $7000 $7FFF $BF00 $BFFF $BFC0 $BFFF $F000 $FFFF $FFC0 $FFFF Static RAM 192 bytes Internal register and I/O ROM (PROM) 4 KB ROM (PROM) 4 KB BOOT ROM 256 bytes Single Chip Expanded Multiplexed Special Bootstrap Special Test Special modes Interrupt Vectors Normal modes Interrupt Vectors Can be disabled by EPON bit (CONFIG Reg) CHALMERS Lindholmen 21
Memory allocation 0000 00FF 2000 4000 Partition of address space in four 16kB regions. Three 16kB memories can be accommodated at addresses $4000, $8000, and $C000. Two address lines decode CS signals: CS2, CS3, CS4. The region $2000-$3FFF could be saved for future system development. Internal registers on the top of MM 6000 8000 A000 C000 E000 CHALMERS Lindholmen 22
Debugging tools: Oscilloscope test loops. Problem: We can not access a RAM. The signals connected to RAM are address bus-lines, data bus lines and signals CS, OE and WE. TEST LDAA #AA S_LOOP STAA MemAddress * LDAB MemAddress BRA S_LOOP * End of program * cyclicly to/from a memory address * The program writes/reads * Test loop of a memory chip. First oscilloscope channel displays the signal CS; the second OE or CS or WR. Triggering to CS signal which comes before and ends after the signal OE and WE 2, we we expect to observe signals similar to the read cycles shown in time diagrams. 2 the later are valid only on the second (high) cycle of E clock CHALMERS Lindholmen 23
Wire-wrapping and other practical details Wirewrap is an technology to interconnect electronics that was popular few decades ago 3. It has the advantages that it is easily modifiable, and easy to create prototype systems but, on the other hand, it is quite labor intensive. Considering the learning process we are going through and relatively small size of the system we are building we would take advantage of wire-wrapping technique, see 4 3 The wirewrap technology declined in use because the PC board technology costs dropped and allowed higher density. Also PC boards allowed for a more controlled signal environment which was required for faster logic see http://www.pdp8.net/wirewrap/wirewrap.html 4 http:// www.okindustries.com/products/4.1.1.1.htm for practical details CHALMERS Lindholmen 24