EC-801 Advanced Computer Architecture Lecture 5 Instruction Set Architecture I Dr Hashim Ali Fall 2018 Department of Computer Science and Engineering HITEC University Taxila!1
Instruction Set Architecture (An Overview)!2
Instruction Set Architecture (ISA) Serves as an interface between software and hardware. Provides a mechanism by which the software tells the hardware what should be done. High level language code : C, C++, Java, Fortran, compiler Assembly language code: architecture specific statements assembler Machine language code: architecture specific bit patterns software instruction set hardware!3
Instruction Set Design Issues Instruction set design issues include: Where are operands stored? registers, memory, stack, accumulator How many explicit operands are there? 0, 1, 2, or 3 How is the operand location specified? register, immediate, indirect,... What type & size of operands are supported? byte, int, float, double, string, vector... What operations are supported? add, sub, mul, move, compare...!4
Classifying ISAs Accumulator (before 1960, e.g. 68HC11): 1-address: add A acc acc + mem[a] Stack (1960s to 1970s): 0-address: add tos tos + next Memory-Memory (1970s to 1980s): 2-address: add A, B mem[a] mem[a] + mem[b] 3-address: add A, B, C mem[a] mem[b] + mem[c] Register-Memory (1970s to present, e.g. 80x86): 2-address: add R1, A R1 R1 + mem[a] load R1, A R1 mem[a] Register-Register (Load/Store, RISC) (1960s to present, e.g. MIPS): 3-address: add R1, R2, R3 R1 R2 + R3 load R1, R2 R1 mem[r2] store R1, R2 mem[r1] R2!5
Operands Location in Four ISA Classes GPR!6
Code Sequence C = A + B (for Four Instruction Sets) Stack Accumulator Register (register-memory) Register (load-store) Push A Push B Add Pop C Load A Add B Store C Load R1, A Add R1, B Store C, R1 Load R1, A Load R2, B Add R3, R1, R2 Store C, R3 acc = acc + mem[c] R1 = R1 + mem[c] R3 = R1 + R2!7
Types of Addressing Modes (VAX) Addressing Mode Example Action 1. Register direct Add R4, R3 R4 <- R4 + R3 2. Immediate Add R4, #3 R4 <- R4 + 3 3. Displacement Add R4, 100(R1) R4 <- R4 + M[100 + R1] 4. Register indirect Add R4, (R1) R4 <- R4 + M[R1] 5. Indexed Add R4, (R1 + R2) R4 <- R4 + M[R1 + R2] 6. Direct Add R4, (1000) R4 <- R4 + M[1000] 7. Memory Indirect Add R4, @(R3) R4 <- R4 + M[M[R3]] 8. Autoincrement Add R4, (R2)+ R4 <- R4 + M[R2] R2 <- R2 + d 9. Autodecrement Add R4, (R2)- R4 <- R4 + M[R2] R2 <- R2 - d 10. Scaled Add R4, 100(R2)[R3] R4 <- R4 + M[100 + R2 + R3*d] Studies by [Clark and Emer] indicate that modes 1-4 account for 93% of all operands on the VAX.!8
Types of Operations Arithmetic and Logic: Data Transfer: Control: System: Floating Point: Decimal: String: Graphics: AND, ADD MOVE, LOAD, STORE BRANCH, JUMP, CALL OS CALL, VM ADDF, MULF, DIVF ADDD, CONVERT MOVE, COMPARE (DE)COMPRESS!9
MIPS Instructions All instructions exactly 32 bits wide Different formats for different purposes Similarities in formats ease implementation 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct R-Format 6 bits 5 bits 5 bits 16 bits op rs rt offset 6 bits 26 bits op address I-Format J-Format!10
MIPS Instruction Types Arithmetic & Logical - manipulate data in registers add $s1, $s2, $s3 or $s3, $s4, $s5 $s1 = $s2 + $s3 $s3 = $s4 OR $s5 Data Transfer - move register data to/from memory load & store lw $s1, 100($s2) $s1 = Memory[$s2 + 100] sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Branch - alter program flow beq $s1, $s2, 25 if ($s1==$s1) PC = PC + 4 + 4*25 else PC = PC + 4!11
MIPS Arithmetic and Logical Instructions Instruction usage (assembly) add dest, src1, src2 sub dest, src1, src2 and dest, src1, src2 dest=src1 + src2 dest=src1 - src2 dest=src1 AND src2 Instruction characteristics Always 3 operands: destination + 2 sources Operand order is fixed Operands are always general purpose registers Design Principles: Design Principle 1: Simplicity favours regularity Design Principle 2: Smaller is faster!12
Arithmetic & Logical Instructions (Binary Representation) 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct Used for arithmetic, logical, shift instructions op: Basic operation of the instruction (opcode) rs: first register source operand rt: second register source operand rd: register destination operand shamt: shift amount (more about this later) funct: function - specific type of operation Also called R-Format or R-Type Instructions!13
Arithmetic & Logical Instructions (Binary Representation Example) Machine language for add $8, $17, $18 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct 0 17 18 8 0 32 Decimal 000000 10001 10010 1000 00000 100000 Binary!14
MIPS Data Transfer Instructions Transfer data between registers and memory Instruction format (assembly) lw $dest, offset($addr) sw $src, offset($addr) load word store word Uses: Accessing a variable in main memory Accessing an array element!15
Instruction Set Architecture I!16
Introduction Platform Hardware Programmable Processor Software Program to run How can we execute program on our own design processor? Higher Level Languages Assembly Language Low Level Languages [Machine Level]!17
Programmable Hardware Combinational Circuit A specific Function Memory We can store what ever we want RAM, ROM (One time) Configurable Combinational Logic Decoder + 1 bit RAM Decoder + m bit RAM ALU Control Unit + Operations!18
Configurable Logic Block (CLB) Any Boolean Function of 3 inputs can be implemented!!!19
CLB: Multiple Functions of 3 Inputs!20
Example BCD to 7-segment Decoder!21
Programmable Machine Machine Input Code + Data Output Desired Output Stored Program Architecture Jon von Neumann!22
The Abstract Machine Addresses Data Instructions Programmer-Visible State PC Program Counter Register File Heavily used Data Condition Codes Memory Byte Array Code + Data Stack!23
Computing with Peripheral / IO Computer Systems Internal [ Processor + Memory (RAM) ] Peripheral [Disk, Display, Audio etc ]!24
Store Program Architecture Instruction get store in memory Data get store in memory CPU read instruction one by one and execute Instruction AND/OR/ADD/SUB/MUL/DIV/SLT, Load, Store, Move, Branch Data get from input There are also instructions for I/O control Data may be send to output There are also instructions for I/O control!25
Example of Instruction Program Add two numbers stored at locations 2000 and 2001, write result at location 5000!26
Example Schematic View of Computer 0000 0001 0002 0003 0004 0005 2000 2001 5000!27
Work to DO in an Instruction Read Instruction Decode Instruction Do the Work Set PC, Read Memory, Write to Register, Read Registers, Register to T1, Register to T2, Operation, R to Reg, Store to Memory Increment PC!28
Tasks to DO in an Instruction Read Instruction Decode Instruction Do the Work Set PC, Read Memory, Write to Register, Read Registers, Register to T1, Register to T2, Operation, R to Reg, Store to Memory Increment PC How much tasks to do? Instruction Designer decides!29
Instruction Set Design Keep all the instruction simple Number of tasks is unto 1 to 4 Size of instruction are almost same Load/Store are separated from Arithmetic Instruction (INS) Load and Store are separate instructions No complex instruction Controller and Data path simpler RISC based Instructions are mixed of complex and simple instruction Number of tasks is unto 1 to 20 CISC based!30
Instruction Set How many different types of instruction Examples are: One Instruction Set Computer OISC : 1 (instruction) Reduced Instruction Set Computer RISC : Around 80 Application-specific Instruction Set Processor ASIP : 100 Complex Instruction Set Computer CISC : Around 3000!31
Instruction Set Size Cost of Hardware Power Area Design Time (of Hardware) Code Size (OISC smaller/bigger) Compile Time CISC Huge, may not take advantage of all the hardware Execution Time (Performance)!32
The Instruction Set Architecture (ISA) - Problems - Algorithms - Language (Program) Programmable Computer Specific Manufacturer Specific!33
What Constitutes ISA? Main Features: Set of basic/primitive operations Storage structure Registers/Memory How addressees are specified How instructions are encoded Operations: How many? Which ones? } Instruction Format: Size How many formats? Operands: How many? Location Types How to specify? We will look at some of the decisions facing an instruction set architect, and How those decisions were made in the design of the MIPS instruction set.!34
RISC vs. CISC!35
RISC vs. CISC MULT 2:3, 5:2 CISC vs. LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A RISC!36
Instruction Length!37
Instruction Length!38
How many Operands?!39
How many Operands?!40
How many Operands? Burroughs 6500, 7500 0 address machine add values on top of stack!41
How many Operands? Intel 8080, PDP-8 1 address machine Acc = Acc + x (Acc is implicit)!42
How many Operands?!43 2 address machine r1 = r1 + r2 3 address machine r1 = r2 + r3
Instruction Set!44
MIPS Instruction Formats!45
MIPS Accessing the Operands!46
MIPS Instruction Set!47
Memory Organization!48
Memory Organization!49
MIPS Instructions / Operations Arithmetic ADD, SUB etc. Logical AND, OR etc. Relational Less than etc. Branch/jump Conditional Branch Unconditional Jump Data movement Load, Store Procedure linkage!50
MIPS ISA Features Addressing Purpose Operand sources Result destinations Jump targets Addressing modes Immediate Register Base/index PC relative (pseudo) Direct Register indirect!51
Location of operands R/M R-R : both operands in registers R-M : one operand in register and one in memory M-M : both operands in memory R+M: combines R-R, R-M and M-M!52
MIPS Instructions!53
A Basic MIPS Instruction C code: a = b + c ; Assembly code: (human-friendly machine instructions) add a, b, c # a is the sum of b and c Machine code: (hardware-friendly machine instructions) 00000010001100100100000000100000 Translate the following C code into assembly code: a = b + c + d + e;!54
Example C code a = b + c + d + e; translates into the following assembly code: add a, b, c add a, b, c add a, a, d or add f, d, e add a, a, e add a, a, f Instructions are simple: fixed number of operands (unlike C) A single line of C code is converted into multiple lines of assembly code Some sequences are better than others the second sequence needs one more (temporary) variable f!55
Subtract Example C code f = (g + h) (i + j); Assembly code translation with only add and sub instructions:!56
Subtract Example C code f = (g + h) (i + j); translates into the following assembly code: add t0, g, h add f, g, h add t1, i, j or sub f, f, i sub f, t0, t1 sub f, f, j Each version may produce a different result because floating-point operations are not necessarily associative and commutative more on this later!57
Operands In C, each variable is a location in memory In hardware, each memory access is expensive if variable a is accessed repeatedly, it helps to bring the variable into an on-chip scratchpad and operate on the scratchpad (registers) To simplify the instructions, we require that each instruction (add, sub) only operate on registers Note: the number of operands (variables) in a C program is very large; the number of operands in assembly is fixed there can be only so many scratchpad registers!58
Registers The MIPS ISA has 32 registers (x86 has 8 registers) Why not more? Why not less? Each register is 32-bit wide (modern 64-bit architectures have 64-bit wide registers) A 32-bit entity (4 bytes) is referred to as a word To make the code more readable, registers are partitioned as $s0-$s7 (C/ Java variables), $t0-$t9 (temporary variables)!59