CS2 Computer Systems note 1a Some MIPS instructions More details on these, and other instructions in the MIPS instruction set, can be found in Chapter 3 of Patterson and Hennessy. A full listing of MIPS instructions is given in Appendix A.10 of the same book. All instructions are a single 32-bit word, and each is word-aligned in memory, ie occupies bytes at addresses 4n, 4n+1, 4n+2 and 4n+3. Add Symbolic representation: add r1, r2, r3 Adds the contents of registers r2 and r3, and stores the result in register r1. (Overflow is ignored in the simulated processor in Practical 2) bits 31..26 the main opcode, 0 for the add instruction bits 25..21 first source register, r2 bits 20..16 second source register, r3 bits 15..11 destination register, r1 bits 5..0 the sub-function of opcode 0, 32 for the add instruction Subtract Symbolic representation: sub r1, r2, r3 Subtracts the contents of registers r3 from r2, and stores the result in register r1. (Overflow is ignored in the simulated processor in Practical 2) bits 31..26 the main opcode, 0 for the sub instruction bits 25..21 first source register, r2 bits 20..16 second source register, r3 bits 15..11 destination register, r1 1
bits 5..0 the sub-function of opcode 0, 34 for the sub instruction Add immediate Symbolic representation: addi r1, r2, n Adds the integer n to the contents of register r2, and stores the result in register r1. (Overflow is ignored in the simulated processor in Practical 2) bits 31..26 the opcode, 8 for the addi instruction bits 25..21 source register, r2 bits 20..16 destination register, r1 bits 15..0 the integer n, as a 16-bit 2 s-complement number, which is signextended Load word Symbolic representation: lw r1, n(r2) Adds the integer n to the contents of register r2, and uses the resulting integer to address memory and read the word at that address, which is stored in register r1. bits 31..26 the opcode, 35 for the lw instruction bits 25..21 base address register, r2 bits 20..16 register to be loaded, r1 bits 15..0 the integer n, as a 16-bit 2 s complement number, which is signextended Store word Symbolic representation: sw r1, n(r2) Adds the integer n to the contents of register r2, and uses the resulting integer to address memory, storing the word in register r1 at that address. bits 31..26 the opcode, 43 for the lw instruction bits 25..21 base address register, r2 2
bits 20..16 register to be stored, r1 bits 15..0 the integer n, as a 16-bit 2 s complement number, which is signextended Branch on equal Symbolic representation: beq r1, r2, label Compares the contents of registers r1 and r2, and if they are equal branches to the address indicated by label. bits 31..26 the opcode, 4 for the beq instruction bits 20..16 register r2 bits 15..0 an integer, represented as a 16-bit two s complement number, which is multiplied by 4 and sign-extended to 32 bits, and then added to the address of the following instruction, and the result stored in the Program Counter to effect the branch. Branch on not equal Symbolic representation: bne r1, r2, label Compares the contents of registers r1 and r2, and if they are not equal branches to the address indicated by label. bits 31..26 the opcode, 5 for the bne instruction bits 20..16 register r2 bits 15..0 an integer, represented as a 16-bit two s complement number, which is multiplied by 4 and sign-extended to 32 bits, and then added to the address of the following instruction, and the result stored in the Program Counter to effect the branch. Set less than Symbolic representation: slt r1, r2, r3 If the contents of register r2 is less than the contents of register r3, stores 1 into register r1, else stores 0 into register r1. The contents of r2 and r3 are interpreted as 32-bit 2 s-complement signed numbers. 3
bits 31..26 the opcode, 0 for the slt instruction bits 25..21 register r2 bits 20..16 register r3 bits 15..11 register r1 bits 5..0 the subfunction of opcode 0, 42 for the slt instruction Set less than immediate Symbolic representation: slti r1, r2, n If the contents of register r2 is less than the integer n, stores 1 into register r1, else stores 0 into register r1. The contents of r2 is interpreted as a 32-bit 2 s complement number. bits 31..26 the opcode, 10 for the slti instruction bits 25..21 register r2 bits 20..16 register r1 bits 15..0 the integer n, as a 16-bit 2 s-complement number, which is signextended to 32 bits before the comparison. Jump Symbolic representation: j target Unconditionally jump to the address indicated by target. bits 31..26 the opcode, 2 for the jump instruction bits 25..00 an integer, represented as a 26-bit number, which is multiplied by 4 and sign-extended to 32 bits, and then stored in the Program Counter to effect the branch. Jump and link Symbolic representation: jal target Save the address of the following instruction in register $ 31, and unconditionally jump to the address indicated by target. 4
bits 31..26 the opcode, 3 for the jal instruction bits 25..00 an integer, represented as a 26-bit number, which is multiplied by 4 and sign-extended to 32 bits, and then stored in the Program Counter to effect the branch. Jump register Symbolic representation: jr r1 Unconditionally jump to the address in register r1. bits 31..26 the opcode, 0 for the jr instruction bits 20..6 unused, set to 0 bits 5..0 the subfunction of opcode 0, 8 for the jr instruction Halt This final instruction is not a real MIPS instruction, but is included for the purposes of Practical 2. Symbolic representation: halt Causes the simulated processor/memory system in CS2 Practical 2 to halt. bits 31..26 the opcode, 0 for the halt instruction bits 25..6 unused, set to 0 bits 5..0 the subfunction of opcode 0, 12 for the halt instruction 2001-2004 Marcelo Cintra (2000 Tim Hopkins) 5