M Product Reliability OVERVIEW Microchip Technology Inc. s products provide competitive leadership in quality and reliability, with demonstrated performance of less than 1 FITs (Failures in Time) operating life for most products. The designed-in reliability of Microchip s products are supported by ongoing reliability data monitors. This document presents current data for your use - to provide you with results you can count on. The test descriptions included in this document explain Microchip s quality and reliability system. The product data demonstrates its results. The customer s quality requirements are Microchip s top priority. Ongoing customer feedback and device performance monitoring drive Microchip, leading to continuing improvements in the long-term quality and reliability. FAILURE RATE CALCULATION Extended field life is simulated by using high ambient temperature. In the semiconductor technology, high temperatures dramatically accelerate the mechanisms leading to component failure. Using performance results at different temperatures, an activation energy is determined using the Arhenius equation. For each type of failure mechanism, the activation energy expresses the degree to which temperature increases the failure rate. The activation energy values determined by Microchip Technology agree closely with those published in the literature. For complex CMOS devices in production at Microchip Technology, an activation energy of.6 ev has been shown to be representative of typical failures on operating life. This activation energy also applies to some of our retention bake failures, though most are 1.2eV. By definition, failure is reached when a device no longer meets the data sheet specifications as a direct result of the reliability test environment to which it was exposed. Common failure modes for CMOS integrated circuits are identified for each test environment. To establish a field failure rate, the acceleration factor is applied to the device operating hours observed at high temperature stress and extrapolated to a failure rate at 55 C ambient temperature in still air. The actual failure rate experienced could be considerably less than that calculated if lower device temperatures occur in the application board, such as would be the case if a fan, a heat sink, or air flow by convection is used. Environment Dynamic Life Temperature Cycle Autoclave Retention. Bake High Temp. Reverse Bias DEFINITIONS Typical Failure Mechanism Process parameter drift/shift Metal electromigration Internal leakage path Lifted bond/ball bond chip-out Lifted bond/ball chip-out Cracked die or surface cracks Bond pad corrosion Inter-pin leakage Charge loss Charge loss Charge gain, Parameter drift/ shift FIT (Failure In Time): Expresses the estimated field failure rate in number of failures per billion power-on device-hours. 1 FITS equals.1% fail per 1, device-hours. Dynamic Life Test: The device is dynamically exercised at a high ambient temperature (usually 125 C) to quickly simulate field life. Derating from high temperature, an ambient use condition failure rate can be calculated. Temperature Cycle: The devices are exposed to severe extremes of temperature in an alternating fashion (-65 C for 1 minutes, 15 C for 1 minutes per cycle). Package strength, bond quality and consistency of assembly process are stressed using this environment. Autoclave (pressure cooker): Using a pressure of one atmosphere above atmospheric pressure, plastic packaged devices are exposed to moisture at 121.5 C. The pressure forces moisture permeation of the package and accelerates related failure mechanisms, if present, on the device. Microwire is a registered trademark of National Semiconductor. 1998 Microchip Technology Inc. DS118K-page 1
Thermal Shock: Exposes devices to extreme temperatures from -55 C to +125 C by alternate immersion in liquid media. Retention Bake: A 15 C temperature stress is used to accelerate charge loss in the memory cell and measure the data retention on the EPROM and EEPROM portions of the circuitry. HAST: Moisture, extreme heat and bias are used to accelerate corrosion and contamination in plastic packages. The conditions are 13 C and 85% relative humidity. Typical bias voltage is +5 Volts and ground on alternating pins. RELIABILITY CONTROL SYSTEM A comprehensive qualification system ensures that released products are designed, processed, packaged and tested to meet both design functionality and strict reliability objectives. Once qualified, a reliability monitor system ensures that wafer fabrication and assembly process performance is stable over time. A set of baseline specifications is maintained that states which changes require requalification. These process changes can only be made after successful demonstration of reliability performance. This system results in reliable field performance, while enabling the smooth phase-in of improved designs and product capability. RELIABILITY DATA SUMMARY Introduction This section provides a reliability summary of Microchip Technology's product. Included is reliability data and packaging information obtained over the recent past. Plastic Package Characteristics and Codes As part of an on going product program, Microchip Technology will apply its Quality and Reliability process in evaluating the latest developments in plastic packaging technology, and implement the highest reliability materials and assembly techniques. The plastic packages that are currently available from Microchip are listed in the table below. Package Description Identification Code Package Description Plastic Leadless Chip Carrier Plastic Dual In Line (6) Plastic Dual In Line (3) Plastic SOIC (.15) Plastic SOIC (.27) Plastic SOIC (.3) Plastic TSOP (8 x 2mm) Plastic SSOP (.27) Identification Code L P SP SL/SN SM SO TS SS FIGURE 1: RELIABILITY CONTROL SYSTEM DIAGRAM DESIGN AND DEVELOPMENT Specify: Design objectives/specifications Testability goals Reliability requirements Process/packaging requirements Design guidelines Design: Functional models Logic design & verification Circuit design & verification Layout design & verification Prototype verification Performance characterization Develop (as required): Wafer fabrication processes Package/packaging technology QUALIFICATION Confirm design objectives using qualification tests: Dynamic life, 125 C ambient Temp-cycle, -65 /15 C Thermal shock, -55 /125 C ESD, ± 4 V HBM ESD, ± 4 V MM Latch-up (CMOS devices) Autoclave (pressure cooker) retention bake RELIABILITY CONTROL Assure Outgoing Quality Level: Design release document Baseline wafer fabrication process Baseline assembly process Qualification release Enter device to specification system Wafer-level reliability controls Assembly reliability controls Early failure rate sampling Reliability monitoring Statistical process control feedback Audit specifications Analyze returned failures Requalify devices as needed for major changes such as ESD resistance enhancement, cost reduction/die shrink, process improvement, and new package types. HIGH TEMPERATURE (125 C) DYNAMIC LIFE TEST DS118K-page 2 1998 Microchip Technology Inc.
Graph set for EEPROM, PICmicro and EPROM for all conditions FIGURE 4: PICMICRO MCU DYNAMIC LIFE High temperature dynamic life testing accelerates random failure modes which would occur in user applications. Voltage bias and address signals are used to exercise the device in a manner similar to user systems. 3 25 2 27 FIGURE 2: EEPROM DYNAMIC LIFE FIT Rate (FITs) 15 1 8 18 18 39 43 5 31 16 21 13 19 6 14 12 1989 199 1991 1992 1993 1994 1995 1996 1997 97 FIT Rate (FITs) 1 8 6 With removal of 26 DLT 4 37 3 fails due to wafer sort program error 2 15 11 18 4 199 1991 1992 1993 1994 1995 1996 1997 FIGURE 3: EPROM DYNAMIC LIFE 45 45 4 35 3 FIT Rate (FITs) 25 2 15 115 114 16 1 6 55 5 15 14 199 1991 1992 1993 1994 1995 1996 1997 PICmicro is a trademark of Microchip Technology Inc. 1998 Microchip Technology Inc. DS118K-page 3
DATA RETENTION BAKE Data storage in applicable devices is done by developing a charge on the floating gate structure in the memory cell. Charge loss in this cell structure results in a conversion of zeroes to ones. This bake accelerates charge loss in the memory cell and 168 hours at 15 C is equivalent to greater than 25 years in the field at 55 C. FIGURE 5: EEPROM RETENTION BAKE FIGURE 7: FIT Rate (FITs) 7 65 6 5 4 3 2 PICMICRO MCU RETENTION BAKE 1 25 23 1 14 2 12 8 1989 199 1991 1992 1993 1994 1995 1996 1997 2 FIT Rate (FITs) 15 1 73 5 7 4 199 1991 1992 1993 1994 1995 1996 1997 FIGURE 6: EPROM RETENTION BAKE 16 15 14 12 1 FIT Rate (FITs) 8 6 55 78 4 38 32 2 1 199 1991 1992 1993 1994 1995 1996 1997 DS118K-page 4 1998 Microchip Technology Inc.
PCT (PRESSURE COOKER AUTOCLAVE) Autoclave testing is used to determine the resistance of the package to moisture under high temperature and humidity conditions. This test accelerates failure modes caused by delamination, corrosion or ionic contamination. Operating Hours Package 24 168 MQFP /22 /2199 PDIP /892 1/8134 PLCC /2746 /2746 SOIC /1442 7/1485 TSOP /25 /25 PCT Failure Modes: 1 Unit of 8L PDIP (24LC2B) failed due to high IDDs. 1 Unit of 28L SOIC (9764) failed due to die surface delamination. 4 Units of 8L SOIC (24LC4B) failed due to column defects 1 Unit of 8L SOIC (24LC4B) failed due to oxice breakdown in the charge pump. 1 Unit of 8L SOIC (24LC4B) failed functinality at high speed. TEMPERATURE CYCLING This thermal tests evaluates air to air rapid temperature change evaluating built in material stresses. This is a worst case simulation of system power up/power down and is based on stringent military packaging requirements. Operating Results Package 1 Cycles MQFP /5 PDIP /26 PLCC /742 SOIC 1/3346 TSOP /8 TC Failure Modes: 1 Unit of 18L SOIC (PIC16C62) failed programming a bit column. THERMAL SHOCK Thermal shock is the most extreme case of temperature cycling by using liquid immersion for the technique to change the device environment. This accelerates any stress related failures with the rapidly changing gradient. After the temperature stressing a constant force centrifuge test is also preformed prior to final electrical testing to further uncover any defects that may have occurred under stress. Operating Results Package 1 Cycles QFP /53 PDIP /175 PLCC /69 SOIC /323 TSOP /8 HAST (13 /85% R.H.) Highly Accelerated Stress Testing evaluates plastic encapsulated devices ability to withstand extreme high temperature, high humidity environments while under electrical bias. This stress is designed to create corrosion of the metal or internal device leakage if ionic contaminants are present but also may cause charge loss in memory cells. Operating Results Package 48 Hours 168 Hours QFP /175 /168 PDIP 1/4323 /431 PLCC /1857 /1854 SOIC /8168 /8142 TSOP /29 /29 HAST Failure Modes: 1 Unit of 8L PDIP (24LC32A) failed due to oxice breakdown in the charge pump. 1998 Microchip Technology Inc. DS118K-page 5
PRODUCT RELIABILITY DATA PICmicro MCUs Operating Hours Device Operation 168 18 Fails Device Hours Fit Rates, 6% CL @ 55 C ALL PICS Dynamic Life 4/232 /1578 4 12,783,12 6 Retention Bake 3/31596 /643 3 1,686,648 <1 ALL 9k PICS Dynamic Life /14718 /6633 8,44,344 1 Retention Bake 2/2279 /4216 2 6,948,312 <1 ALL 77k PICS Dynamic Life 4/4589 /2155 4 2,581,152 49 Retention Bake /5161 /138 1,738,968 <1 ALL 57k PICS Dynamic Life /3893 /179 2,157,624 1 Retention Bake 1/6156 /1149 1 1,999,368 <1 PIC16C924 Dynamic Life /1578 /66 819,54 14 Retention Bake /2157 /39 689,976 <1 PIC16C622 Dynamic Life /2436 /166 1,34,688 9 Retention Bake /3223 /66 1,95,864 <1 PIC16C84A Dynamic Life 2/76 /38 2 446,88 167 Retention Bake / / N/A PIC16C74A Dynamic Life /1264 /61 724,752 16 Retention Bake /173 /49 624,2 <1 PIC16C71 Dynamic Life / / N/A Retention Bake /145 /2 343,56 <1 PIC16C7 Dynamic Life / / N/A Retention Bake /1178 /215 378,54 <1 PIC16C63/65A Dynamic Life /1173 /46 583,464 2 Retention Bake /1567 /299 514,416 <1 PIC16C62A/64A Dynamic Life /1132 /441 56,616 21 Retention Bake /1346 /34 481,488 <1 PIC16C61 Dynamic Life /76 /38 446,88 26 Retention Bake /2114 /445 728,952 <1 PIC16C58A Dynamic Life /2399 /1139 1,359,792 12 Retention Bake /2468 /515 847,224 <1 PIC16C57 Dynamic Life /1519 /725 864,192 25 Retention Bake /2113 /48 697,74 <1 PIC16C56 Dynamic Life /1959 /948 1,125,432 2 Retention Bake /2393 /4 738,24 11 PIC16C55 Dynamic Life /1174 /462 585,312 38 Retention Bake 1/1649 /34 1 532,392 32 PIC16C54 Dynamic Life 2/231 /15 2 1,27,8 59 Retention Bake /348 /63 1,41,264 <1 PIC16C54A Dynamic Life /1787 /95 1,98,216 11 DS118K-page 6 1998 Microchip Technology Inc.
PICmicro MCUs Operating Hours Device Operation 168 18 Fails Device Hours Fit Rates, 6% CL @ 55 C Retention Bake /2516 /53 867,888 <1 PIC17C44 Dynamic Life /225 /81 1,2,6 12 Retention Bake 2/1932 /368 2 633,696 <1 PIC12C58 Dynamic Life /924 /497 572,712 21 Retention Bake /1117 /326 461,496 <1 Failure Modes: Dynamic Life 2 units of PIC16C84A failed to single bit charge loss 2 units of PIC16C54 failed to verify programming Retention Bake 2 units of PIC17C44 failed due to marginal programming 1 unit of PIC16C55 failed due to single bit charge loss 1998 Microchip Technology Inc. DS118K-page 7
DS118K-page 8 1998 Microchip Technology Inc.
Serial EEPROMs Operating Hours Device Operation 168 Hrs. 18 Hrs. Fails Device Hrs. Fit Rates, 6% CL @ 55 C ALL SERIAL Dynamic Life 1/3286 1/1344 2 16,81,8 4 EEPROMS Retention Bake 37/367 /73 37 12,181,176 <1 57k SERIAL Dynamic Life /574 /28 2,599,632 8 EEPROMS Retention Bake 1/6485 /13 1 2,181,48 <1 77k SERIAL Dynamic Life 1/27732 1/1136 2 14,21,376 5 EEPROMS Retention Bake 36/29522 /6 36 9,999,696 <1 24C1A/2A Dynamic Life /3134 /128 1,61,712 14 Retention Bake /452 /8 1,352,736 <1 24C4 Dynamic Life /194 /8 997,92 22 Retention Bake 1/2433 /5 1 828,744 <1 93LC46 Dynamic Life /2348 /96 1,2,864 18 Retention Bake /327 /6 1,12,536 <1 93LC56/66 Dynamic Life /3522 /144 1,81,296 12 Retention Bake /3562 /7 1,186,416 <1 24LC1B Dynamic Life /317 /128 1,597,176 14 Retention Bake /38 /6 1,9,344 <1 24LC2B Dynamic Life /3532 /144 1,82,976 12 Retention Bake /3464 /7 1,169,952 <1 24LC4B Dynamic Life 1/3116 /128 1 1,598,688 3 Retention Bake /3529 /7 1,18,872 <1 24LC8B Dynamic Life /195 /8 999,6 22 Retention Bake /2475 /5 835,8 <1 24LC16B Dynamic Life /1577 /64 82,536 27 Retention Bake /1988 /4 669,984 <1 24LC32A Dynamic Life /2316 1/96 1 1,195,488 41 Retention Bake 1/196 /5 1 749,28 <1 24LC65 Dynamic Life /2725 /112 1,398,6 16 Retention Bake 35/3534 /7 35 1,181,712 2 24LCS21 Dynamic Life /2747 /112 1,42,296 16 Retention Bake /2481 /5 836,88 <1 24LCS52 Dynamic Life /384 /16 198,912 111 Retention Bake /494 /1 166,992 <1 25LC8/16 Dynamic Life /48 /16 22,944 18 Retention Bake / / N/A Failure Modes: Dynamic Life 1 unit of 24LC4B failed due to a column defect 1 unit of 24LC32A failed programming Retention Bake 35 units of 24LC65 failed due to single bit charge loss 1 unit of 24LC32A failed due to single bit charge loss 1 unit of 24LC4A failed due to single bit charge loss 1998 Microchip Technology Inc. DS118K-page 9
Parallel EEPROMs Operating Hours Device Operation 168 Hrs. 18 Hrs. Fails Device Hrs. Fit Rates, 6% CL @ 55 C ALL PARALLEL Dynamic Life /1989 /8 1,6,152 22 EEPROMS Retention Bake /1958 /4 664,944 <1 28C64 Dynamic Life /1989 /8 1,6,152 22 Retention Bake /1958 /4 664,944 <1 Failure Modes: Dynamic Life N/A Retention Bake N/A EPROMS Operating Hours Device Operation 168 18 Fails Device Hrs. Fit Rates, 6% CL @ 55 C ALL EPROMS Dynamic Life /2818 /112 1,414,224 14 Retention Bake 5/3186 /72 5 1,124,928 <1 ALL 9k EPROMS Dynamic Life /423 /16 25,464 57 Retention Bake 3/496 /1 3 167,328 2 ALL 77k EPROMS Dynamic Life /2395 /96 1,28,76 18 Retention Bake 2/269 /62 2 957,6 <1 27C256 Dynamic Life /2395 /96 1,28,76 18 Retention Bake 2/269 /62 2 957,6 <1 27C512A Dynamic Life /423 /16 25,464 57 Retention Bake 3/496 /1 3 167,328 2 Failure Modes: Dynamic Life N/A Retention Bake 2 units of 27C256 failed due to single bit charge loss 3 units of 27C512A failed due to single/multiple bit charge loss DS118K-page 1 1998 Microchip Technology Inc.
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