Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2016.16.3.359 ISSN(Online) 2233-4866 Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC M. Vijayaraj 1 and K. Balamurugan 2,* Abstract Today s multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput. Index Terms SoC, NoC, Docket-NoC, Multiprocessor, Mesh topology Manuscript received Dec. 4, 2015; accepted Feb. 18, 2016 1 Government College of Engineering, Tirunelveli 2 Einstein College of Engineering, Tirunelveli E-mail : m_vijayaraj@yahoo.co.in, bala237115@gmail.com I. INTRODUCTION Moore s law pave the way for integration of many Intellectual Property Blocks (IP blocks) in a single chip called as System- on-chip (SoC). In SoC, many IP cores like DSP processor, Memory blocks etc are integrated. The semiconductor industries are working to integrate IP cores as many as possible inside a single chip. Multiprocessor SoC (MP SoC) techniques are emerging as a high speed computational system and the speed of computation leads to heavy power dissipation [1]. In MPSoC, the IP blocks can communicate with each other with the help of an on-chip network. High bandwidth communication is needed in a SoC when it is integrating with large number of IP cores. The communication between the IP blocks is still a bottleneck. The traditional methods such as bus communication system to interconnect IP cores also failed to provide an efficient communication system [2]. The communication delay in a multicore system called as latency plays an important role in the transfer of data from one core to the other. The fastest communication between the IP cores can be done by a technology called as Network-on-Chip (NoC). In NoC, instead of sending signals from one core to the other, packets are transferred to achieve high speed. The NoC system is comprised of Processing Elements (or) IP cores (or) Tiles, Network interface (NI), Routers for transferring the packets from one processing element (or) tile to other and vice versa. In the NoC, many IP cores are integrated into a single chip using network of routers. While designing the Network-on-Chip, the designer has to consider the important mechanisms such as network topology, routing algorithm, flow control mechanism (FCM), switching techniques. Routing protocols have a

360 M. VIJAYARAJ et al : PERFORMANCE ORIENTED DOCKET-NOC (DT-NOC) SCHEME FOR FAST COMMUNICATION IN NOC significant impact on the latency and power consumption of NoC-based systems. In order to avoid the blocking of packets within NoCs, some routing algorithms have to be adapted. An efficient and perfect routing algorithm which includes the fault tolerant capability and congestion tolerance capability can improve the overall performance of NoC. In our work, a 2D mesh topology is used for NoC as shown in Fig. 1. as it has many advantages over the other topologies. In this 2D mesh, each router has four neighbors (north, east, south, and west) except the corner routers.corner routers have only two ports. Each router of this mesh connected topology is tied with an IP core through Network Interface (NI). The physical connection between the routers is established by bidirectional wires. This work provides the in-depth studies on routing algorithms to discover and rectify the key problems in the current and next generation of many-core SoCs. All survey details reveal that there are more intrinsic overhead in conventional source routing and per hop running in distributed routing methods. Also the performance parameters like power consumption, latency and throughput are high, large and poor respectively. In order to eliminate all the drawbacks of NoC reported earlier, we developed a new technology which is CURVE based technology called as Docket-NoC (Dt-NoC) to improve the performance parameters. Recent studies have explored that the Distributed routing algorithm in NoC is commonly used because of its flexibility. But the major drawback of source routing is the size of the header [3]. Similarly, the source routing increases the size of the source tables and this leads to increase in the size of the chip. This scheme shrinks all the disadvantages caused by the source routing. For a 4 x 4 node Processor, our proposed technique Dt-NoC needs only 2 bits for the entire process. Similarly this Dt-NoC works without the routing table for its routing to reduce the area. 1. Related work The literature survey reveals that, in source routing the packet size is very large which leads to increase in latency. This technology is called as Baseline XY routing. In Baseline XY technique the size of the header depends on the size of the network. The header of the packet in Fig. 1. Mesh architecture of NoC. source routing contains the entire routing path to reach the destination from the source. In order to reduce the header flit, encoded technique is used to reduce the bits in the header flit of the packet. This Technique is named as EnA (also called as EA). In this method only two bits are used to represent each halfway router. The Network Interface which is available between the IP core and the router provides the two bits per hop. EnA uses the turn based model adapted in [4] stated that the incoming packets can choose any one of the four output port by 0, 90, 180, and 270 turns. In this technique the local port is considered as 0 and the packets coming from one port will not go back to the same port. According to the data available in the header, the router decides the rotation to send the packets to the output port. Table 1 illustrates encoding table used in EnA method. The next method is the Optimized Encoded Address (OEnA) to encode the header flit of the incoming packets further than EnA method. This OEnA method uses the same strategy of EnA but instead of two bits, it uses only one bit per hop after the header turns to the other dimension. These entire source routing algorithms such as Baseline XY, EnA, OEnA is also called as OEA and it

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 361 Table 1. EnA and OEnA rotational codes Dimension Before Turn After Turn Code EnA Rotation (Degrees) Code OEnA Rotation (Degrees) 00 180 00 180 01 90 01 90 10 270 10 270 11 0 11 0 00 180 0 180 01 90 1 0 10 270 -- -- 11 0 -- -- is used to add the bits to the header every time it reaches a router. This increases the number of bits in the header flit and thus increases the latency. Table 1 compares the code of both EnA and OEnA encoding techniques before turn and after turn. OEnA enhances the additional overhead of the EnA method by 25%. As the OEnA uses added only one bit to the header flit, it reduction the power consumption of bits. The authors of [5] used the OEnA methodology and formed TNoC, but it is not fully adaptive, fault tolerant and fully deadlock free [6, 7]. This work considers the source routing and distributed routing [8] techniques to provide fast routing in NoC. The objective of Dt-NoC scheme architecture is to reduce the latency by decreasing the number of bits in the header of the packets. As a clear routing method is formulated and implemented, Dt-NoC proves it is deadlock and live-lock free as it uses adaptive approach. As XY routing algorithm is simpler and fast [9, 10], in this proposed work XY routing algorithm is taken as basic reference [11]. Dt-NoC is very much reliable to modify for any topology. II. DESIGN OF DOCKET-NOC ROUTER The Dt-NoC Router has the following components circular buffer, header comparison unit, docket generating unit and cross bar switch. The circular buffer is used to store the incoming packets.circular buffer system is used to optimize the buffering process [13]. The circular buffer is useful for storing the incoming packets and transferring it to the destination, as illustrated in Fig. 2. Dt-NoC Routing architecture has a central unit called as header comparison unit which compares the X/Y coordinate of the current router with Fig. 2. Simplified block diagram of Dt-NoC Router. Table 2. Docket Generation and Docket port allotment X coord. Y coord. Router coord. Port Rot. Docket X i < X j -- X i-1,y i S 90 00 X i > X j -- X i+1,y i N 90 0φ 01 X i = X j Y i < Y j X i,y i-1 W 180 10 X i = X j Y i > Y j X i,y i+1 E 180 1φ 11 Fig. 3. Header comparison unit for docket generation. the X/Y coordinate of the destination router as shown in Fig. 3. The header comparison unit is available inside the Network Interface (NI) to compare and then produce the Docket bits. When the header reaches the router, the destination address (X, Y coordinates) of the header flit is compared with the address (X,Y coordinates) of the current router using header comparison unit. If the output of comparison gate is 1, then it denotes the packets has to choose North-South Direction (Y axis), if the output is 0 then the packet has to choose East-West Direction (X axis). The second bit of the Docket shows the exact direction whether it has to move North or South or East or West. The second bit is denoted by φ as illustrated in Table 2. The value of φ may be either 0 or 1, depends on the CURVE movement of the packet from its

362 M. VIJAYARAJ et al : PERFORMANCE ORIENTED DOCKET-NOC (DT-NOC) SCHEME FOR FAST COMMUNICATION IN NOC Fig. 4. Dt-NoC CURVE based routing scheme. Fig. 6. 16-node, 2D multicast mesh network. (East port of the Xi,Yi+1 router) as given in Fig. 5. Fig. 5. Allocation of ports. current router. When the X and Y coordinate of the current router is same as the Destination router, and then it denotes that the packet reached the destination. The CURVE based technique works based on the docket value generated by the Dt-NoC as shown in Fig. 4. If the output is 90 (+ve) then the packets move from the current router towards up (South port of the Xi-1, Yi router). If the output is 90 (-ve) then the packets move from the current router towards down (North port of the Xi+1,Yi router). If the output is 180 (-ve) then the packets move from the current router towards left (West port of the Xi,Yi-1router). If the output is 180 (+ve) then the packets move from the current router towards right When a packet moves from the source router on the way to reach the destination, the first two bit dockets are generated. This docket bits shows the packet to get the next router in the next turn. Similarly, whenever the packet crosses the intermediate router, two docket bits are generated and replaces the previous docket bit to show the path for the packet to reach the destination. Let us consider the IP core of a router (Xi,Yi) sends the message from its local router to other router (destination router (Xj, Yj)), it works according to the Dt-NoC algorithm as illustrated in Table 2. If the coordinates are in the following condition, Xi < Xj, Xi > Xj, the packets moves to Xi-1,Yi (South) or Xi+1,Yi (North) respectively. If the above condition is Xi = X j, it will look for the Y coordinates as Yi < Y j, Yi > Y j and the packets will move to either Xi,Yi-1 or Xi,Yi+1 respectively. A 16-node, 4 x 4, 2D multicast mesh network, in which Dt-NoC routing method is applied for three scenarios as given in Fig. 6. It illustrates the path for the packets with reference to the docket bit generated. The data packet has data flits [14, 15], coordinates (X and Y) of the current router and Docket bits. Each Router is supplied with the information of destination router such

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 363 as X, Y coordinates. Once the packet reaches the first current router, it compares the X coordinate of the current router with the X coordinates of the destination router. If X coordinates of the current and Source router is not same, then it checks which coordinates is larger. The Dt-NoC will work according to its algorithm as shown in the Table 3. If the X coordinates of the current router is same as the destination router, then it will check the Y coordinates of the current and destination router. If it is same then it is concluded that the packets reached the destination. If it differs then it has to move according to the Dt-NoC algorithm. For illustration of the Dt-NoC routing scheme, a 4 node SoC is considered and it is analyzed by considering the possible nodes as a Source node and the remaining node as the destination. The source node here is (0,0) and the destination node is (1,1).According to the Dt-NoC algorithm the packets takes the route shown as dotted lines in Fig. 7. Initially the docket is denoted as XX and it will change immediately as soon as the router decided its first movement. The Docket receives ZZ as soon as it reached the destination. X i X j, the router compares the X coordinates of current router with the X coordinates of destination router and the packet transverse as per the algorithm. If X i = X j,, then the router compares the Y coordinates of current router with the Y coordinates of destination router and the packet transverse as per the algorithm. X i = X j & Y i = Y j the packet reached the destination using Dt- NoC. Pseudo code for Adaptive Docket NoC Routing X i := X coordinate of Current Router X d := X coordinate of Destination Router Y i := Y coordinate of Current Router Y d := Y coordinate of Destination Router Dt := Docket Initial: Dt := XX; If X i < X d Dt = SOUTH := 00 ;else Dt = NORTH := 01 ; If X i = X d & Y i < Y d Dt = EAST := 10 ; else if X i = X d & Y i > Y d Dt = WEST := 11; If X i = X d & Y i = Y d Dt = Destination reached := ZZ; // For Adaptive Implementation Faulty path := F; E 1 := End node before F; N 1 := Total number of paths in E E 11 := Node before End node in the Original path; // If Fault occurs If N 1 = 4; F := closed; (The Opposite path of F) G := closed; Remaining path 1 : H; Remaining path 2 : J; If Y H = Y J & X H > X J ; Dt := X H ; else if Y H = Y J & X H < X J ; Dt := X J ; If X H = X J & Y H > Y J ; Dt := Y H ; else if X H = X J & Y H < Y J ; Dt := Y J ; If N 1 = 3; F := closed; (The Opposite path of F ) G := closed; Remaining path1: H; Dt := H; If N 1 = 2; F := closed; Remaining path : G; Dt := G; N 11 := 3; G := closed; Remaining path : I; Dt := I;

364 M. VIJAYARAJ et al : PERFORMANCE ORIENTED DOCKET-NOC (DT-NOC) SCHEME FOR FAST COMMUNICATION IN NOC Fig. 8. Latency vs Load traffic for various routing scheme. Fig. 7. Movement of packet from node (0,0) to (1,1). III. RESULTS AND PERFORMANCE ANALYSIS A 16-node, 4 4 multicast mesh network with interconnection links is implemented in VHSIC HDL (VHDL) to obtain experimental results. The power consumption, latency and area of each architecture are obtained by a combination of cycle-accurate RTL router simulation, VHDL synthesis done in CADENCE in order to extract experimental results. The overall performance of combining both the source and distributed routing methods is much better than the baseline XY schemes for both fixed and variable network size [16-18]. The latency (in nanoseconds) of various traffics are marked for various routing schemes shown in Fig. 8. With high injection rate the overall performance of EnA, OEnA, and Dt-NoC routing algorithms are better than the baseline XY method [19]. From Fig. 8., it is clear that the values of both EnA/OEnA has almost same value. When compared with other techniques Dt-NoC scheme is providing a better performance in terms of latency for all types of traffics. Table 3 illustrates power consumption of 16 node mesh network for all the schemes discussed here. It is proved that that Dt-NoC routing algorithm with Dt-NoC architecture consumes less power compared to other schemes. Fig. 9 shows the comparison of power consumption with the corresponding clock period. It is reported that Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85 % less than Baseline, EnA and OEnA architectures respectively. Table 4 illustrates the clock period, frequency and area of baseline XY, EnA, OEnA and Dt-NoC methods which is calculated using CADENCE software. As both EnA and OEnA added the binary bits to the header, it has more clock cycle, frequency and area compared to Dt- NoC. From the simulation, it is proved that Dt-NoC is the high speed technique by 1.84%, 10.59%, and 6.06% less clock period compared to baseline XY, EnA, OEnA respectively. As the Dt-NoC scheme eliminates the routing table, it occupies 14.29%, 8.22%, 7.57% less area than baseline XY, EnA and OEnA respectively. Table 5 illustrates the number of header bits needed for each approach and it is proved that the Dt-NoC needs only 10 bits for the entire process including the 8 bit destination address. That is the address of each router is 8 bit. Along with the 2 docket bits, the size of header is 10 bits.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 365 Table 3. Power consumption of 16 node mesh network Power Consumption (µw) Baseline XY EnA OEnA Dt-NoC Dynamic Power 260.56 210.94 186.90 76.72 Leakage Power 8.1 9.07 10.86 2.84 Total Power 268.56 220.01 197.76 79.56 Table 4. Frequency results of a 4 x 4 node mesh network Approaches Clock Period (ns) Frequency (GHz) IV. CONCLUSION Area (sq.µm) Baseline XY 0.7466 1.34 2958 EnA 0.8196 1.22 2820 OEnA 0.7801 1.28 2800 Dt- NoC 0.7328 1.36 2588 Table 5. Message Header size of various methods Approach Header bits Baseline XY 144 EnA 36 OEnA 27 Dt-NoC 10 Fig. 9. Power versus Clock period. From the analysis it is known that source routing algorithms result in large amount of information overhead to the packet s header. In this work, mathematical calculation of Dt-NoC is performed, analysed and implemented in terms of power consumption, latency, maximum frequency, and area overhead. Dt-NoC is the most efficient method which overcomes the drawbacks of both source routing and distributed routing algorithms. In the NoC communication infrastructure, wired 16 node, 2D-mesh based NoC architecture is designed, coded in VHDL language and simulated using CADENCE TSMC 18 nm technology and results were obtained. Dt-NoC has the best performance while compared to baseline and other proposed methods under running traffics for different injection rates while it only imposes two extra bits comparing to baseline. Also Dt-NoC is reported as the fastest technique comparing to baseline, EnA, and OEnA techniques by RTL based cycle accurate simulator. REFERENCES [1] Bahn J. H. and Bagherzadeh N. A generic traffic model for on-chip interconnection Networks, International Workshop on Network-on-Chip Architectures, pp. 22 29, 2009. [2] A. Balakrishnan and A. Naeemi, Interconnect network analysis of many-core chips, IEEE Trans. on Electron Devices, vol. 58, no. 9, pp. 2831 2837, 2011.. [3] W. H. Hu, C. Wang, and N. Bagherzadeh, Design and analysis of a mesh-based wireless network-onchip, J. Supercomputing, vol. 71, no. 8, pp. 2330 2846, 2014. [4] Chand Mal Samota, Naveen Choudhary and Dharm Singh Performance Evaluation of Turn Model based Routing using LBDR, Int. J. Computer Applications, vol.7, No. 2, pp.15-18, 2014. [5] A. Ben Ahmed and A. Ben Abdallah, Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures, J Parallel and Distributed Computing, vol. 74, no. 4, pp. 2229 2240, 2014. [6] J. Wu, A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model, IEEE Tran. Computers, vol. 52, no. 9, pp. 1154 1169, 2003. [7] Eghbal A, Yaghini P. M, Pedram H. and Zarandi H. R., Designing fault-tolerant network-on-chip router architecture, Int. J. Electronics, Vol.97, No.10, pp.1181 1192, 2010. [8] Flich J, Rodrigo S. and Duato J., An efficient implementation of distributed routing algorithms for NoCs, Second ACM/IEEE International Symposium on Networks-on-Chip, pp. 87 96, 2008. [9] Z. Wang, H. Ligang, W. Jinhui, G. Shuqin, and W.

366 M. VIJAYARAJ et al : PERFORMANCE ORIENTED DOCKET-NOC (DT-NOC) SCHEME FOR FAST COMMUNICATION IN NOC Wuchen, Comparison research between XY and odd-even routing algorithm of a 2-dimension 3x3 mesh topology network-on-chip, in Proceedings of WRI Global Congress on Intelligent Systems, vol. 3, pp. 329 333, 2009. [10] Gupta N, Kumar M, Laxmi V. and Gaur M.S. σlbdr: Congestion-aware logic based distributed routing for 2D NoC, 19th International Symposium on VLSI Design and Test (VDAT), pp.1-6, 2015. [11] John M.R, James R, Jose J. and Isaac E,. A Novel Energy Efficient Source Routing for Mesh NoCs, Fourth International Conference on Advances in Computing and Communications (ICACC), pp.125-129, 2014. [12] T. Moscibroda and O. Mutlu, A case for bufferless routing in on-chip networks, ACM SIGARCH Computer Architecture News, vol. 37, no. 3, p. 196, 2009. [13] T. T. Ye, L. Benini, and G. De Micheli, Packetization and routing analysis of on-chip multiprocessor networks, J. Syst. Architecture, vol. 50, no. 2 3, pp. 81 104, 2004. [14] Lotfi-Kamran P, Rahmani A, Daneshtalab M, Afzali-Kusha A. and Navabi Z., Edxy a low cost congestion-aware routing algorithm for networkon-chips,j. Syst. Architecture, Vol. 56, No.7, pp.256 264, 2010. [15] Nickray M, Dehyadgari M. and Afzali-Kusha, A., Adaptive routing using context-aware agents for networks on chips, Fourth International Design and Test Workshop (IDT), pp.1-6, 2010. [16] A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark, and J. Duato, Region-based routing: A mechanism to support efficient routing algorithms in NoCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 3, pp. 356 369, 2009. [17] Prasun Ghosal and Tuhin Subhra Das, Improved Extended XY On-chip Routing In Diametrical 2D Mesh NOC,Int.J. VLSI design & Communication Systems, vol.3, no.5, pp.199-200, 2012. [18] C. Killian, C. Tanougast, F. Monteiro, and A. Dandache, Online routing fault detection for reconfigurable NoC, in Proceedings - 2010 International Conference on Field Programmable Logic and Applications, pp. 183 186, 2010. [19] Sancho J.C, Robles A. and Duato, J., On the relative behavior of source and distributed routing in NOWs using Up/Down routing schemes, Ninth Euromicro Workshop on Parallel and Distributed Processing, pp.11-18, 2011. M. Vijayaraj completed his Bachelors of Engineering from the department of Electronics and Communication in Thiagarajar College of Engineering, Madurai, Tamilnadu, India and Masters Degree in Alagappa Chettiar College of Engineering and Technology, Karaikudi, India and PhD in Anna University Chennai. He has 25 years of teaching and research experience in the field of Wireless Communication. Currently he is working as Associate Professor in the Department of Electronics and Communication Engineering at Government College of Engineering, Tirunelveli, Tamilnadu, India. He has published his research papers in various National and International Conferences and Journals in the field of VLSI Design, wireless Communication. K. Balamurugan received his Bachelors of Engineering degree from Manonmanium Sundaranar University, Tirunelveli, India and Masters Degree from Anna University, Chennai. Currently he is Pursuing PhD under Anna University Chennai in VLSI Design. He has 10 years of teaching and research experience in the field of NoC/SoC. Currently he is working as Assistant Professor in the Department of Electronics and Communication Engineering at Einstein College of Engineering, Tamilnadu, India. He has published his research papers in the field of VLSI Design in various National, International Journals and Conferences.