PC-MIP Link Receiver Board Interface Description E. Hazen, A. Chertovskikh Boston University Rev 2. August 24, 26 1 Description and Operation This document describes briefly the PC-MIP 3-channel Link Receiver Board (LRB) Version V2.9. It consists of 3 channels of National DS9CR286 Channel Link 28-bit LVDS serial link receiver, a FIFO for each link, and an FPGA with readout logic and PCI interface. The PCI interface supports 32-bit 33MHz operation with unlimited length block transfers. This note documents the protocol and physical and electrical characteristics of the link for those wishing to implement a custom transmitter. The Channel Link chipset provides a 28-bit point-to-point data path with a continuous clock and no protocol (see data sheets[1]). The LRB can accept data from 2MHz 66MHz per link, however the link clocks must be less than or equal to twice the PCI clock speed. The three link clocks need not be the same frequency. A block diagram is shown in Figure 1. The three receivers directly transfer data to an Altera ACEX FPGA. The data is buffered in three FIFOs implemented in an external SSRAM. The raw link data format is shown in Figure 2. 28 bits are sent each clock cycle. Each carries 16 data bits, 8 Hamming code bits for error correction, two parity bits for error detection and two status bits to identify the word type. Data must be formatted in blocks as shown in Figure 3. An even number of words is always required. The minimum size block is four words: header, data, data 1 and trailer. The Event ID field should be filled in with an 8-bit block number (hopefully unique!) and the Reserved field may be used for additional 8 bits of event ID. The transmitter should send idle words when there is no data to transmit. The ECC bits are calculated (for each byte) by the transmitter as: 1
Altera ACEX 1K1 FPGA PCI 33MHz 32 bit 32MHz 64MHz 256k x 36 Synchronous ZBT SRAM 128MHz W133 3 U6 W133 1 U6 PCI Clock 32 MHz Figure 1: LRB Block Diagram H = XOR(D,D1,D3,D4,D6,D8,D1,D11,D13,D15,S1) H1 = XOR(D,D2,D3,D5,D6,D9,D1,D12,D13,S,S1) H2 = XOR(D1,D2,D3,D7,D8,D9,D1,D14,D15,S,S1) H3 = XOR(D4,D5,D6,D7,D8,D9,D1) H4 = XOR(D11,D12,D13,D14,D15,S,S1) P = XOR(D,D1,D2,D4,D5,D7,D1,D11,D12,D14,S1) and inserted in the transmitted data. 2 Physical The LRB is designed to comply with the PC-MIP[2] standard. Photographs of a board are shown in Figure 4. Each link input uses a 1-pin RJ-45 type header with special keying. The PCB connector is Steward P/N SS-6411S-A-NF-RMK4. The mating cable connector is Stewart P/N 94- SP-311R-RMK4. The pinout of the input connector is shown in Table 1. Cables should be twisted-pair with 1Ω impedance. 2
28 26 25 24 23 22 21 2 19 18 17 16 15 14 13 12 11 1 9 8 7 6 5 4 3 2 1 Bit# S2 S1 P H3 H2 H1 H P H3 H2 H1 H ECC Bits D7 D6 D5 D4 D3 D2 D1 D D7 D6 D5 D4 D3 D2 D1 D Data Bits Byte 1 with DCC Byte with ECC S2 S1 State Header 1 Data 1 Trailer 1 1 Idle Byte 1 Byte Channel ID Event ID User data User data Event ID Errors Figure 2: Link Data Format. One 28-bit link word is shown. Pin Function Pin Function Note 1 Rx 2 Rx+ Pair 1 3 Rx1 4 Rx1+ Pair 2 5 Rx2 6 Rx2+ Pair 3 7 CLK 1 CLK+ Pair 5 9 Rx3 8 Rx3+ Pair 4 References Table 1: Link Connector Pinout [1] +3.3V Rising Edge Data Strobe LVDS 28-Bit 66MHz Channel Link Receiver, National Semiconductor. Available at: http://www.national.com/pf/ds/ds9cr285.html [2] PC-MIP Specification. VITA 29 Draft.92b, 2 June 1999. Available at http://ohm.bu.edu/~hazen/my_d/std/pc-mip_2spec_2r92b.pdf 3
Header Data Data 1 Data 2 Pair 1 Pair 2 Block 1 Data N Trailer Pair M Header Data Data 1 Data 2 Pair 1 Pair 2 Block 2 Data N Trailer Pair M Figure 3: Block Data Format. Each word shown represents one 28-bit link word. 4
LVDS Inputs PCI Bus Link 1 Link 2 Link 3 Programming Connector Figure 4: LRB Photos 5