ILI2511. ILI2511 Single Chip Capacitive Touch Sensor Controller. Specification ILI TECHNOLOGY CORP. Version: V1.4. Date: 2018/7/5

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Single Chip Capacitive Touch Sensor Controller Specification Version: V1.4 Date: 2018/7/5 ILI TECHNOLOGY CORP. 8F., No.1, Taiyuan 2 nd St., Zhubei City, Hsinchu County 302, Taiwan (R.O.C.) Tel.886-3-5600099; Fax.886-3-5600055 http://www.ilitek.com

Revision History Version Date Page Description V1.01 2016/8/10 All Preliminary released V1.02 2016/9/19 6,7,17,18 Modify the pin description & application circuit. V1.03 2016/10/27 6,7 Modify the pin assignment & pin description. V1.04 2016/11/3 2 Modify the page information of revision history. V1.05 2016/11/28 4,17,18 Modify the feature and application circuit. V1.06 2017/2/9 4.7,10,11 Modify VDDIO operation voltage V1.07 2017/3/28 14,15 Modify Power Sequence V1.08 2017/5/18 9,10,11,13 Modify Recommended Operating Conditions, DC Characteristics, I2C DC Characteristics V1.1 2017/9/7 All Final Specification released V1.2 2017/10/13 All Change VDDIO From 5V into 3.3V V1.3 2017/12/20 All Add VDDIO 3.3V or 1.8V Input Power Supply Characteristics Add Marking Information V1.4 2018/7/5 10,11 Modify Input Power Supply Voltage Range Page 2 of 19

Table of Content REVISION HISTORY... 2 TABLE OF CONTENT... 3 1. DESCRIPTION... 4 2. FEATURES... 4 3. BLOCK DIAGRAM... 5 4. PIN DEFINITION... 6 4.1 QFN-88 PIN ASSIGNMENT... 6 4.2 QFN-88 PIN DESCRIPTION... 7 5. ELECTRICAL CHARACTERISTICS... 9 5.1 ABSOLUTE MAXIMUM RATINGS... 9 5.2 RECOMMENDED OPERATING CONDITIONS... 10 5.3 DC CHARACTERISTICS... 11 5.4 I2C AC CHARACTERISTICS... 13 6. POWER SEQUENCE... 14 6.1 POWER-ON SEQUENCE... 14 6.2 POWER-OFF TO POWER-ON SEQUENCE... 15 7. PACKAGE INFORMATION... 16 7.1 QFN-88 PACKAGE DIMENSION... 16 7.2 MARKING INFORMATION... 17 8. TYPICAL APPLICATION CIRCUIT... 18 8.1 USB APPLICATION CIRCUIT... 18 8.2 I2C APPLICATION CIRCUIT... 19 Page 3 of 19

1. Description The is a single chip capacitive touch sensor controller optimized for POS, ATM and Industry Capacitive Touch Panel applications. It integrates high speed Capacitance to Digital Converter (CDC), total 65 channels including high voltage Driving and Sensing channels, high voltage Charge Pump Controller, high voltage regulator and 32-bit high performance Micro-controller (MCU). With compact QFN-88 package, its package size is 10mm*10mm*1mm and pad pitch is 0.4mm. meets all Windows 8.1 and Windows 10 requirements with best user touch experience and highest noise immunity performance. 2. Features 65 channels for capacitive touch panel Flexible driving or sensing channel assignment Max TX channel number is 42 Max RX channel number is 41 Programmable driving voltage for driving channels High voltage charge pump controller with programmable high voltage regulator High speed ADC converter Support baseline calibration function Support mutual-capacitance sensing Support self-capacitance sensing Built-in noise processing function Support IEC 61000-4-6 (CS test), Level 3: 10Vrms Built-in 1.8V LDO for 1.8V operation of VDDIO for I2C and GPIO Built-in 32-bit high performance Micro-controller (MCU) Input voltage low level detection circuit Input voltage power on reset circuit Driving to Sensing mutual capacitance: 1pF to 4pF Page 4 of 19

3. Block Diagram LDO LVD HV Charge Pump USB I2C UART 32-bit CPU core OSC XTAL PLL Flash ROM Memory Timer SRAM 65-ch HV I/O CDC Figure 3-1: Block Diagram Page 5 of 19

4. Pin Definition 4.1 QFN-88 Pin Assignment Bottom View TX[13] TX[12] TX[11] TX[10] TX[9] TX[8] TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] VDDIO RSTN INT UART_TX SCK SDA VTX VGH GND 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 TX[14] 66 1 C2N TX[15] 65 2 C2P TX[16] 64 3 C1N TX[17] 63 4 C1P TX[18] 62 5 C0N TX[19] 61 6 C0P TX[20] 60 7 VDD3D TX[21] 59 8 DM TX[22] 58 9 DP TX[23] 57 10 VDD TX[24] 56 11 VDD16 RX[41] 55 12 XTAL_IO1 RX[40] 54 13 XTAL_IO2 RX[39] 53 14 VDD3A RX[38] 52 15 RX[1] RX[37] 51 16 RX[2] RX[36] 50 17 RX[3] RX[35] 49 18 RX[4] RX[34] 48 19 RX[5] RX[33] 47 20 RX[6] RX[32] 46 21 RX[7] RX[31] 45 22 RX[8] 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RX[9] RX[10] RX[11] RX[12] RX[13] RX[14] RX[15] RX[16] RX[17] RX[18] RX[19] RX[20] RX[21] RX[22] RX[23] RX[24] RX[25] RX[26] RX[27] RX[28] RX[29] RX[30] Figure 4-1: QFN-88 Pin Assignment Page 6 of 19

4.2 QFN-88 Pin Description Table 4-1 Pin Type Define Symbol P CLK I O I/O Power pad Clock Input only Output only (Push-pull) input / output pad Description Table 4-2 Pin Description Name Type Description VDD P 3.3V input power supply, connect 1uF capacitor to system ground VDD3D P 3.3V input power supply, connect 1uF capacitor to system ground VDD3A P 3.3V input power supply, connect 1uF capacitor to system ground VDDIO P 1.8V or 3.3V input power supply for I2C, SPI, UART, INT, RSTN, connect 2.2uF capacitor to system ground VDD16 P 1.6V regulator output, connect 1uF capacitor to system ground VTX P HV regulator output, connect 1uF capacitor to system ground VGH P Charge pump HV output, connect 1uF capacitor to system ground GND P connect to system ground C2N P Cathode of charge pump capacitor, connect 1uF capacitor to C2P C2P P Anode of charge pump capacitor, connect 1uF capacitor to C2N C1N P Cathode of charge pump capacitor, connect 1uF capacitor to C1P C1P P Anode of charge pump capacitor, connect 1uF capacitor to C1N C0N P Cathode of charge pump capacitor, connect 1uF capacitor to C0P C0P P Anode of charge pump capacitor, connect 1uF capacitor to C0N DM I/O USB interface, D- signal. DP I/O USB interface, D+ signal. XTAL_IO1 I/O External crystal input, connect 12Mhz crystal for USB application XTAL_IO2 I/O External crystal output, connect 12Mhz crystal for USB application RSTN INT I/O I/O External hardware reset input, internal pull high to VDDIO, pull high resistance is about 4.7kΩ. Interrupt output, internal pull high to VDDIO, pull high resistance is about 4.7kΩ. Page 7 of 19

UART_TX I2C_SCL I2C_SDA I/O I/O I/O UART TXD output, internal pull high to VDDIO, pull high resistance is about 4.7kΩ. I2C interface, clock input, internal pull high to VDDIO, pull high resistance is about 4.7kΩ. I2C interface, data input, internal pull high to VDDIO, pull high resistance is about 4.7kΩ. RX[1:23] I/O Typical touch panel sensing channels RX[24:41] I/O Typical touch panel sensing channels and can be configured to driving channels TX[1:24] I/O Typical touch panel driving channels EPAD P connect to system ground Page 8 of 19

5. Electrical Characteristics 5.1 Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Table 5-1: Absolute Maximum Ratings Parameter Symbol Min Max Unit Chip power input V DD -0.3 3.6 V V DD3A to GND V DD3A -0.3 3.6 V V DD3D to GND V DD3D -0.3 3.6 V V DDIO to GND V DDIO -0.3 3.6 V V DD16 to GND V DD16-0.3 1.65 V V GH to GND V GH -0.3 32 V V TX to GND V TX -0.3 32 V ESD Susceptibility HBM (Human Body Mode)(Note 1) HBM 4000 V ESD Susceptibility MM (Machine Mode) (Note 1) MM 400 V Operating Ambient Temperature Range T A -40 85 ºC Operating Junction Temperature Range T J -40 125 ºC Storage Ambient Temperature Range T ST -40 150 ºC Note 1: Devices are ESD sensitive. Handling precaution is recommended. Page 9 of 19

5.2 Recommended Operating Conditions Table 5-2: Recommended Operating Conditions Parameter Symbol Min Max Unit V DD to GND input power supply voltage V DD 3.0 3.6 V V DD3A to GND V DD3A 3.0 3.6 V V DD3D to GND V DD3D 3.0 3.6 V V DDIO (3.3V) to GND V DDIO 3.0 3.6 V V DDIO (1.8V) to GND V DDIO 1.7 1.9 V V DD16 to GND V DD16 1.55 1.65 V V GH to GND V GH 23 32 V V TX to GND V TX 19 21 V Operating Ambient Temperature Range T A -40 85 ºC Operating Junction Temperature Range T J -40 125 ºC Storage Ambient Temperature Range T ST -40 150 ºC Note: The device is not guaranteed to function outside its operating conditions. Page 10 of 19

5.3 DC Characteristics Table 5-3: Input Power Supply (VDD3A=VDD3D=3.3V, Room Temperature) Item Symbol Min Typ. Max Unit Condition Digital input power supply voltage* V DD3D 3.0 3.3 3.6 V Analog input power supply voltage V DD3A 3.0 3.3 3.6 V 3.3V I/O input power supply voltage* V DDIO 3.0 3.3 3.6 V 1.8V I/O input power supply voltage* V DDIO 1.7 1.8 1.9 V *If VDDIO & VDD3D is not supplied power, there is risk of I/O pin with current leakage Table 5-4: DC Characteristics (VDD3A=VDD3D=3.3V, Room Temperature) Item Symbol Min Typ. Max Unit Condition Operation current I op 100 ma Active Mode @ 21.5 Input Low Voltage V IL1 0 0.3V DDIO V Input High Voltage V IH1 0.6V DDIO V DDIO +0.5 V Hysteresis voltage V HY 0.2V DDIO V Input Low Voltage, XT_In V IL2 0 0.6 V V DDIO =3.3V Input High Voltage, XT_In V IH2 2.6 V DDIO +0.2 V V DDIO =3.3V Negative going threshold, /Reset Positive going threshold, /Reset V ILS 0 0.2V DDIO V V IHS 0.6V DDIO V DDIO +0.5 V Output High Voltage V OH 0.7V DDIO V Output Low Voltage V OL 0.3V DDIO V V DDIO =3.3V, I OH =8mA V DDIO =3.3V, I OL =10mA Page 11 of 19

Table 5-5: USB DC Characteristics Item Symbol Min Typ. Max Unit Condition Input Low V IL 0.8 V Input High (driven) V IH 2.0 V Differential input sensitivity V DI 0.2 V (D+) (D-) Differential common-mode range V CM 0.8 2.5 V Includes VDI range Single-ended receiver threshold V SE 0.8 2.0 V Receiver hysteresis V RH 200 mv Output low (driven) V OL 0 0.3 V Output high (driven) V OH 2.8 3.6 V Output signal cross voltage V CRS 1.3 2.0 V Pull-up resistor R PU 1.425 1.575 kω Pull-down resistor R PD 14.25 15.75 kω Termination Voltage for upstream port pull up (RPU) V TRM 3.0 3.6 V Table 5-6: Crystal Characteristics Item Symbol Min Typ. Max Unit Condition Input clock frequency f XIN 12 MHz External crystal Page 12 of 19

5.4 I2C AC Characteristics Table 5-7: I2C AC Characteristics Parameter Symbol Standard-mode Fast-mode Min Max Min Max Unit SCL clock frequency f SCL 0 100 0 400 khz Hold time START condition t HD;STA 4.0-0.6 - us LOW period of the SCL clock t Low 4.7-1.3 - us HIGH period of the SCL clock t High 4.0-0.6 - us Set-up time for a repeated START condition t SU:STA 4.7-0.6 - us Data hold time t HD;DAT 300-300 - ns Data set-up time t SU;DAT 250-100 - ns Rise time of both SDA and SCL signals (30% to 70%) t r - 1000 20 300 ns Fall time of both SDA and SCL signals (70% to 30%) t f - 300 20 300 ns Set-up time for STOP condition t SU;STO 4.0-0.6 - us Bus free time between a STOP and START condition t BUF 4.7-1.3 - us Capacitive load for each bus line C b - 400-400 pf Noise margin at the LOW level for each connected device Noise margin at the HIGH level for each connected device V nl 0.1V DD - 0.1V DD - V V nh 0.2V DD - 0.2V DD - V *SCL = I2C Host must to support clock stretching mode for using 400 khz. Page 13 of 19

6. Power Sequence 6.1 Power-on Sequence V VDD 0.9 * VDD ~ VDDIO 0.9 * VDDIO ~ ~ RSTN USB or I2C Commands & INT Start to report location By USB or I2C ~ USB/I2C/INT T1 T2 T3 T4 Time 1. T1: the time difference between 0.9*VDD and 0.9*VDDIO. T1 must be 0 sec. 2. T2: the time difference between 0.9*VDDIO and RSTN. T2 must be 200 us. 3. T3: the time difference between RSTN and Commands.T3 must be 150 ms. 4. T4: IC start to report point location to host. T4 must be 300 ms. Page 14 of 19

6.2 Power-off to Power-on Sequence V VDD ~ 0.5V RSTN ~ Tg1 Tg2 Tg1 : the time difference between power-off and power-on. Tg1 must be > 10us. Tg2 : the time difference between power-off and power-on. Tg2 must be > 10us. Note. During the power off time, the VDD must be lower than 0.5V that make sure the touch controller have been correctly reset. Page 15 of 19

7. Package Information 7.1 QFN-88 Package Dimension Top View Bottom View Figure 7-1: Package Information of QFN-88 Page 16 of 19

7.2 Marking Information Column 1: ILITEK Logo Column 2: Product Code Code 1~4: Model Name Code 5: Package Type, Q: QFN Code 6~9: Package Fab Control Number Column 3: Package Assembly Lot No Column 4: Wafer Lot No Page 17 of 19

8. Typical Application Circuit 8.1 USB Application Circuit 3.3Vdc VDD C0P C0N VDD3A C1P C1N 1.8Vdc/3.3Vdc 2.2uF / 25V VDD3D VDD16 VDDIO RSTN C2P C2N VGH VTX XTAL_IO1 12MHz XTAL_IO2 TX[1:24] TX[1:24] UART to HOST Controller UART_TX RX[1:41] RX[1:41] USB to HOST Controller DM DP I2C to HOST Controller I2C_SCL I2C_SDA GND INT Figure 8-1: USB Application Circuit Page 18 of 19

8.2 I2C Application Circuit 3.3Vdc VDD C0P C0N VDD3A C1P C1N 1.8Vdc/3.3Vdc 2.2uF / 25V VDD3D VDD16 VDDIO RSTN C2P C2N VGH VTX XTAL_IO1 12MHz XTAL_IO2 TX[1:24] TX[1:24] RX[1:41] RX[1:41] UART to HOST Controller UART_TX I2C_SCL I2C to HOST Controller I2C_SDA GND INT Figure 8-2: I2C Application Circuit Page 19 of 19