WHAT HAPPENS WHEN THE FLASH INDUSTRY GOES TO TLC? Luanne M. Dauber, Pure Storage

WHAT HAPPENS WHEN THE FLASH INDUSTRY GOES TO TLC? Luanne M. Dauber, Pure Storage

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Abstract Leveraging Flash Memory in Enterprise Storage Solid state storage promises to transform the capabilities and economics of the performance storage market, which is increasingly the mainstream of enterprise storage. The main difference between between these systems and traditional storage is one thing: the storage medium. One of its defining characteristics is that semiconductor technology changes a lot. The pending introduction of TLC will increase the capacity per area, what will the impact be on data integrity and resiliency? How are these new cells different from previous and what should you know about them? 3

Agenda Under the Hood: How Flash Cells Work TLC: An Opportunity and a Threat Who is Driving the Roadmap? Correction Codes Predictions for the Future 4

How Flash Cells Work Floating Gate Electrons Tunnel and Get Trapped in Gate Source Drain 5

What is Flash Wear? Floating Gate Electrons tunnel through oxide to charge the floating gate Electron traps interfere with charge Source Drain 6

Impact of Geometry Shrink 7

Flash Device Architecture Erase Block Write Page Read Flash Cells are Arranged Like a Classroom Cells Share Routing Resources to Reduce Space (and Cost/Power) They Read/Write/Erase in Different Sizes Erases take longest 8

Read Write Disturb 9

Write Amplification Erase Block 1 Erase Block 2 You need to move, I am going to erase this block. Erase Block 3 You need to move, I am going to erase this block. 10

What is SLC/MLC/TLC? Smaller and smaller windows to determine signal s value 1 11 111 110 10 101 100 8 States 01 011 010 0 00 001 Incoming Signals Single bit Multi bit TLC 11

MLC: The Opportunity & Threat Higher Density! Lower Power! Cost per Bit! Less Reliable! Shorter Life Cycle! Unclear Performance! GO FLASH!! 12

The Next Flash Cell is Error Prone Source: Characterization and ECC for TLC Flash, UCSD 13

Correcting Errors Errors Occur During All Operations: Erase, Write, and Read At Every Hierarchy: Cell, Page, Chip TLC errs differently than MLC Disturbing bits is easier in TLC SLC and MLC TLC Hamming codes or CRC Typically handled by the controller chip in an SSD BCH or Low Density Parity Check (LDPC) 14

Keep Opportunity/Punt Threat Keep the Benefits of TLC cost, power, density Eliminating the Threats for Enterprise Use is a Team Effort Chip suppliers will bring more sophisticated ECC Storage system makers need to take on extending life, normalizing performance, and correcting errors 15

Conclusion The Flash Industry Will Find <Partial> Solutions The cost benefits are material ECCs will end up in the chips Could be imperfect implementation in first releases Necessary but not sufficient for enterprise applications Software Heals the Flash Cell Extending the max P/E cycles to match or exceed MLC Solves problem at system level Other Cell Types May Find a Foothold MRAM, FeRAM must succeed in consumer to work for us 16

Attribution & Feedback The SNIA Education Committee would like to thank the following individuals for their contributions to this Tutorial. Authorship History Additional Contributors Luanne Dauber / September 2012: Updates: Please send any questions or comments regarding this SNIA Tutorial to tracktutorials@snia.org 17