LAB 4: Seven Seg, Full Adder, Ripple Adder, Heirarchical Design

Engineering 303 Digital Logic Design LAB 4: Seven Seg, Full Adder, Ripple Adder, Heirarchical Design Build the following designs and verify correct operation. This lab uses hierarchical design. Review Part 2 - Qartus II Tutorial: Hierarchical Diagram Design Simulation from lab 1 before you do section 3 of this lab. Deliverables: 0) Seven Segment Decoder 1) Full Adder 2) 8-bit Ripple Carrry Adder 3) 8-bit Ripple Carrry Adder with Hexadecimal Display Demonstration Requirement: Demonstrate Part 3 RippleAdder with seven segment display on the DE2 board from the last part of this lab. Part 0 A Verilog Binary to Hexadecimal Seven-Segment Decoder This is an important design that you will be using the rest of the semester. Make sure it works!! Using Verilog, design and implement a circuit that will receive a 4-bit value from switches, and output a 7- bit code to drive a seven-segment display. The display will output a hexadecimal value between 0 (decimal 0) and F (decimal 15). Here is the diagram for the 7-segment decoder, and the segment numbers. B 4 Just combo logic in here 7 S SSdecode For example, 0000 (hex 0), should turn on all segments except segment 6. Another example, 0011 (hex 3), should turn on segments 0, 1, 2, 3, and 6. Another example, 1010 (hex A), should turn on all segments except 3. The signals to activate (turn on) individual segments on the DE2 board are "active low". This means that a logic level 0 turns a segment ON. For example if "S0" through "S6" are all logic 0, the display will show an 8. Engineering 303 Lab 4 Folsom Lake College Page 1 of 9

Your truth table will look like this, the first row is done for you. It is important that you number the signals left-to-right from "most significant bit" (msb) to "least significant bit" (lsb), as shown here. For example B3 thru BO, left to right. Inputs Outputs Hex B3 B2 B1 B0 S6 S5 S4 S3 S2 S1 S0 minterm 0 0 0 0 0 1 0 0 0 0 0 0 b3 b2 b1 b0 1 0 0 0 1 1 1 1 1 0 0 1 b3 b2 b1 b0 2 0 0 1 0 0 1 0 0 1 0 0 b3 b2 b1b0 3 0 0 1 1 0 1 1 0 0 0 0 b3 b2 b1b0 4 0 1 0 0 0 0 1 1 0 0 1 b3 b2b1 b0 5 0 1 0 1 0 0 1 0 0 1 0 b3 b2b1 b0 6 0 1 1 0 0 0 0 0 0 1 0 b3 b2b1b0 7 0 1 1 1 1 1 1 1 0 0 0 b3 b2b1b0 8 1 0 0 0 0 0 0 0 0 0 0 b3b2 b1 b0 9 1 0 0 1 0 0 1 0 0 0 0 b3b2 b1 b0 A 1 0 1 0 0 0 0 1 0 0 0 b3b2 b1b0 b 1 0 1 1 0 0 0 0 0 1 1 b3b2 b1b0 C 1 1 0 0 1 0 0 0 1 1 0 b3b2b1 b0 d 1 1 0 1 0 1 0 0 0 0 1 b3b2b1 b0 E 1 1 1 0 0 0 0 0 1 1 0 b3b2b1b0 F 1 1 1 1 0 0 0 1 1 1 0 b3b2b1b0 Makes the seven seg display 0 Use Verilog design entry. Use the project name SevenSeg. Method 1 Sum of Products (SOP) Boolean Equations One may simply write the Sum of Products (SOP) Boolean equations for S0..S7 from the truth table and enter the equations into Quartus using Verilog. For example, S0 = (1,4,b,d) = b3 b2 b1 b0 + b3 b2b1 b0 + b3b2 b1b0 + b3b2b1 b0. The Verilog for this is shown below. Note that it is not necessary to simplify the equations using K-maps. You can essentially just enter the unsimplified SOP minterms. The following Verilog template can be used as a guide. Note that for convenience we can declare all 4 bits of B as a group using the syntax [3:0] B. In your equations, reference individual bits using B[0] and so forth. Below is a partial solution, you would need to complete the Verilog by entering the remaining SOP expression for S[1] through S[6]. // A 4-Bit Binary to Seven-Segment Decoder module SevenSeg (B, S); input [3:0] B; // declare a set of 4 inputs wires output [6:0] S; // declare 7 bit output to drive seven segment LED // SOP equations from the truth table // First one is done for you, you determine the rest assign S[0] = ~B[3] & ~B[2] & ~B[1] & B[0] ~B[3] & B[2] & ~B[1] & ~B[0] B[3] & ~B[2] & B[1] & B[0] B[3] & B[2] & ~B[1] & B[0]; // etc... all the way to assign S[6] endmodule Engineering 303 Lab 4 Folsom Lake College Page 2 of 9

Method 2 Use a Case statement to create a Verilog design Another method that we will learn about latter in the class is to use a case statement. The case statement is recommended as it reduces the likely hood of a typographic errors common with the SOP method. The case statement checks the value of B and ouputs the binary value specified in the list. In Verilog case statements must appear inside always statements which we will study latter in the class. Make sure to include the endcase clause before endmodule. Below is a parial solution Verilog code that you will need to complete. // A 4-Bit Binary to Seven-Segment Decoder module SevenSeg (B, S); input [3:0] B; // declare a set of 4 inputs wires output reg[6:0] S; // declare 7bit output register to drive seven segment LED // Binary output from the truth table // First and last two are done for you, you determine the rest always@(*) case(b) 0: S=7 b100_0000; //binary value from truth table 1: S=7 b111_1001; //etc.. complete the rest of the case statements for 2-13 14: S=7 b000_0110; 15: S=7 b000_1110; endcase endmodule Use either method to create a Verilog design for the seven segment decoder. Simulate your design. When simulating, be sure to group your inputs in descending order from "most significant bit" (msb) to "least significant bit" (lsb), as shown. Drag and drop signals to arrange them. You will need to use 16 x 0.1us = 1.6 us end time to test all sixteen of your inputs. Verify that your waveform matches your truth table. This is an important design that you will be using the rest of the semester. Make sure it works!! Program your design to the DE2 board using the following pin outs and verify the LED displays the correct values 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, b, C, d, E, F. In your report, include the Verilog design and simulation waveforms. Signal Name DE2 Name DE2 Pin DE2-115 Pin S[0] HEX0[0] PIN_AF10 PIN_G18 S[1] HEX0[1] PIN_AB12 PIN_F22 S[2] HEX0[2] PIN_AC12 PIN_E17 S[3] HEX0[3] PIN_AD11 PIN_L26 S[4] HEX0[4] PIN_AE11 PIN_L25 S[5] HEX0[5] PIN_V14 PIN_J22 S[6] HEX0[6] PIN_V13 PIN_H22 Engineering 303 Lab 4 Folsom Lake College Page 3 of 9

LAB 4 SIGNAL DE2 Name DE2 Pin DE2-115 Pin B[0] SW[0] PIN_N25 PIN_AB28 B[1] SW[1] PIN_N26 PIN_AC28 B[2] SW[2] PIN_P25 PIN_AC27 B[3] SW[3] PIN_AE14 PIN_AD27 Part 1 A Full Adder Block Diagram Simulation Use a block diagram design to implement the full adder circuit shown below. Use the project name FullAdder. This circuit adds 3 bits to produce a 2-bit binary sum. For example, the last row shows 1+1+1=11, binary 3. Inputs A B Carry In Outputs Carry- Out 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Sum Simulate your design and verify that the waveform matches the truth table. Include the design and your results in the lab report. Part 2 Heirarchical Design Alpha - A Ripple Carry Adder Implement an 8-bit serial adder composed of full-adder modules, from Part 1 of this lab, chained together. This circuit will add 2 numbers A and B, where each number is an 8-bit value between 0000 0000 (decimal 0, hex 00) and 1111 1111 (decimal 255, hex FF). Below is a diagram for a 4-bit version. Implement the 8-bit version, given in the detailed Quartus block diagram at the end of this document. Engineering 303 Lab 4 Folsom Lake College Page 4 of 9

4-bit Ripple Carry Adder The RippleAdder adder module uses the FullAdder module from Part 1 of this lab. This technique is known as "instantiation". Instantiation is how we implement complex heirachical design. Hint: Review Part 2-Qartus II Tutorial: Hierarchical Diagram Design from lab 1 before you continue. Create the symbol files from the FullAdder project you made in the previous part. Then create a new Quartus project for the RippleAdder, named RippleAdder8bit, and reference the Full Adder project in the Project Library. Then you will be able to insert the FullAdder into your RippleCarry adder project file. Helpful Hint: Insert an initial single instance of the FullAdder then add the input and outputs and label s0, a0, b0. Select all and copy (CNTL-C) and paste (CNTL-V) and Quartus will auto increment the I/O names to s1, a1, b1. Repeat and place one a top the other until you have a total of eight instances. Now connect cout to cin as shown and complete the design. When testing the waveform, make sure A, B and S bits are arranged from MSB to LSB (top to bottom). For example A=(A7,A6,A5,A4,A3,A2,A1,A0), B=(B7,B6,B5,B4,B3,B2,B1,B0) and SUM=(Cout, S7,S6,S5,S4,S3,S2,S1,S0). Drag and drop to arrange the signals in order then group and subgroup the signals as shown. Make sure to include Cout as the MSB of SUM. Change the radix from Binary to unsigned decimal to simplify reading. Set the step size to 100 or 200nS to accommodate for the propogation delay of a ripple carry adder. For our purposes we need only simulate a subset for verification before testing the final design on the DE2 board. For example, you can test A = 2, 3 and set count on B to range 0 to 255. Set Cin to logic zero before simulating. Here is a section of the waveform showing 3 + 36 = 39. Seems to work, but you should also examine your waveform carefully for several other values. Include the diagram and sample waveform segment in the lab report. Engineering 303 Lab 4 Folsom Lake College Page 5 of 9

Part 3 Heirarchical Design - Ripple Carry Adder with Hex Display Hexadecimal display is useful when testing larger designs on the DE2 board. Use a block diagram design to combine the seven segment decoder and the ripple carry adder. The final circuit will display the hexadecimal equivalent of the binary adder output. You will create a new RippleCarry8bitDecode project, and reference the subprojects (and the subsubproject) using the Project Library. Remember to export the symbol files from the subprojects first. You must include the three subprojects SevenSeg, FullAdder, and RippleAdder8bit. The design shown below uses a bus to group wires together. A bus is just a set of wires. Use the Orthogonal Bus Tool to draw buses to connect things. Use the Orthogonal Node Tool to draw single wires to connect to the bus. Single wires are connected to a bus by name matching (see Hint). Be sure to ground the carryin (Cin) input using the GND symbol. Helpful Hint: Select the wire to be named then right click and select properties then enter the name (eg A[0]) and then select OK. To name a bus do the same although use a bus naming (eg Sum[7..0]). Name buses and individual wires as shown below so that things are hooked up correctly. For testing on hardware, it is often usefull to run some internal signals out of the design so that we can look at their values on the hardware. These extra output signals are sometimes called hooks. For this design the adder outputs S[7..0] have been run out as hooks. Connect all the module outputs including to DE2 pins. Enter, compile, simulate, verify the design given below. Fully document all this in your report. The waveform would look something like shown below. You should check the output of a few sample input sequences on the waveform before you download to DE2 hardware. But, it is actually much easier to test this design on the DE2 device than it is with the waveform. Engineering 303 Lab 4 Folsom Lake College Page 6 of 9

You must demo this part so you will need to assign pins and download to DE2 hardware. For your convenience, here are the pins for the 0 th and 1 st hex displays: Signal Name DE2 Pin DE2-115 Pin HEX0[0] PIN_AF10 PIN_G18 HEX0[1] PIN_AB12 PIN_F22 HEX0[2] PIN_AC12 PIN_E17 HEX0[3] PIN_AD11 PIN_L26 HEX0[4] PIN_AE11 PIN_L25 HEX0[5] PIN_V14 PIN_J22 HEX0[6] PIN_V13 PIN_H22 HEX1[0] PIN_V20 PIN_M24 HEX1[1] PIN_V21 PIN_Y22 HEX1[2] PIN_W21 PIN_W21 HEX1[3] PIN_Y22 PIN_W22 HEX1[4] PIN_AA24 PIN_W25 HEX1[5] PIN_AA23 PIN_U23 HEX1[6] PIN_AB24 PIN_U24 Engineering 303 Lab 4 Folsom Lake College Page 7 of 9

Multibit values must be displayed left-to-right, from most-significant-bit (msb) to least-significant-bit (lsb). Use the following pins for the OUTPUT Sum[7..0] LAB 4 SIGNAL DE2 Name DE2 Pin DE2-115 Pin Sum[0] LEDR[0] PIN_AE23 PIN_G19 Sum[1] LEDR[1] PIN_AF23 PIN_F19 Sum[2] LEDR[2] PIN_AB21 PIN_E19 Sum[3] LEDR[3] PIN_AC22 PIN_F21 Sum[4] LEDR[4] PIN_AD22 PIN_F18 Sum[5] LEDR[5] PIN_AD23 PIN_E18 Sum[6] LEDR[6] PIN_AD21 PIN_J19 Sum[7] LEDR[7] PIN_AC21 PIN_H19 Use the following pins for INPUTS A and B LAB 4 SIGNAL DE2 Name DE2 Pin DE2-115 Pin A[0] SW[0] PIN_N25 PIN_AB28 A[1] SW[1] PIN_N26 PIN_AC28 A[2] SW[2] PIN_P25 PIN_AC27 A[3] SW[3] PIN_AE14 PIN_AD27 A[4] SW[4] PIN_AF14 PIN_AB27 A[5] SW[5] PIN_AD13 PIN_AC26 A[6] SW[6] PIN_AC13 PIN_AD26 A[7] SW[7] PIN_C13 PIN_AB26 B[0] SW[8] PIN_B13 PIN_AC25 B[1] SW[9] PIN_A13 PIN_AB25 B[2] SW[10] PIN_N1 PIN_AC24 B[3] SW[11] PIN_P1 PIN_AB24 B[4] SW[12] PIN_P2 PIN_AB23 B[5] SW[13] PIN_T7 PIN_AA24 B[6] SW[14] PIN_U3 PIN_AA23 B[7] SW[15] PIN_U4 PIN_AA22 Demonstrate your RippleAdder with seven segment display to the instructor. Engineering 303 Lab 4 Folsom Lake College Page 8 of 9

Ripple Carry 8-Bit Adder Design Engineering 303 Lab 4 Folsom Lake College Page 9 of 9