DP-8020 Hardware User Guide
Revision History The following table shows the revision history for this document. Section General updates Revision Summary 12/06/2018 Version 1.0 Initial Xilinx release. DP-8020 Hardware User Guide www.xilinx.com 2
Table of Contents Revision History... 2 Chapter 1: DP-8020 Introduction... 4 Chapter 2: Board Setup and Configuration... 6 Board Component Location... 6 Default Switch and Jumper Settings... 8 Chapter 3: Hardware Design Introduction... 9 ZU2 MPSOC... 9 DDR4 Chips... 12 Flash... 12 Clock... 12 Reset... 14 I2C Bus... 14 USB... 15 Gigabit Ethernet... 15 Display Port... 15 PCIe... 15 Micro-SD... 16 Debugging UART0... 16 CAN Bus... 16 JTAG... 17 GPIO... 17 Fan... 18 12V Power Supply... 18 Appendix A: Legal Notices... 19 Please Read: Important Legal Notices... 19 DP-8020 Hardware User Guide www.xilinx.com 3
Chapter 1: DP-8020 Introduction DP-8020 is a standard half-height & half-length PCIe board based on Xilinx XCZU2EG-2SFVA625I MPSOC (multiprocessor system-on-chip). DP-8020 with 2GB DDR4 and 8GB emmc Flash. External interfaces are PCIe, USB 3.0, Gigabit Ethernet, Display Port, Micro SD card socket, Debug UART, JTAG, CAN, GPIO etc. al. DP-8020 can be used as PCIe daughter card or work independently powered by DC- 12V power adapter. Block diagram of DP-8020 board is shown in the following figure. USB Ethernet LED Display_Port _Aux(eMIO) PCIe x2 USB3.0 Display Port PL_GPIO DDR4 32-bit PS_REF_CLK JTAG,PS_MODE PS_POR HW_Version PL_GPIO SDIO,SPI1 UART0&1,I2C0 PS_GPIO 8GB emmc CAN,PS_GPIO Figure 1: DP-8020 Block Diagram DP-8020 features are as follows: XCZU2EG-2SFVA625I MPSOC 2GB DDR4 (32bit) 8GB emmc Flash, support emmc boot Support SD card boot Support JTAG boot USB 3.0 PCIe 2.0 ( x2 lane) Display Port Gigabit Ethernet USB-UART Serial port CAN DP-8020 Hardware User Guide www.xilinx.com 4
GPIO LED DC-12V Power Supply Board Size: 68.90mm x 167.65mm Work Temperature: 0 ~45 DP-8020 Hardware User Guide www.xilinx.com 5
Chapter 2: Board Setup and Configuration Board Component Location The following figure shows component locations of DP-8020 board. Each numbered component shown in the following figure is keyed to Table 1. Table 1: DP-8020 Board Components and Functions Figure 2: DP-8020 Board Components Callout Ref. Des. Component/Function 1 U1 XCZU2EG-2SFVA625I 2 U5, U6 MT40A512M16JY-083E:B 2 pcs 8Gb DDR4, totally 2GB 3 U4 MTFC8GAKAJCN-1M WT, 8GB emmc Flash 4 J1 Micro SD card socket 5 J11 USB UART Interface (Micro-B USB connector, and CP2103 is the bridge IC) 6 J12 CAN BUS header 7 J14 JTAG header DP-8020 Hardware User Guide www.xilinx.com 6
Table 2: DP-8020 Board Components and Functions (Cont d) 8 J13 General GPIO header 9 J15 DC-12V power connector 10 SW1 Switch(MPSOC boot mode selection) 11 J18 12V power header for Fan 12 J10 PCIe x4 Connector(DP-8020 supports x2 mode only) 13 J6 USB3.0 Type-A socket 14 D8 Work status indicator LED(Red LED for 3.3V voltage,green LED for board status) 15 J3 RJ45 socket 16 K1 Manual Reset button 17 J9 Display Port socket 18 U9 KSZ9031RNXIC,Gigabit Ethernet PHY 19 U10 USB3320C-EZK,USB PHY 20 J8 Power supply header for USB Host mode 21 J17 USB port mode select header. 22 D3 Error indicator LED for USB-5V power supply 23 D1 LED connected with PS_MIO34 24 D5 Indicator LED for Display Port power supply 25 D7 Indicator LED for DC-12 power input DP-8020 Hardware User Guide www.xilinx.com 7
Default Switch and Jumper Settings Refer to Table 3 for switch and jumper default settings. Table 3: Switch and Jumper Default Settings SW1 J8 J17 Function FPGA boot Mode selection ON = pull down = 0 OFF = pull up = 1 SW1-4: Not used SW1-3: PS_MODE2 SW1-2: PS_MODE1 SW1-1: PS_MODE0 MODE [2:0] = 000=JTAG 101=SD1 110=eMMC USB power supply Enable/Disable 1-2 Connection: Enable 5V power supply for USB device (Host mode) 1-2 Disconnection: No power supply from USB Port (Device mode) USB port work mode configuration 1-2 Connection: Host mode 1-2 Disconnection:Device mode Default Configuration MODE [2:0] = 110 (boot from emmc) SW1-3: OFF SW1-2: OFF SW1-1: ON Note:PS_MODE3 is fixed as 0 Host mode 1-2 Connection Host mode 1-2 Connection DP-8020 Hardware User Guide www.xilinx.com 8
Chapter 3: Hardware Design Introduction This chapter introduces detailed hardware design on DP-8020. ZU2 MPSOC Processor Introduction Processor is XCZU2EG-2SFVA625I, which combines a powerful processing system (PS) and userprogrammable logic (PL) into the same device. Detailed resources are as follows: For detailed introduction of Xilinx Zynq UltraScale+ MPSoC devices, refer to: Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891) Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) DP-8020 Hardware User Guide www.xilinx.com 9
ZU2EG IO Banks The peripheral interfaces and Bank IO voltage of ZU2EG are listed in Table 4. Table 4: The Peripheral Interfaces and Bank IO Voltage of ZU2EG Bank No. Peripheral interface Voltage PS PL PS Bank 500 emmc, CAN, PS_GPIO 1.8V PS Bank 501 SDIO, SPI1, UART0&1, I2C0, PS_GPIO 3.3V PS Bank 502 USB2.0(ULPI), Ethernet(RGMII) 3.3V PS Bank 503 PS_REF_CLK, JTAG, PS_MODE, PS_POR 1.2V PS Bank 504 DDR4 (32-bit) 3.3V PS Bank 505 PCIe x2(gtr0&1), USB3.0(GTR2), Display Port(GTR3) PL HD Bank 26 Display_Port _Aux(eMIO), LED 3.3V PL HP Bank 64 1.8V PL HP Bank 65 HW_Version, PL_GPIO 1.8V PL HP Bank 66 PL_GPIO 1.8V ZU2EG IO Pin Assignment For ZU2EG IO Pin assignment, refer to Table 5 (PS_MIO) and Table 7 (PL_IO). Table 5: XCZU2EG PS_MIO Pin Allocation PS_MIO Definition PS_MIO Definition PS_MIO Definition MIO0 NC MIO26 FPGA_SELFRST_N MIO52 USB0 TX CLK. MIO1 NC MIO27 PS_GPIO5 MIO53 USB0 DIR MIO2 NC MIO28 PS_GPIO6 MIO54 USB0 Data 2 MIO3 NC MIO29 PS_GPIO7 MIO55 USB0 NXT MIO4 PS_GPIO1 MIO30 PS_GPIO8 MIO56 USB0 Data 0 MIO5 PS_GPIO2 MIO31 KSZ9031_RST_N MIO57 USB0 Data 1 MIO6 NC MIO32 NC MIO58 USB0 STP MIO7 PS_GPIO3 MIO33 PCIE RESET_N MIO59 USB0 Data 3 MIO8 PS_GPIO4 MIO34 PS_Debug_LED MIO60 USB0 Data 4 MIO9 NC MIO35 NC MIO61 USB0 Data 5 MIO10 CAN0 RX MIO36 NC MIO62 USB0 Data 6 DP-8020 Hardware User Guide www.xilinx.com 10
Table 6: XCZU2EG PS_MIO Pin Allocation (Cont d) PS_MIO Definition PS_MIO Definition PS_MIO Definition MIO11 CAN0 TX MIO37 NC MIO63 USB0 Data 7 MIO12 NC MIO38 UART0 RX MIO64 GEM3 TX CCLK MIO13 emmc0 Data 0 MIO39 UART0 TX MIO65 GEM3 TX Data 0 MIO14 emmc0 Data 1 MIO40 UART1 TX MIO66 GEM3 TX Data 1 MIO15 emmc0 Data 2 MIO41 UART1 RX MIO67 GEM3 TX Data 2 MIO16 emmc0 Data 3 MIO42 IIC0 SCL MIO68 GEM3 TX Data 3 MIO17 emmc0 Data 4 MIO43 IIC0 SDA MIO69 GEM3 TX CTL MIO18 emmc0 Data 5 MIO44 USB3320_RST_N MIO70 GEM3 RX CCLK MIO19 emmc0 Data 6 MIO45 SD CD MIO71 GEM3 RX Data 0 MIO20 emmc0 Data 7 MIO46 SD Data 0 MIO72 GEM3 RX Data 1 MIO21 emmc0 CMD MIO47 SD Data 1 MIO73 GEM3 RX Data 2 MIO22 emmc0 CLK MIO48 SD Data 2 MIO74 GEM3 RX Data 3 MIO23 emmc0 RESET MIO49 SD Data 3 MIO75 GEM3 RX CTL MIO24 NC MIO50 SD CMD MIO76 GEM3 MDC MIO25 NC MIO51 SD CLK MIO77 GEM3 MDIO Note: NC means this pin is not used on DP-8020. Table 7: XCZU2EG PL_ IO Allocation Table PL Bank PL_IO Definition Bank26 E12 DP_AUX_OUT Bank26 D12 DP_HPD Bank26 B12 DP_OE Bank26 A12 DP_AUX_IN Bank26 B11 Green LED indicator for D8, lighting when D8 is low Bank26 C11 PL_GPIO6 Bank65 R2 HW_VERSION1 Bank65 R1 HW_VERSION2 Bank65 U1 HW_VERSION3 Bank65 V1 HW_VERSION4 DP-8020 Hardware User Guide www.xilinx.com 11
Table 8: XCZU2EG PL_ IO Allocation Table (Cont d) PL Bank PL_IO Definition Bank65 K1 PL_GPIO9 Bank65 J1 PL_GPIO10 Bank66 H1 PL_GPIO7 Bank66 E1 PL_GPIO8 DDR4 Chips DP-8020 with two DDR4 chips (MT40A512M16JY-083E:B 8Gb,DDR4-2400), totally 2GB memory (512M x 32bits). As DDR controller of XCZU2EG-2SFVA625I only supports DDR4-2133Mbps, speed of DDR4 on DP-8020 is up to 2133Mbps. Two DDR4 chips are connected with XCZU2EG PS Bank504, while no DDR4 chip connected on XCZU2EG PL side. Flash DP-8020 board has an 8GB emmc Flash as MTFC8GAKAJCN-1M WT for filesystem and user data storage. emmc is connected with XCZU2EG PS Bank501. Refer to ZU2EG IO Pin Assignment for pin allocation information. Clock Main clock for XCZU2EG s is 33.33333MHz and is provided by crystal oscillator. PCIe reference clock (PS_MGTREFCLK0) is provided through PCIe golden finger interface. Reference clock for USB3.0 and DP display port (PS_MGTREFCLK2, PS_MGTREFCLK3) is provided by difference clock chip Si5340A. Clock system design is as shown in the following figure. DP-8020 Hardware User Guide www.xilinx.com 12
Oscillator 33M Hz PS_RefCLK PS_RefCLK ZU2-SFVA625I Oscillator 48M Hz Si5340A-D- GM USB3.0_REFCLK-26M DP_REFCLK-27M PS_GTR2 PS_GTR3 Figure 3: Clock System DP-8020 Hardware User Guide www.xilinx.com 13
Reset Reset of XCZU2EG is controlled by TPS3808. During power-up phase, TPS3808 monitors the voltage of D1V2. When D1V2 voltage is normal, TPS3808 will release the reset signal with a time delay. After power up, reset source of XCZU2EG is from manual reset (button K1) or FPGA MIO26. Refer to the following figure for reset design on DP-8020. PS_MIO26 PS_MIO33 D1V2 Sense ZU2-SFVA625I FPGA_SELFRST_N Manual Reset & TPS3808 MR_N PS_POR_B Figure 4: Reset Design I2C Bus On DP-8020, I2C0 bus is allocated to PS_MIO42 and 43, and there are two I2C devices: 1. INA226AIDGS is for measuring the power consumption of DC-12V input. I2C address is 0x 1000 000. 2. Si5340A(clock chip) is for generating the PS-GTR reference clock for USB3.0 and Display Port. I2C address is 0x 1110 100 DP-8020 Hardware User Guide www.xilinx.com 14
USB USB port on DP-8020 uses XCZU2EG PS-GTR2, with Type-A socket. USB2.0 PHY chip is USB3320, which is connected to XCZU2EG PS_MIO52~63 by ULPI bus (refer to ZU2EG IO Pin Assignment). PS_MIO PS_GTR2 ULPI USB3320 USB3.0 Type-A Connector Figure 5: USB Design USB port supports Host mode and Device mode, which is configured by J8 and J17. The default mode is Host mode (refer to Default Switch and Jumper Settings). In host mode, USB device is powered by power chip MIC2544. Gigabit Ethernet XCZU2EG PS side contains Gigabit Ethernet MAC, with PHY chip KSZ9031 (10/100/1000Mbps), DP-8020 provide one Gigabit Ethernet Port. KSZ9031 is connected to PS_MIO64~75 (refer to ZU2EG IO Pin Assignment), and could be controlled by MDIO(PS_MIO76&77). The address of KSZ9031 is 5'b00011. Display Port XCZU2EG provides a VESA DisplayPort 1.2 source-only controller. DP-8020 uses PS-GTR3 as the Display Port main link, data rate can be 1.62Gb/s,2.7Gb/s or 5.4Gb/s. Display port auxiliary signal is output from EMIO (IO pins of PL Bank26, refer to ZU2EG IO Pin Assignment), and transferred to LVDS signal DPAUX by FIN1019. Both Main link and DPAUX are connected to Display Port socket J9. PCIe DP-8020 board implements the PCIe 2.0 x2 Lane through PS-GRT0&1. PCIe interface is physically PCIe x4 (only use Lane0&1 on DP-8020). PS_MIO33 is used as PCIE_RESET_N input IO pin. DP-8020 Hardware User Guide www.xilinx.com 15
Micro-SD DP-8020 has one Micro-SD card socket, so SD card can be used as filesystem and user data storage. When Mode[2:0] (SW1) is set as 101, XCZU2EG will boot from SD card. Micro-SD card socket is connected to XCZU2EG PS Bank 501. For more details refer to ZU2EG IO Pin Assignment. Debugging UART0 UART0 (PS_MIO38&39) on XCZU2EG PS side is used for system debugging. It is transferred to USB interface by CP2103 and connected to USB Micro-B connector J11. UART0 s baud rate is configured at 115200. CAN Bus The CAN Bus is allocated to PS_MIO10&11 (1.8V) of PS bank 500. It is connected to CAN bus transceiver SN65HVD232 through TXS0104E (1.8V 3.3V). Physical interface is J12. Table 9: Pin Definition of CAN Bus Connector J12 Pin Definition J12 Pin Definition 1 GND 2 GND 3 CAN0_CANH_TERM 4 CAN0_CANH 5 CAN0_CANL 6 CAN0_CANL_TERM 7 CAN0_CANL 8 CAN0_CANH Note: CAN0_CANH_TERM and CAN0_CANL_TERM are connected to 60ohm terminating resistor. DP-8020 Hardware User Guide www.xilinx.com 16
JTAG DP-8020 has the JTAG connector J14. XCZU2EG could boot from JTAG by setting the Mode[2:0] as 000. Table 10: Pin Definition of JTAG Connector J14 Pin Definition J14 Pin Definition 1 GND 2 3.3V 3 GND 4 PS_JTAG_TMS 5 GND 6 PS_JTAG_TCK 7 GND 8 PS_JTAG_TDO 9 GND 10 PS_JTAG_TDI GPIO DP-8020 has 8 PS GPIO, one UART and 5 PL GPIO, which can all be accessed through connector J13. Also, DC-12V power pin for external power supply is provided through J13. Table 11: GPIO Pin Definition J13 Pin Definition J13 Pin Definition 3 PS_GPIO5 22 PL_GPIO6 4 PS_GPIO7 23 PL_GPIO7 7 PS_GPIO6 24 PL_GPIO8 8 PS_GPIO8 25 PL_GPIO9 11 UART1 TXD 26 PL_GPIO10 12 UART1 RXD 29,30 12V 15 PS_GPIO1 16 PS_GPIO2 17 PS_GPIO3 18 PS_GPIO4 1,2,5,6,9,10,13,14,1 9,20,27,28,31,32 GND DP-8020 Hardware User Guide www.xilinx.com 17
Fan DC-12V Fan connection schematic is shown as in the following figure. The Fan will start to work when DP-8020 is power-up. Figure 6: DP-8020 12V Fan Header 12V Power Supply Two power supply modes for DP-8020 are as follows: As a development board, it is powered through socket J15. DC-12V power adapter is used. As a PCIe daughter card, it is powered through PCIe connector. Power consumption of DP-8020 could be measured by current detection chip INA226AIDGS, which can be accessed through I2C bus. DP-8020 Hardware User Guide www.xilinx.com 18
Appendix A: Legal Notices Please Read: Important Legal Notices The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx s limited warranty, please refer to Xilinx s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos. AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS XA IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ( SAFETY APPLICATION ) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ( SAFETY DESIGN ). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.. Copyright 2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DP-8020 Hardware User Guide www.xilinx.com 19