Contents Introduction Board Operation Power options Device configuration System connection Power-on sequence Board Design Information PCB Schematic PCB Layout Reference PCB BOM List PIEQX68ZDE PIEQX68ZDE Evaluation Board Rev.B User Guide Nov.6, 0 Introduction PIEQX68ZDE Evaluation Board is designed to allow convenient testing of its operation and features. This board can work with readily available SATA and esata cables for easy connection to SATA.0 HDD, SSD, OMD storage components and PC system hosts. This board allows the PIEQX68ZDE device to be powered in +.5V directly from external power, or 5V with a mini- USB connector provided to convert. This User Guide describes the setup, configuration and operation of PIEQX68ZDE Eval Board Rev.B. Figure provides a top view of PIEQX68ZDE Eval Board Rev.B, and Figure is bottom view of the board. Figure. Top view of PIEQX68ZDE Eval board Rev.A Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page
Figure. Bottom view of PIEQX68ZDE Eval board Rev.A Board Operation PIEQX68ZDE is a -port (-channel), bi-directional, signal SATA.0 re-driver to provide indication when the load is connected to HOST or Device. Figure shows the logical block diagram of PIEQX68ZDE. Two channels of the PIEQX68ZDE are fully independent in operation and configuration by IC function. Channel configuration of output pre-emphasis, output swing and input equalization must be set appropriately to match the attached cable/trace length and type. Figure. Logical Block Diagram of PIEQX68ZDE Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page
Power Options The PIEQX68ZDE Evaluation Board provides the options for supplying +.5V directly or +5V power from mini- USB connector. Figure circles the important connections. ) Using the +5V power supplied by miniusb connector (J). The on-board LDO down-steps the voltage to +.5V. When using this source, note that jumper JP must be shorted (populated). ) Using +.5V power input directly by JP8 power pin header and JP9 ground pin header. When using this method, JP must be open. ) For PIEQX680ZDE power supply, the evaluation board is shipped from the default with +.5V from externally power supply. J VBUS D- D+ ID GND 5 +5V CON_USB.0_MiniB_SMT D LED_G + EC5 u_58 C8 0.u_00 U VIN VOUT ADJ/GND CJ7-.5V R NP_00 + EC u_58 C7 0.u_00 JP R 50ohm_00 R 0_00 JP8 JP9 + EC u_58 C 0.u_00 C 0.u_00 C 0.u_00 C 0.u_00 Figure. Power supply of PIEQX68ZDE Device Configuration The PIEQX68ZDE ReDriver supports Pre-emphasis, swing adjustment and input equalization for optimum operation and signal margins. PIEQX68ZDE provides two ways configuration controls depending on the state of the IC_EN# pin. When IC_EN# is set to HIGH (JP to ), the configuration input pins set the configuration operating state and changes to these control pins will change the operating IC_EN#. For pin configurations, there are some configuration values to be selected only. When IC_EN# pin is set to LOW (JP to GND), reprogramming of these control registers via IC is allowed. For IC configurations, all the configuration values can be used by IC as default configuration on EVB. Table shows the pin functions for pin control and IC control. Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page
PIN NAME P7:EN P8:A0/B_EQ P9:A/B_EM PIN Control FUNCTION With Internal 00k-ohm pull-up resistor High: Normal Operation Low: Power Down Mode Input Equalization for Channel B Tri-level control JP GND Open Input Equalization for Channel B 8dB db 6dB Pre-emphasis control for Channel B Tri-level control IC Control Function Same as Pin control function IC Programmable address bit A0 IC Programmable address bit A JP GND Open Input Equalization for Channel B db 0dB.5dB P0:IC_EN# P7: SDATA/A_EQ P8:APD_EN# P9: SCLK/A_EM P0:SW IC Enable High: pin control Low: IC control Input Equalization for Channel A Tri-level control by JP5 Setting Value same as P8 Auto slumber mode Enable High: disable Low: enable Pre-emphasis control for Channel A Tri-level control by JP7 Setting Value same as P9 Output Swing control for Channel A&B Tri-level control Output Swing for Channel A&B JP mv(vtx_diff_pp) at Gb/s GND 667 Open 5 900 Same as Pin control function IC Data Line Don't Care IC Clock Line Don't Care ) Pin Configurations Configuration begins with IC_EN# pin with JP, which must be connected to. The EN pin of the PIEQX68ZDE has an internal 00K pull-up resistor to define a high level default (JP0 Open) for normal operation. When EN pin is shorted to GND (JP0 is shorted to GND), device operation is disabled. This is useful for checking PIEQX68ZDE disabled-state power consumption. Figure5 is pin strap configuration for pin headers. Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page
Figure5. Pin Strap Configuration of PIEQX68ZDE Input Equalizer Setting Input equalizer setting has P7 (A_EQ) and P8 (B_EQ) tri-level configuration by JP5 and JP. So it is available with values in Blue color in Table below. Output Pre-emphasis Setting Output Pre-emphasis setting has P9 (A_EM) and P9 (B_EM) tri-level configuration by JP7 and JP. Table shows its selectable setting values. Output Swing Setting Output Swing setting has P0 (SW) tri-level configuration by JP. Table shows its selectable setting values. Auto-slumber Mode Enable Setting Auto-slumber mode enable setting has P8 (APD_EN#) configuration by JP6. When JP6 is connected to GND, auto-slumber mode will be enabled, but it is connected to, auto-slumber mode will be disabled. ) IC Configuration On PIEQX68ZDE EVB, IC_EN# pin (JP) is shorted to GND on EVB, IC configuration is enabled for all the setting as default. And P8 (JP, A0) and P9 (JP, A) pins are also shorted to GND as default IC address-c0. Figure6 is their locations on EVB and IC interface connector definition and location. Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page 5
Figure6. IC address Pins Jumper and Interface location For PIEQX68ZDE s IC interface, it is compliant with.v power. Figure7 is read/write waveform sample at the register value below for the reference. IC Write Sequence IC Read Sequence C0 DUMMY BYTE Figure7. IC Write/Read Waveform Sample NOTE that there is one dummy byte in Write Sequence. For detail IC register description, please refer to Page7-0 in datasheet. Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page 6
) Board Connection Figure8 is board connections for the reference. To Device or HDD GND From Host Figure8. Board Connection System Connection The diagrams below show some example system test setups with the PIEQX68ZDE Eval Board. Figure9 shows the connection using a NB PC and esata Express Card. Note that many notebooks PCs already offer an esata port which can be used as the test signal source without the add-in card. PIEQX68ZDE EVB Figure9. ehdd connection Test Setup using NB+eSATA Express Card with PIEQX68ZDE Eval Board Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page 7
Figure0 shows the connection using Intel MB PIEQX68ZDE EVB Figure0. internal HDD connection Test Setup using Intel MB with PIEQX68ZDE Eval Board Power-on Sequence It is recommended as good practice, that all system components be powered off while connections and configuration settings are made. There is no specific power-on sequence required when applying power to the PIEQX68ZDE Eval Board. When connected to the system and powered by USB as shown above, then all devices will power-up together. If the host PC and/or HDD are powered on, while the Eval Board is off, there will be no damage to the PIEQX68ZDE under typical conditions. If the Eval Board is then powered on, the system will generally detect the SATA HDD as a hot-plug event, and the HDD will begin to operate properly. Note that some PC systems offer BIOS control over hot plug events, and if the HDD is not recognized, this BIOS setting is the most likely cause and should be changed. When connecting to the system as shown above, all devices will power on together and avoid this BIOS issue. Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page 8
Board Design Information PCB Schematic JP8 is +.5V for PIEQX68 +.V JP7 JP6 JP9 + EC u_58 C 0.u_00 C 0.u_00 C 0.u_00 C 0.u_00 JP SCL_AEM SW APD_EN# SDA_AEQ JP5 SDA_AEQ SCL_AEM R0 0k_00 R9 0k_00 C6 0.u_00 J p-.5mm Connector JP 5 5 6 6 7 7 CON_SATA_SMT AI_P AI_N BO_C_N BO_C_P C5 C6 R6 0_00 R7 0_00 0n_00 0n_00 R AI_R_P AI_R_N BO_N BO_P NP/0_00 U HGND SW 0 9 SCLK/A_EM 9 8 APD_EN# 7 SDATA/A_EQ 7 6 6 EN A0/B_EQ A/B_EM IC_EN# AI+ AI- NC 5 BO- BO+ 5 AO+ AO- NC BI- BI+ R5 AO_P C 0n_00 AO_N C 0n_00 BI_R_N R8 0_00 BI_R_P R9 0_00 NP/0_00 AO_C_P AO_C_N BI_N BI_P JP 5 6 5 7 6 7 CON_SATA_SMT 0 6 7 8 9 PIEQX68ZDE@TQFN0 JP0 JP JP EN IC_EN# JP A0_BEQ A_BEM J VBUS D- D+ ID GND 5 +5V CON_USB.0_MiniB_SMT D LED_G + EC5 u_58 C8 0.u_00 U VIN VOUT ADJ/GND CJ7-.5V R NP_00 + EC u_58 C7 0.u_00 JP R 50ohm_00 R 0_00 PCB Layout Reference a. Stack Up: b. Isolation Spacing = 0 mil c. Width & Spacing (W/S) of 00Ω Differential Trace = 0 / 9 mil Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page 9
PCB BOM List Reference Description Package Qty U LM67-.5V SOT-5 U PIEQX68ZDE@TQFN0 TQFN0 Bare PCB PCB, PIEQX68ZDE-SATA ReDriver Rev.B PCB D LED 0805 JP,JP SATA L-type connector L-type J p-.5mm Connector.5mm J miniusb connector B-type JP PIN HEADER.5mm JP8,JP9,JP0,JP,JP, JP,JP,JP5,JP6,JP7 PIN HEADER.5mm 0 C,C,C5,C6 Ceramic Capacitor, 0nF 00 C,C,C,C,C6,C7,C8 Ceramic Capacitor, 0.uF 00 7 EC,EC,EC5 Tan cap, u 58 R Chip Resistor, 50ohm 00 R9,R0 Chip Resistor, 0Kohm 00 R,R6,R7,R8,R9 Chip Resistor, 0ohm 00 5 Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page 0
History Version.0 Original Version Nov 6, 0 Pericom Semiconductor Corp., 55 N. First Street, San Jose, California, USA 08-5-0800 www.pericom.com Page