SAM4 Reset Controller (RSTC)

APPLICATION NOTE AT06864: SAM4 Reset Controller (RSTC) ASF PROGRAMMERS MANUAL SAM4 Reset Controller (RSTC) This driver for SAM devices provides an interface for the configuration and management of the device's Reset Controller functionality. The Reset Controller manages all Resets of the System including; external devices (via the NRST pin), Processor Reset and Peripheral Reset. It also provides the status of the last reset source. The following peripherals are used by this module: RSTC (Reset Controller) The outline of this documentation is as follows: Prerequisites Module Overview Special Considerations Extra Information Examples API Overview

Table of Contents SAM4 Reset Controller (RSTC)... 1 Software License... 4 1. Prerequisites... 5 2. Module Overview... 6 2.1. NRST Manager... 6 2.1.1. NRST Signal or Interrupt... 6 2.1.2. NRST External Reset Control... 6 2.2. Reset State Manager... 6 2.2.1. General Reset... 6 2.2.2. Backup Reset... 6 2.2.3. User Reset... 6 2.2.4. Software Reset... 6 2.2.5. Watchdog Reset... 7 2.2.6. Reset State Priorities... 7 3. Special Considerations... 8 4. Extra Information... 9 5. Examples... 10 6. API Overview... 11 6.1. Macro Definitions... 11 6.1.1. Macro RSTC_BACKUP_RESET... 11 6.1.2. Macro RSTC_CPMR_KEY_PASSWD... 11 6.1.3. Macro RSTC_GENERAL_RESET... 11 6.1.4. Macro RSTC_NRST_HIGH... 11 6.1.5. Macro RSTC_NRST_LOW... 11 6.1.6. Macro RSTC_SOFTWARE_RESET... 11 6.1.7. Macro RSTC_USER_RESET... 11 6.1.8. Macro RSTC_WATCHDOG_RESET... 11 6.2. Function Definitions... 12 6.2.1. Function rstc_assert_reset_of_coprocessor()... 12 6.2.2. Function rstc_deassert_reset_of_coprocessor()... 12 6.2.3. Function rstc_disable_user_reset()... 12 6.2.4. Function rstc_disable_user_reset_interrupt()... 13 6.2.5. Function rstc_enable_user_reset()... 13 6.2.6. Function rstc_enable_user_reset_interrupt()... 13 6.2.7. Function rstc_get_reset_cause()... 14 6.2.8. Function rstc_get_status()... 14 6.2.9. Function rstc_reset_extern()... 14 6.2.10. Function rstc_set_external_reset()... 14 6.2.11. Function rstc_start_software_reset()... 15 7. Extra Information for Reset Controller Driver... 16 7.1. Acronyms... 16 7.2. Dependencies... 16 7.3. Errata... 16 7.4. Module History... 16 8. Examples for Reset Controller Driver... 17 8.1. Quick Start guide for SAM RSTC driver... 17 8.1.1. Basic Use Case... 17 8.1.2. Setup Steps... 17 8.1.3. Usage Steps... 17 2

8.2. Reset Controller (RSTC) Example... 18 8.2.1. Purpose... 18 8.2.2. Requirements... 18 8.2.3. Description... 18 8.2.4. Main Files... 18 8.2.5. Compilation Information... 18 8.2.6. Usage... 18 Index... 21 Document Revision History... 22 3

Software License Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. The name of Atmel may not be used to endorse or promote products derived from this software without specific prior written permission. 4. This software may only be redistributed and used in connection with an Atmel microcontroller product. THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4

1. Prerequisites There are no prerequisites for this module. 5

2. Module Overview The Reset Controller contains an NRST Manager and a Reset State Manager. It runs at Slow Clock (SCLK) and generates the following: Processor and Watchdog Timer reset Embedded peripheral reset Co-processor and Co-processor peripheral reset (SAM4C devices only) External device reset (via the NRST pin) These reset signals are asserted by the Reset Controller acting on external events or as the result of an action performed by software. The Reset State Manager controls the operation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. 2.1 NRST Manager To control an external device reset the NRST Manager shapes the NRST assertion period using a programmable timer. While asserted, after power-up, NRST is an output and driven low. When the programmable time period has elapsed the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal. 2.1.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock (SCLK) speed and drives this pin low when required by the Reset State Manager. When the line is detected as being low a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed not to trigger a reset when NRST is asserted. The Reset controller can also be programmed to generate an interrupt instead of generating a reset. 2.1.2 NRST External Reset Control The NRST Manager can assert NRST for a programmable time period of between 60μs and 2s (approximately). This allows the Reset Controller to shape the NRST pin level and thus to guarantee that the NRST line is low for a time that is compliant with any external devices also connected to the system reset. 2.2 Reset State Manager The Reset State Manager handles the different reset sources and generates the internal reset signals. 2.2.1 General Reset A general reset occurs when either a Power-on-reset is detected or the Supply Controller detects a Brownout or Voltage regulation loss. 2.2.2 Backup Reset A Backup reset occurs when the chip returns from Backup Mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs. 2.2.3 User Reset If User Reset is enabled then the state is entered when a low level is detected on the NRST pin. When User Reset is entered both the Processor Reset and the Peripheral Reset are asserted. The User Reset state is left when NRST rises and the processor clock is re-enabled as soon as NRST is confirmed high. 2.2.4 Software Reset The Reset Controller allows software to assert the the following reset signals: Reset the processor and the Watchdog Timer 6

Reset all the embedded peripherals Reset the Co-processor (SAM4C devices only) Reset all the embedded peripherals associated with the Co-processor (SAM4C devices only) Assert NRST for a programmable time period Note The embedded peripheral reset also includes the memory system and the Remap Command and is generally used for debugging purposes. For SAM4C devices the Co-processor peripheral reset only affects the embedded peripherals associated with the Co-processor. The processor's peripherals are not reset. 2.2.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. 2.2.6 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: General Reset Backup Reset Watchdog Reset Software Reset User Reset Particular cases are listed below: When in User Reset: A watchdog event is impossible because the Watchdog Timer is being reset A software reset is impossible because the processor reset is being activated When in Software Reset: A watchdog event has priority over the current state The NRST has no effect When in Watchdog Reset: The processor reset is active and so a Software Reset cannot be programmed A User Reset cannot be entered 7

3. Special Considerations System designs using any external devices that require a software controllable reset signal assertion longer than two seconds should use a dedicated I/O output of the microcontroller. 8

4. Extra Information For extra information, see Extra Information for Reset Controller Driver. This includes: Acronyms Dependencies Errata Module History 9

5. Examples For a list of examples related to this driver, see Examples for Reset Controller Driver. 10

6. API Overview 6.1 Macro Definitions 6.1.1 Macro RSTC_BACKUP_RESET #define RSTC_BACKUP_RESET 6.1.2 Macro RSTC_CPMR_KEY_PASSWD #define RSTC_CPMR_KEY_PASSWD 6.1.3 Macro RSTC_GENERAL_RESET #define RSTC_GENERAL_RESET 6.1.4 Macro RSTC_NRST_HIGH #define RSTC_NRST_HIGH 6.1.5 Macro RSTC_NRST_LOW #define RSTC_NRST_LOW 6.1.6 Macro RSTC_SOFTWARE_RESET #define RSTC_SOFTWARE_RESET 6.1.7 Macro RSTC_USER_RESET #define RSTC_USER_RESET 6.1.8 Macro RSTC_WATCHDOG_RESET #define RSTC_WATCHDOG_RESET 11

6.2 Function Definitions 6.2.1 Function rstc_assert_reset_of_coprocessor() Assert the reset of the Co-processor. void rstc_assert_reset_of_coprocessor( Rstc * p_rstc, const uint32_t reset) Note This function is for SAM4C devices only. Table 6-1. Parameters Data direction Parameter name Description [in, out] p_rstc Module hardware register base address pointer [in] reset The reset to be asserted as a bitmask, which could be RSTC_CPMR_CPEREN (peripheral reset) and/or RSTC_CPMR_CPROCEN (core reset). 6.2.2 Function rstc_deassert_reset_of_coprocessor() Deassert the reset of the Co-processor. void rstc_deassert_reset_of_coprocessor( Rstc * p_rstc, const uint32_t reset) Note This function is for SAM4C devices only. Table 6-2. Parameters Data direction Parameter name Description [in, out] p_rstc Module hardware register base address pointer [in] reset The reset to be deasserted as a bitmask, which could be RSTC_CPMR_CPEREN (peripheral reset) and/or RSTC_CPMR_CPROCEN (core reset). 6.2.3 Function rstc_disable_user_reset() 12

Disable User Reset. void rstc_disable_user_reset( Rstc * p_rstc) Table 6-3. Parameters Data direction Parameter name Description [in, out] p_rstc Module hardware register base address pointer 6.2.4 Function rstc_disable_user_reset_interrupt() Disable the User Reset interrupt. void rstc_disable_user_reset_interrupt( Rstc * p_rstc) Table 6-4. Parameters Data direction Parameter name Description [in, out] p_rstc Module hardware register base address pointer 6.2.5 Function rstc_enable_user_reset() Enable User Reset. void rstc_enable_user_reset( Rstc * p_rstc) Table 6-5. Parameters Data direction Parameter name Description [in, out] p_rstc Module hardware register base address pointer 6.2.6 Function rstc_enable_user_reset_interrupt() Enable the User Reset interrupt. void rstc_enable_user_reset_interrupt( Rstc * p_rstc) Table 6-6. Parameters Data direction Parameter name Description [in, out] p_rstc Module hardware register base address pointer 13

6.2.7 Function rstc_get_reset_cause() Get the reset cause. uint32_t rstc_get_reset_cause( Rstc * p_rstc) Table 6-7. Parameters Data direction Parameter name Description [in] p_rstc Module hardware register base address pointer Returns The last reset cause. 6.2.8 Function rstc_get_status() Get the RSTC status. uint32_t rstc_get_status( Rstc * p_rstc) Table 6-8. Parameters Data direction Parameter name Description [in] p_rstc Module hardware register base address pointer Returns RSTC status. 6.2.9 Function rstc_reset_extern() Asserts the NRST pin for external resets. void rstc_reset_extern( Rstc * p_rstc) Table 6-9. Parameters Data direction Parameter name Description [out] p_rstc Module hardware register base address pointer 6.2.10 Function rstc_set_external_reset() Set the external reset length. void rstc_set_external_reset( 14

Rstc * p_rstc, const uint32_t ul_length) Table 6-10. Parameters Data direction Parameter name Description [in, out] p_rstc Module hardware register base address pointer [in] ul_length The length of external reset 6.2.11 Function rstc_start_software_reset() Perform a Software Reset. void rstc_start_software_reset( Rstc * p_rstc) Table 6-11. Parameters Data direction Parameter name Description [out] p_rstc Module hardware register base address pointer 15

7. Extra Information for Reset Controller Driver 7.1 Acronyms Below is a table listing the acronyms used in this module, along with their intended meanings. Acronym GND I/O NRST QSG SCLK Definition Ground Input Output Synchronous Microcontroller Reset Quick Start Guide Slow Clock 7.2 Dependencies This driver has the following dependencies: None 7.3 Errata There are no errata related to this driver. 7.4 Module History An overview of the module history is presented in the table below, with details on the enhancements and fixes made to the module since its first release. The current version of this corresponds to the newest version in the table. Changelog Initial document release 16

8. Examples for Reset Controller Driver This is a list of the available Quick Start Guides (QSGs) and example applications for SAM4 Reset Controller (RSTC). QSGs are simple examples with step-by-step instructions to configure and use this driver in a selection of use cases. Note that QSGs can be compiled as a standalone application or be added to the user application. Quick Start guide for SAM RSTC driver Reset Controller (RSTC) Example 8.1 Quick Start guide for SAM RSTC driver This is the quick start guide for the SAM Reset Controller (RSTC) driver, with step-by-step instructions on how to configure and use the driver in a selection of use cases. The use cases contain several code fragments. The code fragments in the steps for setup can be copied into a custom initialization function, while the steps for usage can be copied into, e.g., the main application function. 8.1.1 Basic Use Case In this basic use case, the User Reset interrupt is enabled and the main application notified about NRST signal assertion events. 8.1.1.1 Prerequisites System Clock Management Watchdog Timer 8.1.2 Setup Steps 8.1.2.1 Example Code Add the following to the application C-file: static volatile bool reset_interrupt_triggered = false; void RSTC_Handler(void) { /* Clear the interrupt. */ rstc_get_status(rstc); } reset_interrupt_triggered = true; 8.1.2.2 Workflow Enable the User Reset interrupt: rstc_disable_user_reset(rstc); NVIC_DisableIRQ(RSTC_IRQn); rstc_enable_user_reset_interrupt(rstc); NVIC_ClearPendingIRQ(RSTC_IRQn); NVIC_SetPriority(RSTC_IRQn, 0); NVIC_EnableIRQ(RSTC_IRQn); 8.1.3 Usage Steps 8.1.3.1 Workflow Add to, e.g., main loop in application C-file: 17

if (reset_interrupt_triggered) { /* Critical section to access a variable that is set in an IRQ. */ cpu_irq_enter_critical(); reset_interrupt_triggered = false; cpu_irq_leave_critical(); } puts("user Reset IRQ triggered. Press any console key for the menu\r"); 8.2 Reset Controller (RSTC) Example 8.2.1 Purpose This basic example shows how to use the Reset Controller (RSTC) peripheral available on SAM devices. The RSTC handles all the resets of the system, reports which reset occurred last and also drives independently or simultaneously the external reset and the peripheral and processor resets. 8.2.2 Requirements This example can be used with SAM evaluation kits Optional: An oscilloscope connected to the evaluation kit's NRST signal 8.2.3 Description Upon startup, the program displays the reset controller status and a menu to perform the following: * Menu: * 0 - Reset Status information. * 1 - User Reset enable. * 2 - User Reset disable. * 3 - User Reset interrupt enable. * 4 - User Reset interrupt disable. * 5 - Software Reset. * 6 - Watchdog Reset. * 7 - NRST assert. The menu can be used to initiate several types of reset and to enable/disable the User Reset interrupt. 8.2.4 Main Files rstc.c: Reset Controller driver rstc.h: Reset Controller driver header file rstc_example1.c: Reset Controller example application 8.2.5 Compilation Information 8.2.6 Usage This software is written for GNU GCC and IAR Embedded Workbench for Atmel. Other compilers may or may not work. 1. Build the program and download it into the evaluation board. 18

2. On the computer, open and configure a terminal application (e.g., HyperTerminal on Microsoft Windows ) with these settings: 115200 baud 8 bits of data No parity 1 stop bit No flow control 3. Start the application. 4. In the terminal window, the following text should appear: * -- RSTC Reset Controller Example -- * -- xxxxxx-xx * -- Compiled: xxx xx xxxx xx:xx:xx -- * * Reset info : General Reset, NRST=1, User Reset=0 * * Menu: * 0 - Reset Status information. * 1 - User Reset enable. * 2 - User Reset disable. * 3 - User Reset interrupt enable. * 4 - User Reset interrupt disable. * 5 - Software Reset. * 6 - Watchdog Reset. * 7 - NRST assert. 5. Press one of the keys listed in the menu to perform the corresponding action. Press '1': The following message is displayed: User Reset enabled - Press evaluation kit RESET button to test. If the evaluation kit's reset button is pressed the last reset source will be displayed and the menu shown again. Press '2': The following message is displayed: User Reset enabled - Press evaluation kit RESET button to test. If the evaluation kit's reset button is pressed it will have no effect on the system. Press '3': The following message is displayed: User Reset interrupt enabled.. If the evaluation kit's reset button is pressed the following message will be displayed. User Reset IRQ triggered. Press any console key for the menu Press '4': The following message is displayed: 19

User Reset interrupt disabled. If the evaluation kit's reset button is pressed it will have no effect on the system. Press '5': The following message is displayed: Software Reset activated. The evaluation kit will perform a software reset, the last reset source will be displayed and the menu shown again. Press '6': The following message is displayed: Watchdog Reset will trigger in 3 seconds. The evaluation kit will perform a watchdog reset, the last reset source will be displayed and the menu shown again. Press '7': The following message is displayed: NRST asserted. The evaluation kit will assert the NRST signal for 60μs. Note The "NRST assert" menu option requires an oscilloscope connected to the evaluation kit's NRST signal. To avoid a hardware conflict during the test do not use the evaluation kit's manual RESET button. 20

Index F Function Definitions rstc_assert_reset_of_coprocessor, 12 rstc_deassert_reset_of_coprocessor, 12 rstc_disable_user_reset, 12 rstc_disable_user_reset_interrupt, 13 rstc_enable_user_reset, 13 rstc_enable_user_reset_interrupt, 13 rstc_get_reset_cause, 14 rstc_get_status, 14 rstc_reset_extern, 14 rstc_set_external_reset, 14 rstc_start_software_reset, 15 M Macro Definitions RSTC_BACKUP_RESET, 11 RSTC_CPMR_KEY_PASSWD, 11 RSTC_GENERAL_RESET, 11 RSTC_NRST_HIGH, 11 RSTC_NRST_LOW, 11 RSTC_SOFTWARE_RESET, 11 RSTC_USER_RESET, 11 RSTC_WATCHDOG_RESET, 11 21

Document Revision History Doc. Rev. Date Comments 42279A 05/2014 Initial document release 22

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