SECOND шт. Assembly and С Programming forthefreescalehcs12 Microcontroller Fredrick M. Cady Department of Electrical and Computer Engineering Montana State University New York Oxford Oxford University Press 2008 EDITION
Preface xiü 3 Structured Program Design 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Some Basic Definitions Computers, Microprocessors, Microcomputers, Microcontrollers Motorola/Freescale Developments Leading to the HCS12 Embedded Systems Notation General Principles of Microcontrollers 2.1 2.2 A Typical Microcontroller The Program Memory The Central Processor Unit The I/O Interface The Address, Data, and Control Buses Timing 2.3 Software/Firmware Development 2.4 The Software Development Tool Set Absolute Assemblers Relocatable Assemblers Compilers The Linker Creating a Relocatable Program 2.5 Remaining Questions 2.6 2.7 2.8 3.1 The Need for Software Design 3.2 The Software Development Process 3.3 Тор-Down Design 4 5 6 6 7 7 7 8 11 13 17 18 18 21 22 23 23 24 25 25 26 26 27 27 Understand the Problem Completely Design in Levels Ensure Correctness at Each Level Postpone Details Successively Refine Your Design Design Without Using a Programming Language 3.4 Design Partitioning 3.5 Bottom-Up Design 3.6 The Real-World Approach 3.7 Types of Design Activity 3.8 Design Tools Structured Programming Pseudocode 3.9 3.10 3.11 3.12 3.13 3.14 Using Pseudocode Structured Elements as i Design Tool Top-Down Debugging and Testing Structured Programming in Assembly Language Software Documentation Software Requirements Specification (SRS) Software Design Document (SDD) Software Code Software Verification Plan (SVP) User Manuals A Top Down Design Example Seat Belt Alarm Problem Statement The Top Down Design 28 28 28 29 29 30 31 31 32 32 32 32 33 34 34 34 35 39 41 47 48 v
vi 4 to the HCS12 Hardware 50 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 50 The CPU, Registers, and Condition Code Bits 52 The Programmer's CPU Model 52 Control Registers 53 Operating Modes 54 Normal Single-Chip Mode 54 Normal Expanded Mode 55 Background Debug Mode 55 Memory Map 56 Addressing Modes 56 Inherent Addressing 56 Immediate Addressing 57 Direct and Extended Addressing 58 Indexed Addressing 59 Relative Addressing 63 Reset 64 Causes of Reset 65 Reset Summary 65 65 66 66 5 An Assembler Program 5.1 5.2 5.3 5.4 5.5 5.6 68 Assembly Language Example 68 CodeWarrior HC12 Assembler 70 Assembler Source Code Fields 70 Label Field 70 Opcode or Operation Field 71 Operand Field 71 Comment Field 77 Assembler Control 77 Assembler Directives 79 Section Definition 79 Constant Definition 82 Reserving or Allocating Memory Locations 83 Defining Constants in Memory 83 Export or Import Global Symbols 87 Assembly Control 88 Repetitive Assembly 90 Listing Control 91 Macros 93 Conditional Assembly 96 Assembler Files 100 Assembler Listing 100 Debug Listing 101 Object Files 101 Absolute Files 101 Freescale S Files 101 5.7 Remaining Questions 101 5.8 102 5.9 102 5.10 103 6 The Linker 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 Assumptions Code Development Why Use a Relocatable Assembler/ Compiler and a Linker? Memory Types, Sections, and Section Types Code Section Constant Data Section Variable Data Section Stack Section Linker Operation Locating in Proper Memory Linking the Code The Linker Parameter File Parameter File Commands The Linker Output Files The Linker Map File Absolute Files Remaining Questions 7 HCS12 Instruction Set 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 104 104 104 104 105 105 106 106 106 106 107 107 110 111 112 114 114 118 118 118 119 119 122 122 HCS12 Instruction Set 122 HCS12 Instruction and Operand Syntax 126 Addressing Modes 126 Instruction Categories 128 Move Data Instructions 128 Modify Data Instructions 130 Decision Making Instructions 133 Flow Control Instructions 134 Other Instructions 135 Load and Store Register Instructions 136 Eight-Bit Load and Store Instructions 136 Sixteen-Bit Load and Store Instructions 139 Stack Instructions 140 Load Effective Address Instructions 144 Transfer Register Instructions 145 Move Instructions 145 Decrement and Increment Instructions 148
vii 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 Clear and Set Instructions Shift and Rotate Instructions Arithmetic Instructions Add and Subtract Decimal Arithmetic Negating and Sign Extension Multiplication Fractional Number Arithmetic Division Logic Instructions Data Test Instructions Conditional Branch Instructions Signed and Unsigned Conditional Branches Bit Test Conditional Branching Loop Primitive Instructions Unconditional Jump and Branch Instructions Branches to Subroutines Condition Code Register Instructions Interrupt Instructions Fuzzy Logic Instructions Miscellaneous Instructions 151 153 155 I DO 155 157 159 160 162 164 166 167 168 169 170 170 170 171 173 173 173 173 174 174 8.7 8.8 9 Debugging HCS12 Programs 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Program Debugging Code Walkthroughs The Debugging Plan Debugging Tools Debugging Demonstration Program Debugging Program Flow and Logic Debugging Data Elements The Source Code Listing Typical Assembly Language Program Bugs Stack Register Condition Code Register Test Data Strategies Other Debugging Techniques 10 Program Development Using С 204 204 208 208 208 209 210 211 211 213 214 215 216 216 218 221 224 224 224 225 226 8 Assembly Language Programs for the HCS12 179 8.1 Assembly Language Programming Style 179 Source Code Style 179 To Indent or Not to Indent 186 Uppercase and Lowercase 186 Use Equates, Not Magic Numbers 186 Using Include Files 187 Commenting Style 188 8.2 Structured Assembly Language Programming 188 Sequence 189 IF-THEN-ELSE Decision 189 WHILE-DO Repetition 192 DO-WHILE Repetition 193 8.3 Interprocess Communication 195 Information in Registers 195 Information in Global Data Areas 196 Information in Local Data Areas 198 Information on the Stack 199 Using Addresses Instead of Values 202 Passing Boolean Information 202 8.4 Assembly Language Tricks of the Trade 202 8.5 Making It Look Pretty 203 8.6 204 10.1 226 10.2 Major Differences Between С for Embedded and С for Desktop Applications 226 ANSI С Versus Microcontroller Implementations 227 10.3 Architecture of а С Program 229 Startup Code 229 Void Main(Void); 230 Variables 230 10.4 Assembly Language Interface 231 Compiler Produced Assembly Language Code 231 Using Assembly Language in С 232 In-line Assembly 236 10.5 Bits and Bytes Accessing I/O Registers 239 Byte Addressing 239 Bit Addressing 241 Byte and Bit Addressing 2 CodeWarrior Bytes and Bits 244 Caution on Compiler Implementation Dependent Bit Addressing 244 10.6 Interrupts 245 The Interrupt Service Routine or Interrupt Handler 245 Locating the Interrupt Service Routine 246
viii 10.7 10.8 10.9 Remaining Questions 10.10 11 HCS12 Parallel I/O 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 Families of HCS12 Processors The Register Base Address The Port Integration Module (PIM) Bidirectional I/O Ports HCS12 Parallel I/O Ports Ports A and В Port AD Port E Port J PortM PortP Ports PortT Data Direction Registers I/O Port Bit Electronics Reduced Drive Control Pull-up or Pull-down Control Polarity Selection Wired-OR Input Registers Parallel I/O Programming Parallel I/O Software Checklist Parallel I/O Software Examples More Parallel I/O Programming and Interfacing Examples Remaining Questions Parallel I/O Register Address Summary 12 HCS12 Interrupts 12.1 12.2 12.3 General Interrupt System Specifications Asynchronous Events and Internal Processor Timing Enabling the Interrupts Pending Interrupts Multiple Sources of Interrupts HCS12 Interrupts The Interrupt Process The Interrupt Enable The Interrupt Disable 248 248 248 249 250 250 250 250 251 254 256 257 260 263 264 265 265 265 268 269 271 271 273 274 276 277 278 278 278 284 284 284 285 286 286 287 287 289 289 289 290 291 292 292 292 293 12.4 12.5 12.6 12.7 12.8 The Interrupt Request The Interrupt Sequence The Interrupt Return Interrupt Vectors HCS12 System Vectors Initializing the Interrupt Vectors Interrupt Priorities Hardware Prioritization Software Prioritization Nonmaskable Interrupts System Reset Clock Monitor Reset Computer Operating Properly (COP) Reset Unimplemented Instruction Opcode Trap Software Interrupt (SWI) Nonmaskable Interrupt Request XIRQ_L External Interrupt Sources IRQ J. PortP Port J Interrupt Flags Resetting Interrupt Flags Resetting Interrupt Flags in С Multiple Flags with a Single Interrupt Vector Internal Interrupt Sources 12.9 Advanced Interrupts Selecting Edge or Level Triggering What to Do While Waiting for an Interrupt Initializing Unused Interrupt Vectors Other Interrupt Registers 12.10 The Interrupt Service Routine 12.11 12.12 12.13 or interrupt Handier Interrupt Service Routine Hints Interprocess Communication An Interrupt Program Template Remaining Question Interrupt System Register Address Summary 12.14 conclusion ana unapter summary Komts 12.15 12.16 13 HCS12 Memories 13.1 13.2 13.3 13.4 Flash and EEPROM Remapping Memory Resources MC9S12C32 Memory Map Remapping Registers and Memory Locations Remapping RAM 293 294 294 295 295 296 300 300 301 302 302 303 304 308 308 308 309 309 310 316 318 318 319 323 324 326 326 326 330 331 331 332 332 333 335 335 335 335 336 337 337
ix 13.5 13.6 13.7 13.8 13.9 Remapping I/O Registers 338 Remapping EEPROM 339 Memory Priorities 341 Memory Expansion 341 Programming and the Program Page Window 3 Other Memory Mapping Registers 3 Remaining Question 346 Memory System Register Address Summary 346 346 13.10 347 13.11 347 14 HCS12Timer 348 14.1 348 14.2 Basic Timer 349 Prescaler 349 Sixteen-Bit Free-Running TCNT Register 350 Timer Overflow Flag 352 Basic Timer Overflow Programming 353 14.3 Timer Overflow Interrupts 357 14.4 Output Compare 364 Output Compare Time Delays 366 Output Compare Interrupts 371 Output Compare Bit Operation 377 One Output Compare Controlling Up to Eight Outputs 382 Very Short Duration Pulses 388 Forced Output Compares 390 Output Compare Software Checklist 391 14.5 Input Capture 391 Input Capture Software Checklist 396 14.6 Pulse Accumulator 396 Pulse Accumulator Interrupts 398 14.7 Plain and Fancy Timing 400 14.8 Clearing Timer Flags 400 Clearing Timer Flags in С 402 Fast Timer Flag Clearing 403 14.9 Real-Time Interrupt 403 14.10 Pulse-Width Modulator 411 Pulse-Width Modulator Clock Control 413 Pulse-Width Modulator Control Registers 415 Using Port T Outputs for PWM Waveforms 1 Choosing Pulse-Width Modulation Counter Prescaler and Scaler Values 2 Pulse-Width Modulation Software Checklist 7 14.11 Timer System Register Address Summary 1 14.12 Timer Features 3 14.13 3 14.14 14.15 15 HCS12 Serial I/O SCI and SPI 15.1 15.2 15.3 15.4 15.5 15.6 15.7 Asynchronous Serial Communications Interface (SCI) SCI Data SCI Initialization SCI Status Flags SCI Flag Clearing SCI Interrupts SCI Wake-up SCI Break Character Port S SCI I/O SCI Programming Examples SCI Interfacing Synchronous Serial Peripheral Interface (SPI) Interprocessor Serial Communications SPI Data Register SPI Initialization SPI Master and Slave Modes SPI Data Rate and Clock Formats SPI Status Register SPI Interrupts SPI Programming Examples SCI and SPI Register Address Summary 16 HCS12 Serial I/O MSCAN 16.1 16.2 16.3 16.4 4 4 7 7 8 9 440 446 447 447 448 448 448 449 456 456 456 457 458 460 462 464 464 466 466 466 467 467 469 469 Motorola Scalable Controller Area Network Interface (MSCAN) 469 CAN Definitions 469 CAN Serial Communications 470 MSCAN Initialization and Control Registers 476 Initialization Mode 476 CAN Bus Timing 480 MSCAN Identifiers 484 Programmer's Model of Message Storage 491 MSCAN Initialization 496 MSCAN Data Transmitter 499 CAN Transmitter Buffers 499 Transmission Aborts 502
x Remote Transmission Request and Substitute Remote Request 503 MSCAN Transmitting 503 16.5 MSCAN Data Receiver 505 MSCAN Receiving 506 16.6 MSCAN Interrupts 508 MSCAN Sleep Mode and Wake-up 508 16.7 MSCAN Errors 512 Error Detection 512 Error Signaling 512 MSCAN Error Indicators 513 16.8 MSCAN Programming Examples 514 Explanation of Example 16-13 518 Explanation of Example 16-14 523 16.9 MSCAN Register Address Summary 524 16.10 524 16.11 525 16.12 525 17 HCS12 Analog Input 526 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13 526 HCS12 A/D Converter 526 A/D Power Up 528 A/D Conversion Sequence ATDCTL3 530 A/D Resolution, Sampling Time, and Clock Selection ATDCTL4 532 A/D Input Multiplexer and Input Scanning ATDCTL5 536 A/D Operation 537 Digital Results from the A/D 540 A/D Input Synchronization 5 Polling A/D Conversion Complete 5 Clearing Status Flags 545 A/D Interrupts 545 A/D Low Power Modes 546 Digital Input to the A/D 546 Miscellaneous A/D Registers 548 A/D Programming Summary 549 Example ATD Programs 549 Remaining Questions 554 554 554 555 18 Single-Chip Microcontroller Interfacing Techniques 556 18.1 The Single-Chip Microcontroller 18.2 Simple Input Devices Input Switches Arrays of Switches 556 556 556 560 18.3 18.4 18.5 18.6 18.7 18.8 18.9 Simple Display Devices Parallel I/O Expansion Parallel I/O Electronics Serial I/O Devices Serial Communications Interface Serial Peripheral Interface The Analog-to-Digital Converter Interface I/O Software Real-Time Synchronization Polled I/O Handshaking I/O 18.10 573 578 587 589 589 592 604 606 606 607 609 612 613 613 19 HCS12 Fuzzy Logic 615 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.14 615 Our Digital Heritage 616 How Is Fuzzy Logic Different? 617 What Is Fuzzy About Fuzzy Logic? 618 Structure of a Fuzzy Logic Inference Program 619 Fuzzification 621 Rule Evaluation 624 Defuzzification 628 Putting It All Together 630 The Complete Fuzzy Inference System 632 Fuzzy Logic 640 Fuzzy Logic Instructions 640 Minimum and Maximum Instructions 6 Table Lookup Instructions 6 644 645 645 20 Debugging Systems 646 20.1 20.2 20.3 20.4 20.5 646 Software and Hardware Breakpoints 647 Development Related Features of the MC9S12C32 649 Background Debug Module (BDM) 650 Single-Wire Physical Interface 651 Special Mode Select Function 651 Tagging Function 651 Background Communication Function 652 Application Uses for BDM 652 Nonvolatile Memory Programming 652
xi Target System Calibration 652 Field Diagnostics and Code Changes 653 Data Logging Applications 653 20.6 On-Chip Real-Time ICE System 653 Real-Time Bus Capture Versus Breakpoints and Single-Instruction Trace 654 Traditional External ICE 654 Benefits of On-Chip ICE 655 Features of HCS12 On-Chip ICE 656 On-Chip ICE Concepts 657 CodeWarrior User Interface to the On-Chip ICE System 660 A Simple Trace Example 661 A Practical Example of a Trace Run 665 20.7 670 20.8 671 21.6 Designing a System Using an MC9S12C Family Microcontroller 689 21.7 Clock Generator System Register Address Summary 690 21.8 690 Appendix A: Binary Codes Appendix B: HCS12 Instruction Set Appendix C: CodeWarrior Assembler 691 705 708 21 Advanced HCS12 Hardware 672 21.1 21.2 21.3 21.4 21.5 Clocks and Reset Generator System Clock Generator System Clocks Clock Generator Control Registers External Oscillator Phase Locked Loop Oscillator PLL External Connections PLL Programming HCS12 Operating Modes Clock Generator Modes Modes at Reset Wait and Stop Modes 672 673 674 676 680 681 681 682 686 686 687 688 Appendix D: HCS12 I/O Registers Appendix E: Include File Listings Appendix F: HCS12 Interrupt Vector Assignments 710 716 740 Index 7