ECE 3055: Final Exam Instructions: You have 2 hours and 50 minutes to complete this quiz. The quiz is closed book and closed notes, except for one 8.5 x 11 sheet. No calculators are allowed. Multiple Choice Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 TOTAL
Part I Multiple Choice 1) 2 points Which of the following statements is not true? a) In a pipelined design, the critical path delay is the delay through all pipeline stages b) There can be more than one critical path in a system c) The critical path delay is the maximum register-to-register delay in the system d) The critical path delay determines the maximum clock frequency of the system e) None of the above 2) 2 points For which of the following dependences can a pair of instructions never be re-ordered in a pipelined system? a) RAW b) WAR c) WAW d) Both a and c e) Both b and c 3) 2 points Which of the following statements is not true? a) With all other factors being equal, a virtual cache has a larger tag than a physical cache b) If there is a hit in a virtual cache, no address translation is necessary c) There is no reason to have a TLB in a system with a virtual cache d) Virtual caches can have a problem when the system allows different processes to share memory pages e) None of the above A
4) 2 points Which of the following statements is not true? a) A binary semaphore is equivalent to a lock b) A semaphore implementation must use busy waiting c) A counting semaphore is initialized to an integer value k > 1 d) When a semaphore is probed, the testing and decrementing operations must be done atomically e) None of the above 5) 2 points Which of the following statements is not true? a) During a context switch, the OS saves the internal processor state to disk b) Fast context switching is extremely important to reduce the overhead of multitasking c) Context switches are triggered periodically by timer interrupts d) Some processors use very large register files to store the states of multiple processes simultaneously in order to reduce average context switch time e) None of the above
Part II Problems 1) 15 points Consider the pipelined MIPS processor of Patterson and Hennessy, Chapter 6, with the following characteristics: 2-cycle branch penalty with no branch prediction all data hazards except for the lw hazard handled by forwarding no instruction re-ordering by the compiler 20-cycle miss penalty for both instruction and data caches instruction cache misses and data cache misses can not be handled concurrently Assume this processor executes a sequence of 1000 instructions with the following characteristics: 100 branches 150 loads, out of which 50 cause lw hazards 150 stores 15 data cache misses and 10 instruction cache misses a) Calculate how many cycles are required by the processor to execute fully the 1000 instructions. Show your work. b) Calculate the speedup achieved by the pipelined processor on the 1000 instructions compared to a multi-cycle processor that requires 3 cycles for a branch, 5 cycles for lw, and 4 cycles for all other instructions. Assume the same cache behavior described above and show your work.
2) 15 points Consider a direct-mapped write-back cache with 2 words per block and 16 words total. Assume the cache is initially empty. For the following sequence of hexadecimal word addresses, indicate whether each reference is a hit or a miss and show the final contents of the cache. The subscript on each address indicates whether the reference is a read or a write, R = read and W = write. Show your work. A4 R, 9D W, 3A R, B7 R, C1 W, 6B W, 74 W, 2E R, 1F R, 80 W
3) 15 points Consider a system with 32-bit virtual byte addresses, 16-bit physical byte addresses, and a page size of 4 KB. Assume that an entry in a non-inverted page table requires 4 bytes and an entry in an inverted page table requires 10 bytes. Show your work. a) What is the size of the root page table in a 2-level paging scheme for this system? b) What is the size of an inverted page table for this system?
4) 15 points Consider a 16 KB page of data being transferred from a hard disk to memory using DMA. Show your work. a) If the hard disk has the following parameters, how much time is required to read the data from the disk? You need only be concerned with the disk-related part of the transfer time. rotational speed is 100 rotations per second average seek time is 8 milliseconds disk controller overhead is 2 milliseconds disk transfer rate is 8 MB/second b) For a synchronous bus and memory with the following characteristics, how much memory and bus time will be required for the transfer? You need only be concerned with the time taken by the memory and the bus, i.e. you can assume that the disk supplies data as fast the memory and bus can process it. You can further assume that no other device uses the bus during the transfer time. 32-bit wide data bus bus clock rate of 100 MHz 4-word block transfer capability on bus (32-bit word size) bus arbitration takes 1 bus cycle memory access to first word in a block takes 30 ns, access to each subsequent word in the same block takes 20 ns the bus has separate address and data lines
5) 15 points Consider the following set of processes, their arrival times, their priorities, and the CPU times they require. Process Arrival Time Priority CPU Time P0 0 ms 3 4 ms P1 2 ms 1 3 ms P2 3 ms 5 8 ms P3 6 ms 6 6 ms P4 7 ms 2 8 ms P5 14 ms 4 2 ms Show the schedule generated by a preemptive priority scheduling algorithm and calculate the average waiting time for this schedule. Assume a larger priority value indicates a higher priority. Show your work.
6) 15 points Consider the Banker s Algorithm applied to the dining philosophers problem with five processes. Assume that the processes make the following sequence of resource requests: P0 requests left chopstick P1 requests left chopstick P2 requests left chopstick P3 requests left chopstick P4 requests left chopstick P0 requests right chopstick P1 requests right chopstick P2 requests right chopstick P3 requests right chopstick P4 requests right chopstick State which requests are granted and which are denied by the Banker s Algorithm. Justify your answer.