Silesian University of Technology as Centre of Modern Education Based on Research and Innovations POWR.03.05.00-IP.08-00-PZ1/17 Project co-financed by the European Union under the European Social Fund Course title: Digital Circuits Theory (DCT) Faculty of Automatic Control, Electronics and Computer Science, Institute of Informatics Field of study: Informatics Stationary first degree studies
Functions for auxiliary input combinational circuit Comparison of functions depending on the variables selected as root (base) Functions for input combinational circuit when the variables driving MUX are Functions for input combinational circuit when the variables driving MUX are 45
Functions for auxiliary input combinational circuit Matrix method allows to obtain functions for inputs addressed by any selected variables (selection does not have to be optimal) Selection of variables regardless of numbers of don t care conditions 46
Functions for auxiliary input combinational circuit Matrix method expansion of rows with don t care conditions For all don t care conditions on selected variables we repeat the row in the matrix, substituting don t cares with all possible combinations of values of variables 47
Functions for auxiliary input combinational circuit Matrix method ordering and reduction of rows leading to don t care conditions Ordering and grouping Covering Reduction of rows 48
Functions for auxiliary input combinational circuit Matrix method resulting functions The same as previously obtained by algebraic transformations 49
Properties of commutators Commutators and hazards Definitions and structures by canonical forms MUX DDMUX All minterms (or maxterms) implemented independently Consequences for all transitions between logically adjacent states there are static hazards 50
Implementations with Demultiplexers Multi-output functions enabled by added gates Example: Translator from Gray code into natural binary code on 4 bits Logic diagram Definitions of functions corresponding to this implementation Z 3 =x 3 Z 2 =Σ(4,5,6,7,8,9,10,11)x 3 x 2 x 1 x 0 Z 1 =Σ(2,3,4,5,8,9,14,15)x 3 x 2 x 1 x 0 Z 0 =Σ(1,2,4,7,8,11,13,14)x 3 x 2 x 1 x 0 51
Implementations with Demultiplexers Choice of the implemented form of a function For balanced functions can be dictated by available gates For imbalanced functions this form is chosen that requires smaller gate (with fewer inputs) Example Function to implement yz x 00 01 11 10 0 0 0 1 0 Fewer zeros than ones, so PoS form is selected over SoP form Logic diagram Definition corresponding to this implementation F=Π(0,3,7)xyz 52
Implementations with Demultiplexers Implementation of incompletely specified functions Once the circuit is constructed, it is not possible to recognise combinations for which the output is specified from those unspecified Example Function to implement yz x 00 01 11 10 0 1 1 1-1 Logic diagram Fewer ones than zeros, so SoP form is selected over PoS form Definition of the function corresponding to this implementation F=Σ(0,3,6)xyz 53
Implementations with Multiplexers Each MUX can implemented only one function Example: Translator from Gray code into natural binary code on 4 bits Logic diagram Definitions of functions corresponding to this implementation Z 3 =x 3 Z 2 =Σ(1,2)Z 3 x 2 Z 1 =Σ(1,2)Z 2 x 1 Z 0 =Σ(1,2)Z 1 x 0 54
Implementations with Multiplexers Implementation of incompletely specified functions Information inputs corresponding to combinations for which the output is unspecified can be left unconnected (then the answer depends on implementation technology) Example Function to implement yz x 00 01 11 10 0 1 1 1-1 Logic diagram Definition of the function corresponding to this implementation F=Σ(0,3,6(5))xyz 55
Specific implementations Example yz wx 00 01 11 10 00 1 01 1 11 1 Function to implement is of 4 variables, so in regular implementation would require 16-bit commutators, and then the definition would be given as F=Σ(1,4,8,13)wxyz 10 1 On the other hand, we can decompose the function = ++ + + + + ++ = =,, =,, =+(,,) G=Σ(1,2,4,7)wxz 56
Specific implementations Example (cont.) Decomposed function =+(,,) G=Σ(1,2,4,7)wxz Logic diagrams With addition of gates, 8-bit commutators are sufficient for implementation of the function 57
LECTURE10 58
Iterative circuits Problems to be solved by building structures that consist of repetitively, iterativelyused blocks In the structure there can be distinguished some number of identical sub-circuits, cells The number of inputs (cells) is either unspecified, or likely to change Design of an iterative or cascade circuit Cascade can work in one direction or in both 59
General structure of a single direction iterative circuit 60
A typical cell of an iterative circuit The specific number of variables used to carry messages between cells depends on the number of these messages A typical cell that is designed, works as a general template, adapted to requirements of each cell in a cascade. Boundary cells are often degenerate. 61
Standard design procedure 1. Identify inputs and outputs of a typical cell 2. Define clearly messages to be passed between cells (by carry) 3. Define symbolic maps for outputs from the typical cell 4. Encode listed messages with sufficient number of binary variables 5. Obtain binary maps for outputs from the typical cell 6. Set boundary conditions in their symbolic and binary forms 7. Obtain appropriate implementation-dependent forms for switching functions describing the typical cell 8. Implement the typical cell (or boundary cells, or the complete circuit) 62
Example Design a circuit which on the output Y sets 1 when on its four inputs there is a single 1 or two 1 s Standard processing for a combinational circuit 1. Construct a truth table since a circuit is relatively simple we can directly construct Karnaugh map 63
Example 2. Find such form of description that corresponds to intended implementation for implementation with gates we need minimal either SoP or PoS form If we need to change the number of inputs to the circuits, we start designing all over again! 64
Approach of iterative circuits Re-formulate circuit description Design a circuit which on the output Y i sets 1 when on inputs from 0 to i there is a single 1 or two 1 s Start designing an iterative circuit 1. A typical cell For this specific circuit, if constructed in the complete structure, there is needed only one output, from the last cell 65
Approach of iterative circuits 2. Definition of messages passed with carry on inputs there are no 1 s on inputs there is one 1 on inputs there are two 1 s on inputs there are more than two 1 s The number of messages is problem-dependent. We need as many as are necessary and sufficient to pass on relevant information. They need to exhaust all logically possible situations, and always only one choice of message is possible basing on current circuit knowledge. Messages are based on knowledge about preceding cells, and references to inputs of i-th cell would be wrong. 66
Approach of iterative circuits 3. Symbolic maps for output and carry 4. Encoding of symbolic messages Can be natural binary, by Gray code, or more optimisation-oriented. In this example, natural binary encoding is applied. 67
Approach of iterative circuits 5. Binary Karnaugh maps for output and carry 6. Boundary conditions 68
Approach of iterative circuits 7. Expressions for output and carry The form of obtained equations reminds recursive procedures or functions in programming. Without boundary conditions (or with wrong conditions) the whole circuit cannot work correctly. 69
Approach of iterative circuits 8. Implementation For Cell 0 we have: Inputs: Outputs: For Cell 1 we have: Inputs: Outputs: For Cell 2 we have: Inputs: Outputs: For Cell 3 we have: Inputs: Outputs: If we perform calculations for all cells, substituting correct inputs, transforming accordingly with laws of Boolean algebra, as a result the final formula for the output from the circuit corresponds to the one obtained before, for the circuit designed as a regular combinational circuit 70