Section 13. Timer0 HIGHLIGHTS. Timer0. This section of the manual contains the following major topics:

Section 13. Timer0 HIGHLIGHTS This section of the manual contains the following major topics: 13.1 Introduction... 13-2 13.2 Control Register... 13-3 13.3 Operation... 13-4 13.4 Timer0 Interrupt... 13-5 13.5 Using Timer0 with an External Clock... 13-6 13.6 Timer0 Prescaler... 13-7 13.7 Initialization... 13-9 13. Design Tips... 13-10 13.9 Related Application Notes... 13-11 13.10 Revision History... 13-12 13 Timer0 2000 Microchip Technology Inc. DS39513A-page 13-1

PIC1C Reference Manual 13.1 Introduction Figure 13-1: The Timer0 module has the following features: Software selectable as an -bit or 16-bit timer/counter Readable and writable Dedicated -bit software programmable prescaler Clock source selectable to be external or internal Interrupt on overflow from FFh to 00h (FFFFh to 0000h in 16-bit mode) Edge select for external clock Figure 13-1 shows a simplified block diagram of the Timer0 module in -bit mode and Figure 13-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. Timer0 Block Diagram in -bit Mode T0CKI pin T0SE FOSC/4 0 1 T0CS Programmable Prescaler 3 T0PS2:T0PS0 POUT 0 1 PSA Sync with Internal clocks (2 TCY delay) PSOUT Data Bus TMR0 Set interrupt flag bit T0IF on overflow Note 1: T0CS, T0SE, PSA, T0PS2:T0PS0 (T0CON<5:0>). 2: Upon reset, Timer0 is enabled in -bit mode, with clock input from T0CKI, max. prescale. Figure 13-2: Timer0 Block Diagram in 16-bit Mode T0CKI pin T0SE FOSC/4 0 1 T0CS Programmable Prescaler 3 T0PS2:T0PS0 POUT 0 1 PSA Sync with Internal clocks (2 TCY delay) PSOUT TMR0L TMR0 High Byte TMR0H Set interrupt flag bit T0IF on overflow L Write TMR0L Data Bus<7:0> Note 1: T0CS, T0SE, PSA, T0PS2:T0PS0 (T0CON<5:0>). 2: Upon reset, Timer0 is enabled in -bit mode, with clock input from T0CKI, max. prescale. DS39513A-page 13-2 2000 Microchip Technology Inc.

Section 13. Timer0 13.2 Control Register The T0CON register is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. Register 13-1: T0CON: TImer0 Control Register R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T0BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 =StopsTimer0 T0BIT: Timer0 -bit/16-bit Control bit 1 = Timer0 is configured as an -bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin is clock (counter mode) 0 = Internal instruction cycle is clock (timer mode) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = Timer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits These bits are ignored if PSA = 1 111 = 1:256 prescale value 110 = 1:12 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1: prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value 13 Timer0 Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset 1 = bit is set 0 = bit is cleared x = bit is unknown 2000 Microchip Technology Inc. DS39513A-page 13-3

PIC1C Reference Manual 13.3 Operation 13.3.1 -Bit/16-Bit Modes 13.3.1.1 16-Bit Mode Timer Reads 13.3.1.2 16-Bit Mode Timer Write 13.3.1.3 16-Bit Read/Modify Write When initializing Timer0, several options need to be specified. This is done by programming the appropriate bits in the T0CON register. Timer0 can be configured as an -bit or a 16-bit counter. The default state for Timer0 is an -bit counter. To configure the timer as a 16-bit counter, the T0BIT bit (T0CON register) must be cleared. If the timer is configured as an -bit timer, the MSB of TMR0 (TMR0H) is held clear and will read 00h. Normally once the mode of the timer is selected, it is not changed. Some applications may require the ability to switch back and forth between -bit and 16-bit modes. The two cases are: 1. Changing from -bit to 16-bit mode 2. Changing from 16-bit to -bit mode The condition when bit 7 of the Timer0 rolls over must be addressed. If Timer0 is configured as an -bit timer and is changed to a 16-bit timer on the same cycle as a rollover occurs, no interrupt is generated. If Timer0 is configured as a 16-bit timer and is changed to an -bit timer on the same cycle as a rollover occurs, the TMR0IF bit will be set. TMR0H is not the high byte of the timer/counter, but actually a buffered version of the high byte of Timer0. The high byte of the Timer0 counter/timer is not directly readable or writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides a user with the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. The user simply reads the low byte of Timer0, followed by a read of TMR0H, which contains the value in the high byte of Timer0 at the time that the low byte was read. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows a user to update all 16 bits to both the high and low bytes of Timer0 at once (see Figure 13-2). When performing a write of TMR0, the carry is held off during the write of the TMR0L register. Writes to the TMR0H register only modify the holding latch, not the timer (TMR0<15:>). Steps to write to the TMR0: 1. Load the TMR0H register. 2. Write to the TMR0L register. Read-modify-write instructions like BSF or BCF, read the contents of a register, make the appropriate changes, and place the result back into the register. The read cycle of a read-modify-write instruction of TMR0L will not update the contents of the TMR0H buffer. The TMR0H buffer will remain unchanged. When the write cycle (to TMR0L) of the instruction takes place, the contents of TMR0H are placed into the high byte of Timer0. DS39513A-page 13-4 2000 Microchip Technology Inc.

Section 13. Timer0 13.3.2 Timer/Counter Modes 13.4 Timer0 Interrupt Figure 13-3: Timer mode is selected by clearing the T0CS bit (T0CON register). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (T0CON register). In counter mode, Timer0 will increment either on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (T0CON register). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 13.5.1. The TMR0 interrupt flag bit is set when the TMR0 register overflows. When TMR0 is in -bit mode, this means the overflow from FFh to 00h. When TMR0 is in 16-bit mode, this means the overflow from FFFFh to 0000h. This overflow sets the TMR0IF bit (INTCON register). The interrupt can be disabled by clearing the TMR0IE bit (INTCON register). The TMR0IF bit must be cleared in software by the interrupt service routine. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut off during SLEEP. See Figure 13-3 for Timer0 interrupt timing. TMR0 Interrupt Timing OSC1 CLKO (3) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 13 -bit Timer0 TMR0IF bit (INTCON<2>) FEh 1 1 FFh 00h 01h 02h 16-bit Timer0 FFFEh FFFFh 0000h 0001h 0002h 1 Timer0 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC + 2 PC + 4 PC + 4 000h Instruction fetched Inst (PC) Inst (PC+2) Inst (PC+4) Inst (000h) Instruction executed Inst (PC-2) Inst (PC) Inst (PC+2) Dummy cycle Dummy cycle Note 1: Interrupt flag bit TMR0IF is sampled here (every Q1). 2: Interrupt latency = 4TCY where TCY = instruction cycle time. 3: CLKO is available only in RC oscillator mode. 2000 Microchip Technology Inc. DS39513A-page 13-5

PIC1C Reference Manual 13.5 Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements as detailed in 13.5.1 External Clock Synchronization. The requirements ensure the external clock can be synchronized with the internal phase clock (TSCLK). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 13.5.1 External Clock Synchronization 13.5.2 TMR0 Increment Delay When no prescaler is used, the external clock input is used instead of the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 13-4). Therefore, it is necessary for T0CKI to be high for at least 2TSCLK (and a small RC delay) and low for at least 2TSCLK (and a small RC delay). Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TSCLK (and a small RC delay) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 13-4 shows the delay from the external clock edge to the timer incrementing. Figure 13-4: Timer0 Timing with External Clock External Clock Input or Prescaler output (2) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling (3) (1) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. DS39513A-page 13-6 2000 Microchip Technology Inc.

Section 13. Timer0 13.6 Timer0 Prescaler Figure 13-5: An -bit counter is available as a prescaler for the Timer0 module (Figure 13-5). The PSA and T0PS2:T0PS0 bits (T0CON register) are the prescaler enable and prescale select bits. All instructions that write to the Timer0 (TMR0) register (such as: CLRF TMR0; BSF TMR0,x; MOVWF TMR0;...etc.) will clear the prescaler if enabled. The prescaler is not readable or writable. Writes to TMR0H do not clear the Timer0 prescaler in 16-bit mode, because a write to TMR0H only modifies the Timer0 latch and does not change the contents of Timer0. The prescaler is only cleared on writes to TMR0L. Block Diagram of the Timer0 Prescaler CLKO (=FOSC/4) Data Bus T0CKI pin T0SE T0PS2:T0PS0 0 M 0 U X 1 1 T0CS -bit Prescaler -to-1mux M U X PSA Synchronization 2TCY delay T0BIT TMR0L T0BIT TMR0 high reg TMR0H Data Bus Set flag bit TMR0IF on overflow for TMR0L Set flag bit TMR0IF on overflow 13 Note: T0CS,T0SE,PSA,T0PS2:T0PS0arelocatedintheT0CONregister. The prescaler for Timer0 is enabled or disabled in software by the PSA bit (T0CON register). Setting the PSA bit will enable the prescaler. The prescaler can be modified under software control through the T0PS2:T0PS0 bits. This allows the prescaler reload value to be readable and writable. The prescaler count value (the contents of the prescaler) can not be read or written. When the prescaler is enabled, prescale values of 1:2, 1:4,..., 1:256 are selectable. Timer0 2000 Microchip Technology Inc. DS39513A-page 13-7

PIC1C Reference Manual Any write to the TMR0 register will cause a 2 instruction cycle (2TCY) inhibit. That is, after the TMR0 register has been written with the new value, TMR0 will not be incremented until the third instruction cycle later (Figure 13-6). When the prescaler is assigned to the Timer0 module, any write to the TMR0 register will immediately update the TMR0 register and clear the prescaler. The incrementing of Timer0 (TMR0 and Prescaler) will also be inhibited 2 instruction cycles (TCY). So if the prescaler is configured as 2, then after a write to the TMR0 register, TMR0 will not increment for 4 Timer0 clocks (Figure 13-7). After that, TMR0 will increment every prescaler number of clocks later. Figure 13-6: Timer0 Timing: Internal Clock/No Prescale PC (Program Counter) Instruction Fetch Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-2 PC PC+2 PC+4 PC+6 PC+ PC+10 PC+12 MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0 Instruction Executed Write TMR0 executed + 1 + 2 Figure 13-7: Timer0 Timing: Internal Clock/Prescale 1:2 PC (Program Counter) Instruction Fetch Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-2 PC PC+2 PC+4 PC+6 PC+ PC+10 PC+12 MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W TMR0 T0 T0+1 NT0 NT0+1 PC+6 Instruction Execute Write TMR0 executed + 1 Table 13-1: Registers Associated with Timer0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets TMR0L Timer0 Module s Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module s High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u T0CON TMR0ON T0BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA PORTA Data Direction Register --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. DS39513A-page 13-2000 Microchip Technology Inc.

Section 13. Timer0 13.7 Initialization Since Timer0 has a software programmable clock source, there are two examples to show the initialization of Timer0 with each source. Example 13-1 shows the initialization for the internal clock source (timer mode), while Example 13-2 shows the initialization for the external clock source (counter mode). Example 13-1: Timer0 Initialization (Internal Clock Source) CLRF TMR0 ; Clear Timer0 register CLRF INTCON ; Disable interrupts and clear T0IF BCF INTCON2, RBPU ; MOVLW 0x0 ; PortB pull-ups are disabled, MOVWF T0CON ; Interrupt on rising edge of RB0, ; TMR0 = 16-Bit Time ; Timer0 increment from internal clock ; with a prescaler of 1:2. ;** BSF INTCON, T0IE ; Enable TMR0 interrupt ;** BSF INTCON, GIE ; Enable all interrupts ; ; The TMR0 interrupt is disabled, do polling on the overflow bit ; T0_OVFL_WAIT BTFSS INTCON, T0IF GOTO T0_OVFL_WAIT ; Timer has overflowed Example 13-2: Timer0 Initialization (External Clock Source) 13 CLRF TMR0 ; Clear Timer0 register CLRF INTCON ; Disable interrupts and clear T0IF BCF INTCON2, RBPU ; MOVLW 0xBF ; PortB pull-ups are enabled, MOVWF T0CON ; Interrupt on falling edge of RB0 ; Timer0 increment from external clock ; on the high-to-low transition ; of T0CKI ; with a prescaler of 1:256. ;** BSF INTCON, T0IE ; Enable TMR0 interrupt ;** BSF INTCON, GIE ; Enable all interrupts ; ; The TMR0 interrupt is disabled, do polling on the overflow bit ; T0_OVFL_WAIT BTFSS INTCON, T0IF GOTO T0_OVFL_WAIT ; Timer has overflowed Timer0 2000 Microchip Technology Inc. DS39513A-page 13-9

PIC1C Reference Manual 13. Design Tips Question 1: I am implementing a counter/clock, but the clock loses time or is inaccurate. Answer 1: If you are polling TMR0 to see if it has rolled over to zero, you could do this by executing: wait MOVF TMR0,W ; read the timer into W BTFSS STATUS,Z ; see if it was zero, if so, ; break from loop GOTO wait ; if not zero yet, keep waiting Two possible scenarios to lose clock cycles are: 1. If you are incrementing TMR0 from the internal instruction clock (or an external source that is about as fast), the overflow could occur during the two cycle GOTO, soyoucouldmiss it. In this case, the TMR0 source should be prescaled. 2. When writing to TMR0, two instruction clock cycles are lost. Often you have a specific time period you want to count, say 100 decimal. In that case, you might put 156 into TMR0 (256-100 = 156). However, since two instruction cycles are lost when you write to TMR0 (for internal logic synchronization), you should actually write 15 to the timer. DS39513A-page 13-10 2000 Microchip Technology Inc.

Section 13. Timer0 13.9 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Enhanced family (that is, they may be written for the Base-Line, the Mid-Range or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to Timer0 are: Title Application Note # Frequency Counter Using PIC16C5X AN592 A Clock Design using the PIC16C54 for LED Display and Switch Inputs AN590 Note: Please visit the Microchip Web site for additional software code examples. These code examples are stand alone examples to assist in the understanding of the PIC1CXXX. The web address for these examples is: http://www.microchip.com/10/faqs/codeex/ 13 Timer0 2000 Microchip Technology Inc. DS39513A-page 13-11

PIC1C Reference Manual 13.10 Revision History Revision A This is the initial released revision of the Enhanced MCU Timer0 Module description. DS39513A-page 13-12 2000 Microchip Technology Inc.