CSE 260 Digital Computers: Organization and Logical Design Jon Turner Problem Set 1 Solutions 1. Give a brief definition of each of the following parts of a computer system: CPU, main memory, floating point unit, memory management unit, cache, memory bus, peripheral bus interface. The CPU (Central Processing Unit) is part of a computer system that retrieves the instructions that make up the software running on the computer from memory, and executes them (sometimes with the assistance of other parts of the processor). The main memory provides storage for programs and data while the computer system is turned on and active. This memory is usually volatile, meaning that when power is turned off, the information stored in the memory is lost. The floating point unit (FPU) is the part of the processor that is responsible for executing arithmetic instructions on floating point operands (as opposed to integer operands). A cache is a small memory located close to the CPU and used to store instructions and/or data that have been used recently. The copies of data items in the cache are used by the CPU whenever possible, instead of retrieving the originals from main memory, in order to save time. The memory bus is a set of wires connecting the processor to the main memory. It is typically implemented as traces on a printed circuit board. The peripheral bus interface separates the memory bus from the peripheral bus. There are two main reasons to separate these two. First, if there are too many different components on the memory bus, it becomes difficult to sustain high performance. Second, because peripheral components are produced by a variety of companies and have longer product life cycles than processors do, the peripheral bus must be standardized and must be stable over a number of years, while the memory bus design changes more often to track improvements in processor performance. 2. What is the role of a cache in a computer system? Why is it important? Caches in computer systems store recently used instructions and data, with the expectation that because they were used recently, they are likely to be used again in the near future. By retrieving needed instructions and data from the cache, the processor can avoid accessing main memory. This is important because it can take over 100 processor instruction cycles, just to retrieve a single word from memory. During the time that the processor must wait for a value to be returned from memory, it cannot do any useful work. Consequently, caches are critical to sustaining high performance. - 1 -
3. Convert the following binary numbers to decimal: (a) 1100110, (b) 11010111.1101, and (c) 111001001. What are the hexadecimal equivalents of these binary numbers? 110 0110 is 64+32+4+2=102 in decimal and x66 in hex. The integer part of 1101 0111.1101 is 128+64+16+8+4+1=221 in decimal and xd7 in hex. The fractional part is ½+1/4+1/16=.8125 in decimal and x.d in hex. Combining these gives 221.8125 in decimal and xd7.d in hex. 1 1100 1001 is 256+128+64+8+1=457 in decimal and x1c9 in hex. 4. Convert the following decimal numbers to binary: (a) 94, (b) 176, and (c) 235. 94/2=47 with remainder 0; 47/2=23 with remainder 1, 23/2=11 with remainder 1, 11/2=5 with remainder 1, 5/2=2 with remainder 1, 2/2=1 with remainder 0 and 1/2=0 with remainder 1. Taking the remainders in reverse order, we get 1011110 as the binary value. 176/2=88 with remainder 0, 88/2=44 with remainder 0, 44/2=22 with remainder 0, 22/2=11 with remainder 0, 11/2=5 with remainder 1, 5/2=2 with remainder 1, 2/2=1 with remainder 0 and 1/2=0 with remainder 1. Taking the remainders in reverse order, we get 1011 0000 as the binary value. 235/2=117 with remainder 1, 117/2=58 with remainder 1, 58/2=29 with remainder 0, 29/2=14 with remainder 1, 14/2=7 with remainder 0, 7/2=3 with remainder 1, 3/2=1 with remainder 1, 1/2=0 with remainder 1. Taking the remainders in reverse order, we get 1110 1011 as the binary value. 5. List the internal components of the simple processor and describe briefly what each of them does. The Instruction Register holds the current instruction after it is retrieved from memory. The Program Counter holds the address of the next instruction. The Accumulator is used to hold operands for arithmetic operations and store results. It is also the destination of the load instructions and provides the data that is transferred to memory by store instructions. The Indirect Address Register holds intermediate addresses used by the indirect load and store instructions. The ALU implements the various arithmetic and logic operations performed by the processor (add, complement, and). The controller coordinates the activities of all the other components and generates the control signals for the memory. 6. Describe the fetch-and-execute cycle of the simple processor. During the fetch portion of the fetch-and-execute cycle, the processor reads a value from memory, at the location specified by the Program Counter. The data returned from memory is then placed in the Instruction Register. During the execution portion of the cycle, the instruction now present in the Instruction Register is executed. What happens during the execution part varies, depending on the instruction. For example, - 2 -
when an unconditional branch instruction is executed, the Program Counter value is changed to the value specified by the low order 12 bits of the accumulator. If a direct load instruction is executed, the Accumulator value is replaced with a value retrieved from memory. 7. How do the control signals for the memory determine its operation? When the memory enable is low, the memory is idle. When the memory enable is high and the rw signal is high, the memory places a value onto the data bus. The value placed on the data bus is the value stored in the location specified by the value on the address bus. When the memory enable is high and the rw signal is low, the memory replaces one of its stored values with the value on the data bus. The memory location affected by this operation is the one specified by the value on the address bus. 8. For the simple processor, which instructions can cause the accumulator value to change? Which can cause the program counter to change? Which can cause the indirect address register to change? Which can cause the instruction register to change? Which instructions use the ALU? The load instructions, thenegate, the add and the and instructions can all change the accumulator value. Every instruction causes the program counter to increment at the end of the instruction fetch. In addition, the branch instructions may change it during execution. Every instruction changes the value in the instruction register during the fetch. None of them change it during execution. The indirect address register is changed only by the indirect load and indirect store instructions. The ALU is used by the negtate, the add and the and instructions. 9. Suppose that in the simple processor, the memory locations 0100 through 01FF each contain a value that is 5 larger than its address (so 0100 contains 0105, etc). Now suppose the processor executes the instruction 3102 at location 001A. What values are contained in each of the processor s registers after the instruction execution completes? The instruction register contains 3102. The program counter contains 001B. The indirect address register contains 0107. The accumulator contains the value 010C. Now suppose that the next instruction executed by the processor is 5108. What values are contained in each of the processor s registers now? Have any of the values stored in memory changed? If so, how? The instruction register now contains 5108. The program counter contains 001C. The indirect address register contains 010D. The accumulator still contains the value 010C. Location 010D in the memory does change. Its new value is 010C. 10. Suppose that the simple processor fetches and executes the instructions at location 02E4 and 02E5 and that the values of all the processor registers don t change between the completion of the first instruction and the completion of the second instruction. What are the instructions at locations 02E4 and 02E5? (Note, there is more than one acceptable answer.) In order for the instruction register to not change, the instructions must be identical. In order for the program counter to not change, the second instruction must change the value of the program to 02E5. - 3 -
So, one solution is the unconditional branch instruction 62E5. Conditional branches can also work, so long as the accumulator value satisfies the condition, so that the branch is taken. 11. Suppose that in the simple processor, the value in the accumulator is 1ABC before the first instruction in the group of (partially-specified) instructions shown below is executed and that after two instructions have been executed, the accumulator value is E545. Show how the missing hex digits in the first two instructions can be completed in a way that is consistent with this result (assume that all instructions are well-formed). addr value 0130 0001 -- must be negate, since otherwise would halt 0131 a130 -- negating ACC gives E544, adding 0001 gives E545 0132 9130 -- branch to 0130, after next instruction PC=0131 0133 6131 -- this part doesn t matter Suppose that after two more instructions are executed, the value of the program counter is 0131. Show how to complete the third and fourth instructions in a way that is consistent with this result. 12. Write a program for the simple processor that reads a set of input values from the switches and stores them in memory, starting at location 0100. As each value is entered, show it on the display until the next value is entered. Stop accepting input if the user enters zero, or after ten numbers are entered. Then, display the entered values in the reverse order that they were entered. Your program should pause for about one second before going onto the next value in the sequence. You can do this using a loop that simply increments a counter until it reaches some limit value. Note that the clock period of the processor is 20 ns. - 4 -
13. The simulation output shows selected signals from the processor introduced in section 1 of the course notes. The portions of the output corresponding to two different instructions are outlined. Identify the instructions that are being executed. Give the name of the instruction (e.g. direct store, branch-on-positive) and its complete numeric representation. Note that some parts of the simulation output have been blanked out. The first instruction does not access memory during the execution phase and it does change the value of the accumulator. This means it cannot be a load, add or and. It could be a negate or immediate load, but since the new value is not the 2s complement of the original value, it must be the immediate load instruction 1FFF. The second instruction does retrieve data from memory during the instruction execution, so it could be a load, an add or an and. By looking at the address bus, we can see that the value retrieved from memory comes from location 0008 and by looking at the data bus, we can see that that its value is 0001. If this were a load instruction, the new value in the accumulator, after the instruction completes would be 0001. Since it is not, this cannot be a load. If 0001 is added to FFFF, the result is 0, which is what the simulation output shows. Hence, the instruction could be the add instruction A008. Alternatively, it might be the and instruction D008, but in this case the resulting value in the accumulator would be 0001. Hence, it must be an add. - 5 -