Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

Overview Last Lecture s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter MIPS Arithmetic Instructions Register File and Register Naming Convention 2

Review Intro to Computer Architecture Course Style, Philosophy and Structure High Level, Assembly, Machine Language Anatomy of computer system 3

Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Result Store Deposit results in storage for later use Next Instruction Determine successor instruction 4

assembler Different levels of computer language Need to communicate with each other The same thing with computers High level language Assembly language Machine code Natural Different purposes More understandable Better Debugged Portable Better Optimized 5

Different levels of computer language (Cont d) High Level Language Program strange(... ){... } Assembly Language strange: sll $2,$4,2 addu $6,$6,$2... Machine code 00000000100000000001000010000000 00000000110000100011000000100001... compiler assembler 6

Stored Program Computer 7

Stored Program Computer (object code in memory) 8

The process of executing instructions Instruction Fetch PC has the address of the next instruction to be fetched so the control unit fetches the instruction whose address is in PC, and puts it into IR. 9

Next Cycle:? Control unit decodes the instruction and fetches the operands 10

Execute Data path executes the instruction as directed by the Control unit 11

Instruction formats in R3000 Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management Special 3 Instruction Formats: all 32 bits wide Registers R0 - R31 PC HI LO R-format I-format J-format OP OP OP rs rt rd sa funct rs rt immediate jump target 12

Executes (Reg Reg) Data path executes the instruction as directed by the Control unit 13

Mem (Reg Reg) No operation takes place in this cycle 14

WB (Reg Reg) Result will be put into Reg #2 15

Question What if the CPU executes a load instruction lw $2,504($1) what happens in Exe, Mem, and WB 16

RISC: Reduced Instruction Set Computer RISC philosophy Fixed instruction length Load/store instruction set Limited addressing modes Limited operations Examples Alpha processor, Sun SPARC, SGI MIPS, Design a good instruction set How well compilers use it; compiler optimization 17

Homework Assignment SPIM a MIPS Interpreter 18

MIPS Arithmetic Instructions Assembly arithmetic statement add $3, $1, $2 sub $3, $1, $2 Each arithmetic instruction performs only one operation Each arithmetic instruction specifies exactly three operands Destination source1 op source2 The operands should be the contents of the datapath s register files The operand s order is fix: Destination first 19

An example If b is in register $1, c in $2, d in $3, and the result supposed to be in $4 h = (b c) + d sub $5, $1, $2 add $4, $5, $3 20

MIPS Register file Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath s register file Holds thirty-two 32-bit registers 2 read ports 1 write port Registers are Faster than main memory Easier for compiler to use (a * b) (c * d) (e * f) any order of these multiplication Can hold variables so that Code density is improved (fewer bits used to address registers than memory locations) 21

interface Register file (Cont d) 32 bits R#0 src1 addr src2 addr dest addr 5 5 5 interface R#1 R#2 32 32 src1 data src2 data R#31 32 22 Write Back data

Register file (Cont d) 23

Register spilling More about Registers Limited number of registers Compilers place not commonly used registers back into memory Why registers are faster? Small register file Difference in technology Higher throughput in register operations, therefore higher throughput in register file 24

Naming Convention for registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 25

Compile example f = g + h + i if f is in $s0, g in $s1, h in $s2, i in $s3 add $s0,$s1,$s2 add $s0,$s0,$s3 f = (g + h) (i + j) if f is in $s0, g in $s1, h in $s2, i in $s3, and j in $s4 26

Compile Data transfer instructions G = h - A[7]; address of A[0] is in $s1, G in $s2, and h in $s3 27

Compile Example A[20] += A[8]; address of A[0] is in $s1 29

Anatomy of data transfer inst. lw $t0, 5($s1) offset Base register Index register (why?) 30

Instructions, so far Translate to machine code A[20] +=A[8]; 31

Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter MIPS and Register File Register Naming convention 32

Today s class Register Naming Convention, a review MIPS Arithmetic, Load/store and logical instructions slt and jr instructions Branches and jumps pc relative addressing 33

Naming Convention for registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 34

Compile Example A[20] += A[8]; address of A[0] is in $s1 35

Anatomy of data transfer inst. lw $t0, 5($s1) offset Base register Index register (why?) 36

Instructions, so far Translate to machine code A[20] +=A[8]; 37

Shifters Two kinds: logical-- value shifted in is always "0" "0" msb lsb "0" arithmetic-- on right shifts, sign extend msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! 38

MIPS logical instructions and $1,$2,$3 $1 = $2 & $3 or $1,$2,$3 $1 = $2 $3 nor $1,$2,$3 $1 = ~($2 $3) andi $1,$2,10 $1 = $2 & 10 ori $1,$2,10 $1 = $2 10 sll $1,$2,10 $1 = $2 << 10 srl $1,$2,10 $1 = $2 >> 10 sra $1,$2,10 $1 = $2 >> 10 39

A different style Make access to small constant fast Application for(j=0;j<10;j++) A[j]++; Profile analysis shows: In gcc 52% In spice 69% Of arithmetic instructions involve constants op rs rt immediate addi $s4,$s4,4 40

A tiny problem What if the immediate value is beyond the range that 16 bits can provide By the way, what is this range? lui $s1,5 $s1 0000 0000 0000 0101 0000 0000 0000 0000 What if I want to load 5*2 16 +25 to $s1? Who is responsible for doing this? MIPS provides $at for such cases 41

American Std Code for Info. Interchange (ASCII) 42

Load and store bytes lb $t0,0($sp) sb $t1,4($sp) $sp 43

Alignment MIPS requires that all words start at addresses that are multiples of 4 bytes 0 1 2 3 Aligned Not Aligned Called Alignment: objects must fall on address that is multiple of their size. Why do we care? 44

Endian-ness or Edianess Big Endian: Leftmost byte is word address Little Endian: Rightmost byte is word address 3 2 1 0 little endian msb lsb Big endian 0 1 2 3 45

MIPS arithmetic instruction format R-type: I-Type: 31 25 20 15 5 0 op Rs Rt Rd funct op Rs Rt Immed 16 Type op funct ADDI 10 xx ADDIU 11 xx SLTI 12 xx SLTIU 13 xx ANDI 14 xx ORI 15 xx XORI 16 xx LUI 17 xx Type op funct ADD 00 40 ADDU 00 41 SUB 00 42 SUBU 00 43 AND 00 44 OR 00 45 XOR 00 46 NOR 00 47 Type op funct 00 50 00 51 SLT 00 52 SLTU 00 53 46

lbu $t0,0($s0) lb $t0,0($s0) New instructions Extension $t0 94H $s0 94H 47

Examples 0X4E + 0X1F 0X4E 0X1F Overflow Addition/Subtraction operation condition result A + B A > 0 B > 0 < 0 A + B A < 0 B < 0 > 0 A - B A > 0 B < 0 < 0 A - B A < 0 B > 0 > 0 48

What to do on overflow? Ignore Programmer is responsible for Leave it to OS Either completely takes care of it Or signals the application What does MIPS do? For signed operation (if overflow occurs) it throws an exception It ignores the overflow of unsigned operations 49

PC -> EPC If an overflow is detected mfc0 places EPC to a register ($k0 and $k1 are used for such a purpose) Jump to a code which services the interrupt based on the type of the interrupt Resolve the problem Return with an error code Abort program 50

More in overflow No means to check if overflow occurs in MIPS Question: How would I indicate that an overflow occur? For signed operations Unsigned operations 51

Instructions for making decisions Conditional/Unconditional branches beq bne j Example Compile $s1,$s2, L1 $s3,$s4, L2 L3 if(i == j) f = g + h k; else f = g + h + k; Given i: $s1, j: $s2, f: $s3, g: $s4, h: $s5, and k: $s6 52

More examples compile Loop: g += A[i]; i += j; if(i!= h) goto Loop; 53

Compile a while loop while (save[j] == k) j += n; Loop: if(save[j]!= k) goto Exit; j += n; goto Loop; Exit: 54

Hierarchical Interpretation of an Application (Executable file) Executable File Object Object procedure procedure Basic block Basic block instruction 55

slt $s1,$s2,$s3 if $s2 < $s3 set $s1 to 1 else set $s1 to 0 New Instructions jr $s0 jump to the address given by the $s0 56

I-Type Branches (Conditional) bne $s0, $s1, Exit 5 16 17 Exit What seems to be the problem? 57

PC Relative addressing MIPS adds the content of PC to the immediate field to provide a wider range. Why? 50% of conditional branch targets in gcc are smaller than 16 instructions apart from their origin bne $s0, $s1, address PC = (PC + 4) + 4*address What is the range of the branching? What if you need branch farther than that? We will come back to this shortly. 58

J-Type Unconditional Branches opcode Target address What range could it provide? Keep in your mind that J-Type is also word address In J-Type 4 upper bits of the PC will be unchanged Do not place the program across the boundary of 256 MB : 64 million instructions 59

bne $s1,$s2, L1 Final Question and L1 is beyond [-2 17, 2 17 ] apart from PC 60

Function calls and Procedures What is the difference between a function call and a procedure? Leaf versus Recursive What is needed for supporting the procedure calls by hardware? 61

Registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (caller can clobber) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) 62

Instructions jal x (again jal is also word address) $ra= PC + 4 Jump to the address 4*x Instruction type is J with opcode 3 jr $ra Which we have seen already and jump to the instruction whose address is in the register; in this case we have return address register Instruction type is R with opcode 0 and func 8 63

Steps for Making a Procedure Call 1. Save necessary values onto stack 2. Assign argument(s), if any $a0 - $a3 for arguments 3. jal call 4. Restore values from stack 64

Steps taken by the Callee 1. Acquire the storage resources needed If need any of $s registers, should save them onto the stack, and after use restore them back to the registers 2. Perform the desired task 3. Place the result values in $v0 and $v1 4. jr $ra 65

Rules for Procedures Called with a jal instruction, returns with a jr $ra Accepts up to 4 arguments in $a0, $a1, $a2 and $a3 Return value is always in $v0 (and if necessary in $v1) Must follow register conventions (even in functions that only you will call)! 66

Hand - Compile Example int leaf(int g,int h,int i,int j){ int f; f = (g + h) (i + j); return f; } 67

MIPS memory layout 68

Example Hand - compile int leaf(int arg){ int l=10; return l*arg; } main(){ int j; j = leaf(5); } 69

Recursive Calls int fact(int n){ if(n <= 1) return 1; return n * fact(n-1); } int fact(int n){ int a; int b; if(n <= 1) return 1; a = fact(n 1); b = n * a; return b; } 70

Recursive Calls (Cont d) main(){ int j=fact(3); } fact(3){ a=fact(2); b=3*a; return b; } fact(2){ a=fact(1); b=2*a; return b; } 71

How to represent strings Use the beginning of the string for the length (4 bytes) Accompany string with a variable length Use a special character at the end of the string as an indication of string s end (C uses null for that purpose) 72

Example Hand compile strcat(char s[], char t[]){ int i,j; i=j=0; while(s[i]!= 0) i++; while((s[i++] = t[j++])!= 0); } 73

Some Words about SPIM Comments, Identifiers, Labels, Number representation, Strings, and Special Characters Some assembly directives.text <addr>.data <addr> Mydata:.word 1,2,3.ascii str1.asciiz str2 74

System Calls What is a system call? SPIM provides a small set of system calls How does it work? Load syscall code into $v0 Load arguments (if any) into $a0,, $a3 Issue syscall 75