Characterize and Debug Crosstalk Issues with Keysight Crosstalk Analysis App

Similar documents
Advanced Jitter Analysis with Real-Time Oscilloscopes

Keysight N8833A and N8833B Crosstalk Analysis Application for Real-Time Oscilloscopes. Data Sheet

Crosstalk Analysis Application

Agilent Technologies EZJIT and EZJIT Plus Jitter Analysis Software for Infiniium Series Oscilloscopes

Board Design Guidelines for PCI Express Architecture

Keysight Technologies EZJIT Plus Jitter Analysis Software for Infiniium Oscilloscopes. Data Sheet

ECE 497 JS Lecture - 21 Noise in Digital Circuits

Analyzing Digital Jitter and its Components

Automotive Ethernet BroadR-Reach

Jitter Basics Lab Using SDAIII & Jitter Sim

JitKit. Operator's Manual

Copyright 2011 by Dr. Andrew David Norte. All Rights Reserved.

DisplayPort 1.4 Webinar

Power Integrity Measurements

How to Solve DDR Parametric and Protocol Measurement Challenges

Proposal for modeling advanced SERDES

Specifying Crosstalk. Adam Healey Agere Systems May 4, 2005

Agilent Technologies S-Parameter and TDR Impedance Measurement Solution Summary

WENS 540 Multifunction Oscillscope Meter

5 GT/s and 8 GT/s PCIe Compared

Fairchild Semiconductor Application Note December 2000 Revised June What is LVDS? FIGURE 2. Driver/Receiver Schematic

N1014A SFF-8431 (SFP+)

Understanding and Performing Precise Jitter Analysis

Simulation Results for 10 Gb/s Duobinary Signaling

PCI Express 4.0. Electrical compliance test overview

Keysight Technologies N7020A Power Rail Probe for Power Integrity Measurements N8846A Power Integrity Analysis Application

RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications. Revision Date: March 18, 2005

Using RJ45 Category 7 Cabling for 2 Lane, 1 and 2.5Gbps Serial Data Transmission

40 and 100 Gigabit Ethernet Consortium Clause 86 40GBASE-SR4 and 100GBASE-SR10 PMD Test Suite v0.1 Technical Document

COMPLIANCE STATEMENT

High Speed Design Testing Solutions

High-Speed Jitter Testing of XFP Transceivers

Agilent Technologies Advanced Signal Integrity

DesignConEast 2005 Track 6: Board and System-Level Design (6-TA4)

Crosstalk Measurements for Signal Integrity Applications. Chris Scholz, Ph.D. VNA Product Manager R&S North America

Effortless Burst Separation

High Speed Characterization Report. DVI-29-x-x-x-xx Mated With DVI Cable

PCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers

High Speed and High Power Connector Design

Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation Gbps. Revision Date: February 13, 2009

Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height

Virtex-6 FPGA GTX Transceiver Characterization Report

Agilent N5393C PCI Express Automated Test Application

PCI Express Link Equalization Testing 서동현

Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation

CHAPTER 2 NEAR-END CROSSTALK AND FAR-END CROSSTALK

T10 Technical Committee From: Barry Olawsky, HP Date: 13 January 2005 Subject: T10/05-025r1 SFF8470 Crosstalk Study

PCI Express TM Architecture. PHY Electrical Test Considerations Revision 1.1

PCIe 2.0 Compliance Test

MAX 10 FPGA Signal Integrity Design Guidelines

Designing and Verifying Future High Speed Busses

Agenda. Time Module Topics Covered. 9:30 11:00 Wireless Technologies that Enable the Connected Car

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

in Synchronous Ethernet Networks

HOME :: FPGA ENCYCLOPEDIA :: ARCHIVES :: MEDIA KIT :: SUBSCRIBE

Modeling of Gigabit Backplanes from Measurements

Keysight U7231B, U7231C DDR3 and LPDDR3 Compliance Test Application For Infiniium Series Oscilloscopes DATA SHEET

RClamp TM 0504M RailClamp Low Capacitance TVS Diode Array PRELIMINARY Features

An Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation

EMI/ESD Filters for Cellular Phones

Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement

Interconnect Impedance Measurements, Signal Integrity Modeling, Model Validation, and Failure Analysis. IConnect TDR Software.

ProASIC3/E SSO and Pin Placement Guidelines

Chapter 4_2 Signal Integrity in Digital Design

Automotive Electronics Council Component Technical Committee

Tektronix Innovation Forum

Receiver Tolerance Testing With Crosstalk Aggressors TT-MA2. ArvindA. Kumar, Intel Corporation Martin Miller Ph.D., LeCroy Corporation.

On the Modeling and Analysis of Jitter in ATE Using Matlab

PCI Express Electrical Basics

Ethernet SFF-8431 SFP+ SFF-8635 QSFP+ Compliance and Debug Testing. Anshuman Bhat Product Manager

EZJIT Plus Jitter Analysis Software for Infiniium Oscilloscopes

ProASIC PLUS SSO and Pin Placement Guidelines

EDA365. DesignCon Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk

E L E C T R I C A L A N A L Y S I S R E P O R T. Use of Z-PACK 2mm HM for Fibre Channel Applications Application Note #20GC001-1 March 13, 2000

DDR4: Designing for Power and Performance

Keysight N8841A CAUI-4 Electrical Performance Validation and Conformance Software

Keysight Technologies N6468A SFP+ Electrical Performance Validation and Conformance Software

Making Your Most Accurate DDR4 Compliance Measurements. Ai-Lee Kuan OPD Memory Product Manager

Successfully Make AC Line Disturbance Measurements

LeCroy Corporation 700 Chestnut Ridge Road Chestnut Ridge, NY Tel: (845) , Fax: (845) Internet:

LVDS applications, testing, and performance evaluation expand.

Serial Attached SCSI Physical layer

NBASE-T and IEEE802.3bz Ethernet Testing 7 MARCH 2016

CPU. PCIe. Link. PCIe. Refclk. PCIe Refclk. PCIe. PCIe Endpoint. PCIe. Refclk. Figure 1. PCIe Architecture Components

Optical SerDes Test Interface for High-Speed and Parallel Testing

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

Comparison of BER Estimation Methods which Account for Crosstalk

Keysight N8814A 10GBASE-KR Ethernet Backplane Electrical Performance Validation and Conformance

PCI Express Signal Quality Test Methodology

Cluster-based approach eases clock tree synthesis

IP1001 LF DESIGN & LAYOUT GUIDELINES

CIRCUIT DESIGN. is published monthly by: UP Media Group Inc Powers Ferry Road, Ste. 600 Atlanta, GA Tel (678) Fax (678)

Keysight N5990A DisplayPort Extended Tests Embedded DisplayPort

Explore your design space including IBIS AMI models with Advanced Channel Simulation

AOZ8808. Ultra-Low Capacitance TVS Diode. Features. General Description. Applications. Typical Applications

IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems

PSEC-4: Review of Architecture, etc. Eric Oberla 27-oct-2012

Training Kit for HP 1660/70 Series Logic Analyzers

DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

Signal Integrity Analysis for 56G-PAM4 Channel of 400G Switch

Transcription:

Chong Min-Jie Characterize and Debug Crosstalk Issues with Crosstalk Analysis App Page

Characterize and Debug Crosstalk Issues with Crosstalk Analysis App Min-Jie Chong HPS Product Manager & Planner Oscilloscope & Protocol Division Make important design decisions and recover your crosstalk margins

Agenda Page 3 Crosstalk Overview and Types Challenges with Crosstalk Analysis Today Overcome Challenges with Crosstalk Analysis App Analyze and Remove Crosstalk Theory of Operation Summary

Agenda Page 4 Crosstalk Overview and Types Challenges with Crosstalk Analysis Today Overcome Challenges with Crosstalk Analysis App Analyze and Remove Crosstalk Theory of Operation Summary

Crosstalk Overview Amplitude interference uncorrelated with data pattern. Victim In Impact on Eye Aggressor Dv No crosstalk Victim Out Dt Dt = Dv/Slope victim With crosstalk Page 5

Transmission Line Crosstalk Crosstalk is becoming a more important issue, as data speeds increase, and more lanes are packed into small spaces. For example: 100G standards with 4 parallel 25 Gb/s lines ASICS with 100 s of SerDes Transmission line crosstalk is the result of electromagnetic interference between electrical components. Mainly caused by capacitive or inductive coupling between multiple signal lines. Two prominent types: Far End Xtalk (FEXT) Near End XTalk (NEXT) Aggressor Mutual Inductance and Capacitance between 2 transmission lines. Victim Transfer function examples for insertion loss, NEXT and FEXT NEXT FEXT Page 6

Far-End Crosstalk (FEXT) Rx Tx Tx Victim Tx Rx Rx No Serial Aggressor Rx Tx Tx Victim FEXT Tx Rx Rx FEXT Serial Aggressor Data rate and pattern of the aggressor and victim are the same, the eye diagram of the victim will show a bulging indicative of FEXT. Page 7

Near End Crosstalk (NEXT) Rx Tx Tx Victim Tx Rx Rx Rx Tx Tx NEXT Victim Tx Rx Rx No Serial Aggressor NEXT Serial Aggressor Page 8

Power Supply Aggressor PSIJ Power Supply Induced Jitter No Power Aggressor With PSIJ Aggressor Horizontal eye closure High frequency noise in the power supply, induces horizontal jitter. Page 9

Power Supply Aggressor VDAN Voltage Dependent Amplitude Noise No Power Aggressor With Power VDAN Aggressor Thick High level Noise on V cc is transferred to logic high bits, but not affecting the logic low bits, which are tied to ground. Page 10

Power Supply Victim A power supply can also be a victim, where the serial data lines are the aggressors. The best example is Simultaneous Switching Noise (SSN) which can create Ground Bounce (the high voltage rail can also bounce and may be referred to as V cc sag). SSN is the result of parasitic inductances that lie between the device (chip) ground and the system (board) ground. When a serial data line switches states, current flows through these inductances which produces a voltage drop. The more lines that switch at the same time (simultaneously) the bigger the drop. A simplified circuit showing the parasitic inductances that contribute to ground bounce Page 11

Power Supply Victim Example of power supply victim due to clock edges Serial Aggressor Power Supply Victim Power Supply without aggressor Note the large ringing in the yellow power supply that is correlated with the edges of the clock. Page 12

Agenda Page 13 Crosstalk Overview and Types Challenges with Crosstalk Analysis Today Overcome Challenges with Crosstalk Analysis App Analyze and Remove Crosstalk Theory of Operation Summary

Legacy Method of Measuring Crosstalk The need to troubleshoot and characterize crosstalk is not new, but the legacy methods of measuring crosstalk in digital communications systems has relied on the process of selectively disabling some channels while enabling others. This necessarily requires measuring the crosstalk effects in the system while operating in special test modes, which means measuring them under abnormal conditions. Worse yet, some systems cannot even operate the necessary special modes. Victim Turn off Aggressor Victim Turn on Aggressor Manually measure the crosstalk effect on the eye with aggressor on and off Challenges: No special test modes to turn on and off aggressors Huge effort and time to characterize crosstalk from multiple serial aggressors. Power supply cannot be turned off. Page 14

Crosstalk Simulation, but not Identification or Removal VNA can be used to characterize crosstalk between serial data lines. S-parameter models are generated by the VNA. Scope and software tools are available today, using the S-parameter models to simulate the waveform distortion, eye closure and jitter performance. Measured signal 1 InfiniiSim Scope Tool + Measured signal 2 Measured signal 3 S-parameter S-parameter Simulated eye opening on signal 1 with signal 2 and 3 aggressors However, the tools are limited only to simulation, but unable to identify source of crosstalk on the real system or remove crosstalk from the measured waveforms for analysis to see how much margin can be recovered. Page 15

Power Supply, Non-Linear Crosstalk For serial data lines, VNA can be used to characterized the crosstalk because they are linear network model. However, the influence of power supply noise to serial data jitter and amplitude distortion is non-linear and no easy way to characterize the crosstalk transfer. HF Noise Serial Data Victim Power supply noise LF Ripple Non-linear crosstalk transfer Time Interval Error Power supply noise creates a non-linear transfer on the serial data timing error. The crosstalk transfer is difficult to solve and correlate. Page 16

Inaccessible Aggressor Signals Crosstalk could happen inside a package with accessibility only to the serial data output. Is there a way to characterize or debug such scenario? Many crosstalk issues happen inside the package. How to troubleshoot crosstalk when the aggressors are inaccessible? Page 17

Agenda Page 18 Crosstalk Overview and Types Challenges with Crosstalk Analysis Today Overcome Challenges with Crosstalk Analysis App Analyze and Remove Crosstalk Theory of Operation Summary

Crosstalk Analysis Challenges Solved by Application Crosstalk Identification Which signals are coupling onto your victim? Crosstalk Quantification How much error does each aggressor add to your victim? Crosstalk Removal for Analysis What would your signal look without crosstalk? How much margin can be recovered on your signal without crosstalk? If the signal was failing spec, can it pass without crosstalk? Assist in making important design decisions: Is it worth reducing crosstalk impact in design? Where to improve? Page 19

Features of the Crosstalk Analysis Application 1. Analyze up to four signals (aggressors or victims) at once 2. No crosstalk model or simulation files required 3. Identify aggressors by probing around 4. Report the amount of crosstalk present on victims 5. Work for both NEXT and FEXT, automatically determined by the app 6. Work for power supply analysis 7. Plot waveform without crosstalk on the scope which can be: Used by SDA, EZJIT Complete, InfiniiSim, Equalization and Mask test Saved as a waveform file Page 20

Overcome Inaccessible Aggressor Signals The crosstalk application can remove the ideal, ISI and return a waveform with Unknown XT + Noise (residual). Perform further analysis on this residual waveform with measurements such as FFT, markers, etc. to root cause the source of aggressor. Remove: Ideal + ISI of Victim Show: Only Unknown XT + Noise Measured waveform = Ideal + ISI + Unknown XT + Noise Clock coupled into serial data inside the package Simulated waveform = Unknown XT + Noise FFT on Unknown XT + Noise Page 21

Crosstalk Analysis Setup 1. Probe up to 4 signals (Aggressors or victims). No simulation models or inputs are required. 2. Setup the victim signal. 4. The app reports the amount of crosstalk from each aggressors and return a waveform without crosstalk for analysis. 3. Set the number of aggressors and configure the aggressor type. Crosstalk Analysis Application Page 22

Agenda Page 23 Crosstalk Overview and Types Challenges with Crosstalk Analysis Today Overcome Challenges with Crosstalk Analysis App Analyze and Remove Crosstalk Theory of Operation Summary

NEXT and FEXT on Serial Victim Rx Tx Tx Victim Tx Rx Rx Rx Tx Tx NEXT Victim FEXT Tx Rx Rx No Serial Aggressor NEXT & FEXT Aggressors Page 24

Removing NEXT and FEXT with Crosstalk App NEXT and FEXT Aggressors Off With NEXT and FEXT Aggressors Use the crosstalk app to remove effect of NEXT and FEXT NEXT and FEXT Removed Page 25

Power Supply Aggressor (VDAN) on Victim Voltage Dependent Amplitude Noise No Power Supply Aggressor With Power Supply Aggressor Stable Vcc Repetitive Noise & Spikes on Vcc Page 26

Removing Power Supply Aggressor (VDAN) With Power Supply Aggressor Power Supply Aggressor Removed Use the crosstalk app to remove effect of power supply crosstalk Page 27

Removing Power Supply Aggressor (VDAN) Measured Victim Without Aggressor Victim With Power Supply Aggressor Thick High level Victim after Power Supply Aggressor removed Page 28

Power Supply Induced Jitter (PSIJ) Crosstalk on Victim No Power Supply Aggressor With Power Supply Aggressor Noise and Data TIE correlates Power Supply Power Supply TIE Trend TIE Trend Page 29

Removing PSIJ from Victim With Power Supply Aggressor Power Supply Aggressor Removed with Improvement on Data TIE Trend Power Supply Power Supply TIE Trend TIE Trend with the glitch Page 30

Removing PSIJ from Victim Measured Victim Without Aggressor Measured Victim with Power Supply Aggressor Victim after Power Supply Aggressor removed Page 31

Crosstalk Results Understanding the results Victim: Aggressor pair ISI and Serial Data Crosstalk Crosstalk signature deskew Distortion (rms) affecting victim Vertical distortion (rms) affecting victim logic high Power Supply Crosstalk Vertical distortion (rms) affecting victim logic low Crosstalk signature deskew Time Distortion (rms) affecting victim ISI Serial data XT Power supply XT Signature of the serial data is found after de-skewing by 25 ps 14% distortion from ISI. 8% distortion from serial data crosstalk. 6% of the power supply signature is found in the logic level high. 2% of the power supply signature is found in the logic level low. Signature of the power supply is found in the TIE after deskewing by 227 ns 14% distortion of the TIE comes from ISI and 18% comes from the power supply Page 32

Crosstalk Error RMS and PP Calculation Crosstalk on victim, correlated to aggressor signature XT (rms) XT (pp) RMS does not change much between both crosstalk waveforms RMS provides more stable results PP shows the peaks of the crosstalk XT (rms) XT (pp) RMS and PP of the victim waveform Victim (rms) Victim (pp) Volt, Error (rms) = XT (rms) Victim (rms) % Volt, Error (pp) = XT (pp) Victim (pp) % Page 33

ISI Error RMS and PP Calculation Ideal victim waveform Subtract Best fit ISI waveform = RMS and PP of the ISI error ISI (rms) ISI (pp) Volt, Error (rms) = ISI (rms) Victim (rms) Volt, Error (pp) = ISI (pp) Victim (pp) Page 34

Jitter Improvement Without Power Supply Crosstalk Waveforms with and without crosstalk are feed into EZJIT Plus for jitter analysis. Waveform with XT TJ = 158ps PJdd = 58ps DJdd = 68ps Waveform without XT An improvement of 20% to total jitter without crosstalk. TJ = 124ps PJdd = 27ps DJdd = 33ps Page 35

Agenda Page 36 Crosstalk Overview and Types Challenges with Crosstalk Characterization and Debug Overcome Challenges with Crosstalk Analysis App Application Features & Test Setup Crosstalk Analysis Results Theory of Operation Summary

Crosstalk Network Models The crosstalk application constructs different types of crosstalk models from the measured waveforms depending on the victim and aggressor signal types. In the simplest case, when both victim and aggressor are serial data signals, the model is a linear n-port transfer function model. Probing the two serial data channels provides the input waveforms to the crosstalk application. A 4-port network model for two parallel transmission lines. The black dots show possible probe locations at the far end. Page 37

Crosstalk Network Models (continued ) The application begins analyzing the waveforms by extracting the serial clock and data pattern of each. It then uses the ideal data pattern as input to the 4-port linear crosstalk model and computes the best-fit transfer function model, which transforms the ideal waveforms into the actual measured waveforms. Within the model, h 11 and h 22 represent the signal s ISI while h 21 and h 12 represent the coupling or crosstalk between the two signals. This approach allows the crosstalk analysis application to remove the effect of either the crosstalk, ISI or both crosstalk and ISI from the measured waveforms. The crosstalk analysis application computes a 4-port linear crosstalk model, which transforms the ideal waveforms into the actual measured waveforms. Page 38

Agenda Page 39 Crosstalk Overview and Types Challenges with Crosstalk Characterization and Debug Overcome Challenges with Crosstalk Analysis App Application Features & Test Setup Crosstalk Analysis Results Theory of Operation Summary

Most Comprehensive Crosstalk Analysis Application N8833A/B Key Value Propositions Page 40

Q and A Session Page 41