Project Name. No 1 Alhaad Gokhale Shubham Mahajan. Number 08CS EC3506

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Group Name No 1 Alhaad Gokhale Shubham Mahajan Roll Number 08CS3007 08EC3506 Project Name PLA to AND-XOR Format: Given a multi-output function representation in.pla format, use a BDD-based mapping technique to convert it to AND-XOR format. Apply transformations to the AND-XOR graph so as to optimize some objective function. 2 Sankhadeep Pal 08EC3212 Fault Diagnosis: Create a fault simulator where a fault can be applied to the faulty circuit to find out the faulty response of the circuit. Built a full response dictionary and based on the faulty response create the diagnostic tree and find out the fault injected. 3 Arpit Agarwal Neela Abhinav 4 Srijan Kumar Rajesh Ranjan 5 Kalpak Tapas Rahul Katare 6 Chitresh Sinha Arohi Kumar 08CS3010 08CS3014 09CS1015 09CS1038 09CS1005 09CS3005 09CS3026 09CS1014 Deterministic Test Generation for Combinational Circuit: Implement a test pattern generation algorithm for combinational circuits similar to PODEM, which will take a circuit in ISCAS-85 format as input, and a given fault list, and will output the test vectors as output. Parallel Pattern Multiple Stuck-at Fault Simulator for Combinational Circuits: Implement a parallel pattern multiple stuck-at fault simulator using any programming language. Your code should be able to run with large circuits (circuits with more than 10k gates). The simulator will take as input a combinational circuit in ISCAS-89 (scan) benchmark format, the fault list, and the test vectors, and will produce as output (i) a file containing the list of the faults and their corresponding detection patterns (do not perform fault dropping), and (ii) a file containing the output responses of the test patterns in presence of the faults. Deductive Fault Simulator for Combinational Circuits: Design a two-valued deductive fault simulator for combinational circuits, which can accept input circuit description in ISCAS-85 format. Generate the collapsed fault list using equivalence and dominance relations. The fault list, and input pattern set have to be read from files, and the simulation results also to be stored in a file. Programmable Test Pattern Generator for BIST: Design a LFSR based pattern generator for hard-to-detect-faults using deterministic test patterns. Initially generate random patterns for easy-to-detect faults in the circuit. Then modify the characteristic polynomial and/or reseeding technique to generate the obtained test patterns.

7 Rohan Khandelwal Sagar Khurana 8 Gaurav Kumar Rathi Himanshu Agarwal 9 Rishi Mittal Mayank Parasar 10 S. Vinodh Kumar Shrey Sharma 11 Ravdeep Singh Gill Swastik Singh 12 Gaurab Paul Rishabh Agrawal 13 Swarn Prabhat Abhishek Mitruka 09CS1017 09CS1029 09CS1012 09CS1021 08EC3202 09IE1009 09CS1031 09CS3036 09CS1024 09CS1025 09CS1028 09CS3017 09CS1033 09CS3016 Transition Fault Simulator: Implement a transition fault simulator using any programming language. Your simulator should be able to simulate both single and multiple faults. Your program should take as inputs a circuit in ISCAS-89 (scan) benchmark format, a file containing the faults present in the circuit, a file containing test patterns, and a file containing the delays of standard gates (like: NAND, NOR, AND, OR, XOR, XNOR, NOT, and buffer). The outputs that will be generated are: a file containing the list of the faults and their corresponding detection patterns (do not perform fault dropping), and a file containing the output responses of the test patterns in presence of the faults. Hint: Transition fault simulation can be performed using stuck-at fault simulation. Circuit Partitioning: Given the specification of a multioutput function in.pla format, write a program to partition the original specification into a cascade of simpler specifications. The objective function to be optimized will be the quantum cost of the exclusive-or sum-or-product (ESOP) realizations of the partitioned specifications. Dynamic Power Estimation for Combinational Circuit: Pseudo-random Test Generation: Write a program which will read a circuit in ISCAS-85 format, and the specifications of a LFSR based pseudo-random pattern generator, and will produce an output data file showing the variation of percentage fault coverage with the number of patterns. Implement any fault simulator of your choice. DFT Insertion: Given a sequential circuit in ISCAS-89 format, write a program to insert DFT into the circuit. So, it will take circuit with D flip-flops and covert each of them to scan flip-flops. Also add extra input and output pins if necessary. Given a set of ATPG generated test patterns, convert them in to a proper scan sequence. Deterministic Test Generation for Combinational Circuit: Implement a test pattern generation algorithm for combinational circuits similar to PODEM, which will take a circuit in ISCAS-85 format as input, and a given fault list, and will output the test vectors as output. Scan Chain Reordering to reduce Power: Consider the full scan versions of the ISCAS-89 benchmark circuits. Write a program to perform scan chain reordering on the benchmark circuits for given test sets, for reducing the test power. Use any suitable search technique for the reordering (e.g., genetic algorithm, simulated annealing, etc.)

14 S. Sharath Chandra Gujju Chanakya 15 Deepika Bajaj Sunandita Patra 16 Abhirup Rohan Irlapati Yoganshu Sahu 17 Akshay Kumar Singh Ananth Balashankar 18 J. Mohan Satheesh Dannuri 19 Ramneet Kaur Shreyasi Das 20 Dhawal Gadiya Deependra K. Satoiya 09CS1040 09CS3028 09CS1027 09CS3037 09CS1037 09CS3024 09CS1016 09CS3035 12CS60R27 12CS60R33 12CS60R02 12CS60R04 12CS60R05 12CS60R35 Parallel Pattern Multiple Stuck-at Fault Simulator for Combinationa Circuits: Design a parallel pattern multiple stuck-at fault simulator using any programming language. Your code should be able to run with large circuits (circuits with more than 10k gates). The simulator will take as input a combinational circuit in ISCAS-89 (scan) benchmark format, the fault list, and the test vectors, and will produce as output (i) a file containing the list of the faults and their corresponding detection patterns (do not perform fault dropping), and (ii) a file containing the output responses of the test patterns in presence of the faults. Fault Diagnosis: Create a fault simulator where a fault can be applied to the faulty circuit to find out the pass and failed test patterns. Use Effect-Cause based analysis to find the injected fault. Signature Analysis: Write a program that will take a combinational circuit in ISCAS-85 format, a specified pseudo-random pattern generator based on linear feedback shift register (LFSR), the number of patterns to be applied, a specified LFSR-based signature compressor, and a fault list. The program will measure the percentage of faults that can be detected, and report the simulation results in an output file. Implement any fault simulator of your choice. Concurrent Fault Simulator for Combinational Circuits: Design a concurrent fault simulator for combinational circuits, which can accept input circuit description in ISCAS-85 format. Generate the collapsed fault list using equivalence and dominance relations. The input pattern set have to be read from a file, and the simulation results also to be stored in a file. Scan Chain Reordering to reduce Power: Consider the full scan versions of the ISCAS-89 benchmark circuits. Write a program to perform scan chain reordering on the benchmark circuits for given test sets, for reducing the test power. Use any suitable search technique for the reordering (e.g., genetic algorithm, simulated annealing, etc.) DFT Insertion: Given a sequential circuit in ISCAS-89 format, write a program to insert DFT into the circuit. So, it will take circuit with D flip-flops and covert each of them to scan flip-flops. Also add extra input and output pins if necessary. Given a set of ATPG generated test patterns, convert them in to a proper scan sequence. Memory BIST Generation: Generate synthesizable verilog code of a BIST module for a given memory core. The inputs to the program will be: Size of the memory Type of the memory Signal timing details of the memory interface

21 Vivek Nautiyal Amit Kumar Pathak 22 G. Balaram Sajid M 23 Siba Prasad Laxmi Kant Tiwari 24 AnanthNath Talla Megha Garg 12CS60R10 12CS60R34 12AT60R04 12AT60R07 12AT60R01 12AT60R05 12CS60D01 12CS60R36 March algorithm, to be specified by the user in pseudo-code The program should be general enough to incorporate any memory test algorithm, existing or new. Dynamic Power Estimation for Combinational Circuit: Transition Fault Simulator: Implement a transition fault simulator using any programming language. Your simulator should be able to simulate both single and multiple faults. Your program should take as inputs a circuit in ISCAS89 (scan) benchmark format, a file containing the faults present in the circuit, a file containing test patterns, and a file containing the delays of standard gates (like: NAND, NOR, AND, OR, XOR, XNOR, NOT, and buffer). The outputs that will be generated are: a file containing the list of the faults and their corresponding detection patterns (do not perform fault dropping), and a file containing the output responses of the test patterns in presence of the faults. Hint: Transition fault simulation can be performed using stuck-at fault simulation. Pseudo-random Test Generation: Write a program which will read a circuit in ISCAS-85 format, and the specifications of a LFSR based pseudo-random pattern generator, and will produce an output data file showing the variation of percentage fault coverage with the number of patterns. Implement any fault simulator of your choice. Fault Diagnosis: Create a fault simulator where a fault can be applied to the faulty circuit to find out the pass and failed test patterns. Use Effect-Cause based analysis to find the injected fault. 25 Malay Pramanick 10CS10020 Pseudo-random Test Generation: Write a program which will read a circuit in ISCAS-85 format, and the specifications of a LFSR based pseudo-random pattern generator, and will produce an output data file showing the variation of percentage fault coverage with the number of patterns. Implement any fault simulator of your choice. 26 Arpita Dutta Rajit Karmakar 12EC71P02 Parallel Fault Simulator for Combinational Circuits: Design a parallel fault simulator for sequential circuits, which can accept input circuit descriptions in ISCAS-89 format. The simulator has to be implemented using the compiled-code method. The fault list, and input pattern set have to be read from files, and the simulation results also to be stored in a file.

27 Boga Shravan Sajjade Faisal Mustaq 28 Aayush Goel Chetan Kumar Meena 29 Bhuvnesh Agarwal Abhishek Choudhary 30 Anurag Khandelwal Ayush Patwari 31 Aditya Barelia Abhishek Chourasiya 32 Ritesh Kumar Sinha Manish Kaushal 33 Mahesh Kumar Paras Vishnoi 12CS60R30 12RE91S01 09CS3006 09CS3032 09CS1007 09CS1049 09CS1050 09CS1051 09CS1002 09CS3021 09CS3009 09CS3022 12AT60R03 12AT60R06 SCOAP Testability Measure and Fault Collapsing: Compute the combinational and sequential SCOAP testability measures for all the signal lines of a given sequential circuit. The program should accept input circuit description in ISCAS-89 format, and output the computed results in a file. The program should also output the collapsed fault list based on equivalence and dominance relations. Signature Analysis: Write a program that will take a combinational circuit in ISCAS-85 format, a specified pseudo-random pattern generator based on linear feedback shift register (LFSR), the number of patterns to be applied, a specified LFSR-based signature compressor, and a fault list. The program will measure the percentage of faults that can be detected, and report the simulation results in an output file. Implement any fault simulator of your choice. Combinational Circuit ATPG: Given a combinational circuit in ISCAS-85 format, use the Justify() and Propagate() functions to generate tests using 9-valued logic system. Memory BIST Generation: Generate synthesizable Verilog code of a BIST module for a given memory core. The inputs to the program will be: Size of the memory Type of the memory Signal timing details of the memory interface March algorithm, to be specified by the user in pseudo-code The program should be general enough to incorporate any memory test algorithm, existing or new. Programmable Test Pattern Generator for BIST: Design a LFSR based pattern generator for hard-to-detect-faults using deterministic test patterns. Initially generate random patterns for easy-to-detect faults in the circuit. Then modify the characteristic polynomial and/or reseeding technique to generate the obtained test patterns. Dynamic Power Estimation for Combinational Circuit: Concurrent Fault Simulator for Combinational Circuits: Design a concurrent fault simulator for combinational circuits, which can accept input circuit description in ISCAS-85 format. Generate the collapsed fault list using equivalence and dominance relations. The input pattern set have to be read from a file, and the simulation results also to be stored in a file.

34 T. Sidhartha Ankit Lohia 09CS3001 09CS3007 Fault Diagnosis: Create a fault simulator where a fault can be applied to the faulty circuit to find out the pass and failed test patterns. Use Effect-Cause based analysis to find the injected fault. 35 Badal Murmu 06CS3003 Dynamic Power Estimation for Combinational Circuit: 36 M. Rambabu Shashank Sharma 12AT60R02 12AT60R08 Deductive Fault Simulator for Combinational Circuits: Design a two-valued deductive fault simulator for combinational circuits, which can accept input circuit description in ISCAS-85 format. Generate the collapsed fault list using equivalence and dominance relations. The fault list, and input pattern set have to be read from files, and the simulation results also to be stored in a file.

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