LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS

LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS

LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS by Gary D. Hachtel University of Colorado Fabio Somenzi University of Colorado KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

ebook ISBN: 0-306-47592-8 Print ISBN: 0-7923-9746-0 2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print 1996 Kluwer Academic Publishers Dordrecht All rights reserved No part of this ebook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's ebookstore at: http://kluweronline.com http://ebooks.kluweronline.com

To: Linda, Jordan, and Kira, and Chiara and Laura.

Contents I Introduction 1 1 Introduction 1.1 VLSI: Opportunity and Challenge 1.1.1 Manufacturing Technology 1.1.2 Design technology 1.1.3 Why VLSI 1.2 VLSI Processes 1.3 Design Styles 1.3.1 Design Decomposition 1.3.2 1.4 Overview of Optimal Logic Synthesis 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 5 5 5 6 7 7 8 8 Logic (Circuit) Design Styles 10 Area-Time Tradeoff Curves The Technology Independent View A Bit-Serial Full Adder Circuit The Technology Dependent View Technology Mapping Testing Is What I Fabricated What I Wanted? Graph Models and Finite State Machines Successors and Predecessors 1.5 Graph Algorithms and Complexity 1.5.1 Complexity 1.5.2 Computing the Product of Sets of Sets 1.5.3 Longest Paths 1.5.4 Backtracing 1.5.5 Complexity of Computing the Longest Path 1.6 Asymptotic Complexity (or just complexity) 1.7 1.8 1.9 1.10 1.6.1 1.6.2 1.6.3 Worst Case Asymptotic Upper Bound Complexity Complexity of Algorithms Practical Complexities Brief Summary of MOS Device Behavior Notes Summary Problems 14 15 16 18 19 21 24 24 24 26 27 29 32 33 34 36 36 37 39 39 39

viii CONTENTS 2 A Quick Tour of Logic Synthesis with the Help of a Simple Example 2.1 A Simple Case Conversion Circuit 2.2 First Refinement 2.3 The Transform Block 2.3.1 The CC Block 2.3.2 An Optimized Transform Block 2.4 The Command Interpreter 2.4.1 Checking for Equality 2.5 2.6 Optimizing the Command Interpreter 2.4.2 Technology Mapping Problems 47 47 49 50 52 53 54 54 54 57 58 II Two Level Logic Synthesis 73 3 Boolean Algebras 3.1 Sets, Relations, and Functions 3.1.1 Sets 3.1.2 Relations 3.1.3 Reflexive Binary Relations 3.1.4 Functions 3.2 Partial Orders 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.3 Boolean Functions 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 Partially Ordered Sets Hasse Diagrams The Meet and Join Operations Totally Ordered Sets, Well-Ordered Sets, and Induction Lattices Definition of Boolean Algebras Examples and Properties of Boolean Algebras Boolean Formulae Boolean Functions Boole s Expansion Theorem The Minterm Canonical Form 99 Pseudo-Boolean Functions 101 The Boolean Algebra of Boolean Functions Atoms of a Boolean Algebra 3.4 Don t Care Conditions as Boolean Function Algebra Intervals 3.4.1 Satisfiability Don t Care Conditions 3.4.2 Observability Don t Care Conditions 3.4.3 Deriving Don t Cares From and Interval Specification 3.5 Incomplete Specification of Boolean Functions 3.5.1 Incompletely Specified Switching Functions 3.5.2 Incompletely Specified Boolean Functions 3.6 Notes 3.7 Summary 3.8 Problems 77 77 77 79 80 84 85 86 87 87 89 90 92 92 95 96 97 98 101 101 103 104 105 106 106 106 107 108 108 108

CONTENTS 4 Synthesis of Two-Level Circuits 4.1 Design Optimality 4.2 Two-Level Logic 4.2.1 Cost Functions for Two-Level Implementations 4.2.2 Minimality and Testability 4.3 Sums of Products and Products of Sums 4.4 Implicants and Prime Implicants 4.4.1 Quine s Prime Implicant Theorem 4.5 Iterated Consensus 4.5.1 4.5.2 4.5.3 4.6 4.7 4.8 Consensus and Implications: A Digression The Tabular Method of Computing the Prime Implicants Iterated Consensus in General Recursive Computation of Prime Implicants Selecting a Subset of Primes The Unate Covering Problem 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 Reduction Techniques Essential Columns or Variables Row or Constraint Dominance Column or Variable Dominance Systematically Exploring the Search Space Computation of the Lower Bound 4.9 The Branch-and-Bound Algorithm 4.9.1 4.9.2 4.9.3 Choice of the Splitting Variable Examples of Splitting and Lower Bounding The Unate Covering Problem as an Integer Linear Program 4.10 Multiple Output Functions 4.10.1 4.10.2 4.10.3 4.11 4.12 4.13 Notes Summary Problems Multiple-Output Primes Formulating the Covering Problem Incompletely Specified Multiple-Output Functions 5 Heuristic Minimization of Two-Level Circuits 5.1 Local Search 5.1.1 Local Search Applied to Logic Minimization 5.1.2 A Simple Local Search Algorithm for Logic Minimization 5.2 Checking for Equivalence and Tautology 5.2.1 Unate Functions 5.2.2 Additional Speed-Up Techniques for Tautology Checking 5.2.3 Examples of Tautology Checks 5.3 Choosing the Right Direction 5.3.1 Recursive Complementation 5.4 5.5 Using the OFF-set in the Expansion 5.3.2 Identifying Essential Primes Multiple-Valued Logics ix 127 127 129 130 131 132 134 134 134 135 135 137 138 141 143 146 146 146 147 148 149 152 154 155 160 160 161 163 163 164 165 165 185 185 187 190 191 194 197 199 200 201 203 203 204

x CONTENTS 5.6 5.7 5.8 Notes Summary Problems 205 206 206 6 Binary Decision Diagrams (BDDs) 6.1 Representing Logic Functions with BDDs 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Why Ordering is Important 6.2 6.3 6.4 6.5 6.6 Binary Decision Diagrams by Way of Examples Formal Definition of BDDs How to Build the BDD for Reduced BDDs Design Considerations for a BDD Package Algorithms 6.3.1 The ITE Algorithm 6.3.2 Complement Edges 6.3.3 The Computed Table 6.3.4 Conditioning of the ITE Calls 6.3.5 The ITE_CONSTANT Algorithm Notes Summary Problems 219 220 220 222 225 226 230 231 233 234 237 238 238 240 243 244 244 III Models of Sequential Systems 251 7 Models of Sequential Systems 7.1 7.2 7.3 Introduction to Finite State Machines Synthesis of Finite State Machines FSMs: Definitions, Notation, and Examples 7.3.1 Examples 7.3.2 Incomplete Specification 7.4 FSM Minimization for Completely Specified Machines 7.4.1 Identifying the Equivalent States of an FSM 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 State Equivalence Checking: the Partition/Refinement Approach Finding the Reduced Machine Moore Machines and DFAs The Iterative Collapsing Approach Summary of State Equivalence Checking Methods 7.5 Graph Algorithms for FSM Traversal 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 Shortest Paths 7.6 7.7 Graphs, Subgraphs, and Components Graph Traversal Breadth First Search Traversal Depth First Search Finding the SCCs of a Directed Graph Models of Sequential Systems FSTs: Strings, Runs, Reachability and Products 7.7.1 Finite State Transition Structures 255 255 257 261 261 263 265 265 269 272 272 273 275 275 276 278 280 282 286 289 292 292

CONTENTS 7.7.2 7.7.3 7.7.4 7.7.5 NFAs and FSTs as Labeled Digraphs Strings, Tapes and Runs of FSTs Product of FSTs 7.8 FSM Equivalence Checking 7.8.1 Strings which Distinguish Two Machines 7.8.2 Building the Product Machine 7.8.3 Equivalence Identification by Isomorphism 7.9 Reachability Analysis 7.9.1 FSM Traversal Using Binary Decision Diagrams 7.10 Symbolic FSM State Traversal 7.10.1 Transition Relations and Symbolic Image Computation 7.11 Notes 7.12 Summary 7.13 Problems 8 Synthesis and Verification of Finite State Machines 8.1 Minimization of Incompletely Specified Machines 8.1.1 Finding the Compatible Pairs 8.1.2 Finding the Maximal Compatibles 8.1.3 Finding the Prime Compatibles 8.1.4 Setting up the Covering Problem 8.1.5 Forming the Reduced Table 8.2 The Binate Covering Problem 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 Formulation of BCP Reduction Techniques Choice of the Splitting Variable and Bounding Maximal independent set. Choice of the branching column Infeasible problems. An Example of Reductions 8.3 State Encoding 8.3.1 Practical Encoding Algorithms 8.4 Decomposition and Encoding 8.5 8.6 8.7 8.8 8.4.1 8.4.2 8.4.3 8.4.4 Notes Notes Summary Problems Partitions Partitions with Substitution Property Computation of the S.P. Partitions General Decomposition and State Encoding xi 295 295 297 298 300 300 301 305 305 305 308 308 312 313 313 325 325 328 329 329 332 334 335 337 337 340 340 341 341 342 343 343 347 348 350 352 354 356 357 357 357

xii CONTENTS 9 Finite Automata 9.1 Finite Automata and Regular Languages 9.1.1 String Acceptance 9.1.2 Languages of Finite Automata 9.1.3 Complements of Languages 9.1.4 Examples 9.2 DFA Synthesis 9.2.1 9.2.2 9.2.3 Determinization of FSTs and FAs The Subset Construction The Deterministic Image 9.3 9.4 Automata Formal Verification with L-Automata 9.4.1 Languages 9.5 Language Containment 9.6 9.7 9.8 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 Notes Summary Problems Lifting Acceptance Conditions to a Product L-Automaton Example of Product L-Automaton BDD Representation of Cycle Sets and Recur Edges The Language Containment Algorithm Example of Containment Check 369 370 372 373 376 377 378 383 383 385 387 390 390 392 393 393 394 395 396 397 397 398 IV Multilevel Logic Synthesis 405 10 Multi-Level Logic Synthesis 10.1 Introduction 10.1.1 Networks and Algebraic Operations 10.2 Representation Issues and Choices 10.2.1 Alternate Node Representations 10.3 Representing Switching Functions in Factored Form 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 Factored Forms Algebraic and Boolean Expressions Algebraic and Boolean Factored Forms Value of a Factorization Equivalent, Maximal, and Optimum Factorizations Size, Unateness, and Cofactors of a Factored Form 10.4 Division 10.5 Kernels and Co-Kernels 10.5.1 Computation of Co-Kernels and Kernels 10.6 Heuristic Factoring Algorithms 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 Generic Factoring Algorithm Quick Factor Good Factor Boolean Factor Summary of Factoring Algorithms 409 409 410 412 413 417 417 418 419 420 420 422 422 425 427 428 429 433 434 434 435

CONTENTS xiii 10.6.6 Rectangle Covering 10.7 Decomposition and Restructuring 10.7.1 Algebraic Resubstitution 10.7.2 Selective Node Elimination 10.7.3 Extraction 10.8 Notes 10.9 Summary 10.10 Problems 11 Multi-Level Minimization 11.1 Introduction 11.2 Boolean Networks 11.2.1 Network Cost 11.3 Don t Cares in Multi-Level Networks 11.3.1 Satisfiability Don t Cares 11.3.2 Observability Don t Cares 11.3.3 Use of Don t Cares in Minimization 11.3.4 Internal and External Don t Cares 11.3.5 External Satisfiability Don t Care Conditions 11.3.6 External Observability Don t Care Conditions 11.4 11.5 11.6 11.7 11.8 11.9 Internal Satisfiability Don t Cares Observability Don t Cares 11.5.1 Computing ODCs with the Boolean Difference Prime and Irredundant Networks Two-Level Minimization with Multi-Level Don t Cares Notes Summary 11.10 Problems 12 Automatic Test Generation for Combinational Circuits 12.1 Introduction 12.2 Faults and Fault Models 12.3 Automatic Test Generation 12.3.1 Excitation and Sensitization 12.3.2 A Simple Test Generation Algorithm 12.3.3 Implications and Backtracking 12.3.4 Choice of the Decision Variables 12.3.5 Putting the Pieces Together 12.4 12.5 12.6 12.7 Redundancy Removal Notes Summary Problems 436 436 436 437 439 440 441 441 455 455 456 459 461 461 462 462 463 463 463 464 465 468 468 469 470 470 471 475 475 476 478 478 481 483 486 488 488 492 492 492

xiv 13 Technology Mapping 13.1 Graph Covering and Technology Mapping 13.2 Choice of Base Functions 13.3 Creating the Subject Graph 13.4 The DAG-Covering Problem 13.5 Tree Covering by Dynamic Programming 13.6 Decomposition 13.7 Delay Optimization and Graph Covering 13.8 Notes 13.9 Summary 13.10 Problems A ASCII Codes B Supplementary Problems Bibliography Index CONTENTS 505 506 507 508 509 509 512 513 514 514 515 523 525 537 555

List of Figures 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 MOS gates. 8 A six-transistor gate array cell. A three-input NAND gate obtained from the cell of Figure 1.2 Organization of a channeled gate array Two-input look-up table for FPGAs (Field Programmable Gate Arrays). Area-Delay tradeoff curves. Bit-serial adder circuit Bit-serial adder circuit after technology mapping. Bit-serial adder circuit with fault asserted. Finite State Machine for Majority Circuit. A simple directed graph Logic Graph of 1-bit full adder. The gate outputs are the vertices of the graph and the nets connecting gate outputs to gate inputs are the edges of the graph. Procedure for Intersecting 2 sets of sets. A weighted directed acyclic graph. A function in the set and also in the set The FSM corresponding to the driver circuit of Figure 1.1 (middle) Complex CMOS gate for Problem 1. Solution of Problem 1. Circuit for Problem 4. Procedure LEVELIZE1. 12 12 12 13 15 17 19 19 22 23 25 26 28 29 31 35 38 40 40 41 43 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 Interface of the example circuit. Block diagram for LUNC. Block diagram for the transform block. Procedure CHANGECASE Block diagram for the CC block. Circuit schematic for the optimized transform block. Block diagram for the command interpreter. Procedure SWITCH Circuit schematic for an equality checker. Circuit schematic for the optimized command interpreter Circuit schematic for the technology-mapped decoder of the command interpreter. 48 49 51 52 52 53 54 55 56 56 58

xvi LIST OF FIGURES 2.12 2.13 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 Iterative scheme for the 8-bit comparator of Problem 3. Circuit for Problem 4. Venn Diagrams for illustrating set inclusion. Matrix and graph representations of a binary relation. Illustration of image and preimage. Examples of posets. Examples of lattices. The Boolean algebra defined over the power sets of and The Boolean algebra of the Boolean functions of two variables over B = {0,1}. The interval (represented by solid lines) A simple example relating intervals in a Boolean function algebra to satisfiability and observability don t care conditions. Hasse Diagram for Problem 14. Hasse Diagram for Problem 18. Lattice for Problem 18. Partially ordered set (poset) for Problem 26 Partially ordered set (poset) for Problem 27. Hasse Diagrams for Problem 31. Hasse Diagram for Problem 32. Lattice for Problem 33. Lattice of the Boolean functions of one variable over the Boolean algebra (Problem 58.) 60 62 79 80 86 87 90 93 102 103 104 112 113 113 115 115 117 117 118 125 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 Tradeoff of area for speed for optimal designs. NMOS NAND-NAND PLA. Tabular Method Applied to Tabular Method Applied to an Incompletely Specified Function. Example of Recursion Tree for the Computation of Prime Implicants. A Function with a Cyclic Core. Algorithm for computing an MIS. Recursion Tree for a Covering Problem. Example of Search Tree. Branch-and-Bound Algorithm for the Unate Covering Problem. A search tree produced by Procedure BCP A Two-Output Function that Illustrates the Importance of Sharing Common Terms. Two Implementations for the Multiple-Output Function of Figure 4.12. Tabular Method Applied to the Multiple-Output Function of Figure 4.12. Recursion Tree for Problem 14. Recursion Tree for Problem 20. 128 130 136 137 140 142 151 152 153 154 156 161 161 163 172 175 5.1 5.2 5.3 A Pictorial Representation of Local Search. A Convex Optimization Problem. A Non-Convex Optimization Problem. 186 186 187

LIST OF FIGURES xvii 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 A Function with an Initial Cover (a) and after the Expansion of an Implicant (b). A Function and an Initial Cover Illustrating Output Expansion. The Cover of Figure 5.5 after the Expansion of an Output Part. A Function and an Initial Cover Illustrating Input Reduction. Simple Minimization Loop. A Circuit that is Simplified by MAKE_SPARSE. Example where the Directions in which Cubes are Expanded Matters. (a): Initial Cover. (b): After Reduction. (c): After Expansion in the Right Direction. The Interconnection of Sub-Circuits Gives Rise to Encoding Problems. 187 188 188 189 190 191 200 205 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 A MUX circuit and the corresponding BDD. A binary decision diagram. Another BDD. An optimal BDD BDDs for typical functions. Partial BDD after expansion with respect to Partial BDD after expansion with respect to and Final BDD. Non-reduced BDD. Two isomorphic subgraphs. Merging two isomorphic subgraphs. Elimination of a redundant node. BDD illustrating the advantages of a good ordering. BDD illustrating the drawbacks of a bad ordering. Shared BDD. Two-argument operators expressed in terms of ITE. Pseudo-code of the ITE algorithm Example of application of ITE Equivalent pairs of functions. Pseudo-code of the ITE_CONSTANT algorithm. An example of computation by ITE_CONSTANT. BDDs and ITE BDD for Problem 1. Solution for Problem 1. BDD for Problem 2. Solution for Problem 3. Solution for Problem 4. Pseudo-code of the APPLY algorithm. Pseudo-code of the OR operation. Solution for Problem 6. 221 221 222 223 224 225 226 227 227 228 228 229 230 231 232 234 236 236 237 240 241 242 245 245 246 247 248 249 249 249 7.1 7.2 7.3 7.4 Simple Sequential Circuit. State Transition Graph for the Circuit of Figure 7.1. Simplified FSM Design Flow. An FSM with Redundant States. 256 257 257 258

xviii LIST OF FIGURES 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 7.43 7.44 7.45 7.46 7.47 7.48 A Finite State Machine. Example of State Transition Graph Tabular Representations of FSMs STG of the symbolic LUNC FSM Example of Incompletely Specified FSM. Machine Equivalent to the One of Figure 7.9. The STG of a simple FSM. The STG of an FSM equivalent to the one of Figure 7.11. Procedure for Finding Equivalent States of an FSM. The STG of an FSM in which all state pairs are equivalent. Flow Table for a Completely Specified Mealy Machine. Flow Table for a Completely Specified Moore Machine. Result of Reducing the FSM of Figure 7.16. First Collapsed Flow Table. Second Collapsed Flow Table. A simple undirected graph. A digraph and its strong components A directed graph representing the connectivity of the circuit of Figure 1.12. Procedure for basic Breadth First Search. A directed acyclic graph. Algorithm for Depth First Search Traversal of graph G = (V, E) from start vertex (first call) DAG with nodes labeled by Recursive procedure for depth first search, modified to identify SCCs. Algorithm for popping the SCC stack in DFS_SCC DAG with labeled edges. Procedure for finding shortest paths in a weighted graph. A weighted directed acyclic graph. Models of finite-state transition systems. A Finite State Transition Structure. The STGs of Tables 7.2 and 7.3. NFA example with The FST of the Mead-Conway Traffic Controller. Product of FSTs. Product of Nondeterministic FSTs. Product Machine for Equivalence Checking. Encoded Product Machine for Equivalence Checking. Product of two equivalent FSMs. Procedure for equivalence checking a product machine. Procedure for finding a shortest error trace. A simple BDD representing the characteristic function of the set S. Two non-equivalent FSMs Product of the Two FSMs of Figure 7.45. The STGs of two equivalent FSMs. The STG of a modulo 3 counter. 261 262 262 263 264 264 265 266 268 270 271 273 274 274 275 276 277 277 279 279 281 281 283 284 284 287 288 289 293 294 295 296 299 299 301 302 302 303 304 307 310 310 314 315

LIST OF FIGURES xix 7.49 7.50 7.51 7.52 7.53 7.54 7.55 7.56 7.57 7.58 7.59 The STG of an FSM to be minimized. 315 Procedure for finding 1-equivalent states of an FSM. 316 Procedure for finding equivalent states of an FSM. 317 A Completely Specified Flow Table. 319 STG for the Flow Table of Figure 7.52. 319 A Completely Specified Flow Table. 321 Minimized Flow Table for Figure 7.54. 321 Flow Table for Problem 14. 321 A simple directed graph. 322 Another simple undirected graph. 322 Partial labeling of directed acyclic graph 7.59. 323 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 An incompletely specified Moore machine. Another incompletely specified Moore machine. Reduced machine obtained from the one of Figure 8.2. Machine obtained from the one of Figure 8.2 by state splitting. A flow table and its compatibility table. A flow table to illustrate the computation of prime classes. Compatibility table for the flow table of Figure 8.6. Prime compatibles for the flow table of Figure 8.6. Algorithm for computing prime compatibles. Reduced flow table obtained from the one of Figure 8.6. Reduced flow table obtained from the one of Figure 8.10 by heuristic choices of the next state entries. Branch and bound algorithm for binate covering. Example FSM for the discussion of state encoding. Attraction graph for the FSM of Figure 8.13. Attraction graph produced by the fanout-oriented algorithm of MUS- TANG. An assignment derived by the fanout-oriented algorithm. An assignment derived by the fanin-oriented algorithm. Example of FSM with parallel decomposition. Components of the FSM of Figure 8.18. Structure of the parallel decomposition. Structure of the serial decomposition. Example of FSM with serial decomposition. Independent component for the FSM of Figure 8.22. First step in the construction of the dependent component. Second step in the construction of the dependent component. Example FSM for the computation of the S.P. partitions. S.P. partition lattice for the example of Figure 8.26. Example FSM for encoding based on partition pairs. Schematic for the encoding of the machine of Figure 8.28. An incompletely specified flow table. Compatibility table for the flow table of Figure 8.30. Search tree for Problem 3. 326 326 327 327 328 330 330 332 333 335 335 336 344 344 346 346 347 350 351 351 352 352 352 353 353 353 354 355 356 357 358 359

xx LIST OF FIGURES 8.33 8.34 8.35 8.36 8.37 8.38 8.39 8.40 8.41 8.42 8.43 8.44 8.45 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 Result of minimizing the flow table of Figure 8.30 using maximal compatibles only. Flow table for Problem 7. Compatibility table for the flow table of Figure 8.34. Covering table for Problem 7. Search tree for the covering problem of Figure 8.36. Result of minimizing the flow table of Figure 8.34. Flow table for Problem 9. Matrices S and Z for Problem 9. Attraction graph for the fanout-oriented algorithm. Encoding for the fanout-oriented algorithm. 359 361 362 364 364 365 365 366 366 367 Matrices and X for Problem 9. 367 Attraction graph for the fanin-oriented algorithm. Encoding for the fanin-oriented algorithm. 367 368 Physical implementation of a Finite Automaton. A DFA accepting all strings ending in 111. An NFA (Nondeterministic Finite Automaton). Procedure for deciding string acceptance. 370 370 371 373 An NFA (top) and DFA (bottom) accepting the language of Example 9.1.1.375 A DFA abstracted from the modulo 3 counter of Problem 5 of Page 314.376 The complement of the DFA of Figure 9.6. 376 A simple DFA. Binary Parse Tree for Rule for constructing an NFA which accepts the product of two regular languages. Incorrect rule for constructing an NFA which accepts the product of two regular languages. Rule for constructing an NFA which accepts the union of two regular languages. Rule for constructing an NFA which accepts the closure of two regular languages. NFA whose language is DFA whose language is Algorithm SUBSET_CONSTRUCTION for determinizing a given NFA. An FST and its deterministic image. An L-automaton for expressing a safety property in formal verification. An L-automaton recognizing a class of tapes (infinite strings with at most two inputs after an unless there is an intervening ). An L-automaton recognizing a tapes containing an infinite number of substrings. Illustration of and Automata Accepting and An example of a product automaton. ProcedureLANGUAGE_CONTAINMENT. Illustration of non-containment in cycle set. 377 379 379 380 381 382 382 384 386 387 387 389 390 391 392 394 396 396

LIST OF FIGURES xxi 9.26 9.27 9.28 9.29 9.30 9.31 Language containment test on the product automaton of Figure 9.23. 397 Flow table equivalent Moore machine for Problem 1. 399 A DFA for recognizing a certain string. 400 The DFA for Problem 5. 401 An L-automaton expressing a liveness property in formal verification. 402 A simple L-automaton. 403 10.1 Example of Local Optimization. 10.2 Another Example of Local Optimization. 10.3 Example of Circuit Restructuring. 10.4 Example of Boolean Network. 10.5 A CMOS Complex Gate Implementing 10.6 A Simple Gate Implementation of 10.7 NAND and NOR Decompositions. 10.8 Factoring Tree for 10.9 Weak Division Algorithm. 10.10Procedure GEN_FACTOR. 410 410 411 411 415 415 416 420 425 432 10.11Procedures QUICK_FACTOR, QUICK_DIVISOR, and ONE_LEVEL-0_KERNEL.433 10.12Procedure for good factorization 434 10.13Procedure BOOL_FACTOR. 435 10.14Procedure QUICK-EXTRACTION. 439 10.15Factoring Tree for Problem 5. 443 10.16Factoring Tree for Problem 8. 443 10.17Boolean Network for Problem 24. 449 10.18Boolean Network for Problem 24 after Resubstitution. 449 10.19Boolean Network for Problem 26 after Extraction. 451 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Example for Boolean Network. (Input and Output Elements are Buffers and are Considered Part of the Network.) 459 An Example Network for the Computation of Observability Don t Cares.467 Network for Problem 3. 472 Boolean Network for Problem 4. Simplified Boolean Network for Problem 4. Boolean Network for Problem 6. Simplified Boolean Network for Problem 6. Circuit for Problem 7. 473 473 473 474 474 12.1 A short-circuit in a CMOS inverter. 12.2 Stuck-at faults. 12.3 Equivalent faults. 12.4 A simple combinational circuit. 12.5 Another simple combinational circuit. 12.6 A redundant combinational circuit. 12.7 A combinational circuit. 12.8 Use of compound values. 12.9 Frontier element (G4) and unjustified element (G1). 12.10Decision tree for the example of Figure 12.7. 476 476 477 478 479 479 480 481 482 483

xxii LIST OF FIGURES 12.11Example of implications. 483 12.12Another example of implications. 484 12.13Schneider s example. 484 12.14ATPG example. 485 12.15Decision tree for the example of Figure 12.14. 486 12.16Example of backtrace. 487 12.17A redundant circuit. 489 12.18Irredundant circuit derived from the one of Figure 12.17. 489 12.19Circuit with multiple redundancies that cannot be simultaneously removed. 490 12.20Circuit where the removal of one redundancy exposes another redundancy. 490 12.21Circuit of Figure 12.20 after the removal of the only redundancy. 490 12.22Circuit of Figure 12.21 after the removal of the remaining redundancy. 490 12.23A 2-bit carry-skip adder. 491 12.24Combinational circuit for Problems 1 4. 493 12.25A decision tree for Problem 2. 494 12.26Combinational circuit for Problems 5 9. 495 12.27A decision tree for Problem 5. 495 12.28Circuit for Problem 6. 495 12.29Circuit for Problem 8. 496 12.30Decision tree for Problem 8. 496 12.31Circuit of Figure 12.26 after removal of one redundancy. 497 12.32Circuit of Figure 12.31 after removal of one redundancy (top) and after further removal of the inverter pair (bottom). 497 12.33Circuit for Problem 10. 497 12.34Circuit for Problem 11. 498 12.35Circuit of Figure 12.34 after removal of input of Gate 2 connected to stuck-at-1. 12.36Circuit of Figure 12.34 after removal of stuck-at-1. 12.37Circuit of Figure 12.36 after removal of input of Gate 5 connected to stuck-at-0. 499 500 500 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Splitting a DAG into a Forest of Trees. A Subject Tree and its Matches. The Two Possible Patterns for a Four-Input NAND Gate. Two Possible Decompositions of the Same Circuit. Library Patterns for Four-Input NOR and Three-Input OR. Library of Pattern Trees. Best Solution Trace. Final Cover. Modified Library of Pattern Trees. 13.10Best Modified Solution Trace. 13.11Modified Final Cover. 13.12Boolean Network for Problem 3. 13.13Boolean Network for Problems 4 and 5. 510 511 512 513 515 516 517 517 517 518 518 519 519

LIST OF FIGURES xxiii A.1 Table of ASCII Codes. 523 B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 Boolean Network for Problem 13. Boolean Network for Problem 14. Boolean Network for Problem 15. Boolean Network for Problem 16. Circuit for Problem 17. Circuit for Problem 18. Circuit for Problem 19. Circuit for Problem 20. Circuit for Problem 21. 527 528 528 529 529 530 530 531 532

List of Tables 1.1 1.2 1.3 1.4 Data trace for Procedure LONGEST_PATH 30 Comparative growth of log, polynomial, polylog, and exponential functions 37 Computing times on a 10MIP s computer, assuming unit coefficients for each complexity function 37 Data trace for Procedure LONGEST_PATH, applied to Figure 1.7. 45 3.1 3.2 7.1 7.2 7.3 7.4 Mapping of a simple function Mapping of a two Boolean formulae representing the same Boolean function Partial data trace for Procedure SHORTEST_PATH, applied to the graph of Figure 7.31 The mapping for a deterministic FST with initial state A The mapping for a nondeterministic FST with initial state A Data trace for procedure shortest_path 85 96 288 294 294 324 10.1 10.2 Cube Intersection Table. Extended Cube Intersection Table. 427 428

Preface

xxviii Genesis of the Book This book grew from courses taught at the University of Colorado (Boulder) and at the Universidad Politecnica de Madrid, Spain. As the title suggests, we were motivated by two disparate objectives. First, the VLSI CAD group at Boulder was given the responsibility for teaching a course which satisfied the ABET requirement for an upper division algorithms and discrete mathematics course in a EE or ECE curriculum. Hence we started looking for an appropriate book, and taught trial courses from various books including [241], [162], and [190]. While each of these books had their individual strengths, there were always significant areas that were neglected. Second, logic synthesis has matured as a field to the point of almost universal designer acceptance and is used in every major IC design/production house worldwide. Further, the younger field of formal verification, perhaps spurred on by the infamous Pentium bug, appears to be following a trajectory very much like that taken by logic synthesis over the last decade. Consequently, we wanted an orderly integration of modern developments in logic synthesis and formal verification, into the traditional subject matter of Switching and Finite Automata Theory. This clearly eliminated texts like [241], [190], and [146]. The book that came closest to our requirements was Kohavi s book [162]. Although this text was excellent and long lived, it is now outdated, since it does not deal many modern developments in discrete mathematics that were significant to bringing VLSI CAD to its current advanced state. Thus we decided to occupy the niche previously filled by the Kohavi book [162] and supplement the coverage with recent theoretical developments most significant to the emergence of automatic synthesis and verification tools during the nineties. As an example of the aforementioned integration, consider the problem of formally verifying that two distinct FSMs are or are not equivalent. The solution of this problem for problems of practical size was due to the efforts of Coudert, Madre, and McMillan [70, 194]. The solution rested on ingenious interweaving of BDDs (Binary Decision Diagrams) and the state equivalence theory covered in [162]. Boolean function manipulation using BDDs evolved from the work of Bryant in 1986 [47], and is not covered in previous comparable textbooks. Other examples of recent theoretical advances which had profound effects on the development of automatic synthesis tools are : 1. 2. 3. 4. Complexity theory and the development of optimal complexity algorithms like Tarjan s strong components algorithm; The unate recursive paradigm, and its various applications in the industry standard ESPRESSO program for logic minimization [37, 39, 250]; Branch and bound algorithms with lower bound pruning that has proved to be exceptionally powerful for such disparate logic synthesis applications as twolevel logic minimization and state minimization of Finite State Machines [228]; The Kerneling theory of Brayton and McMullen, [38], which led to efficient and widely adopted algebraic methods for restructuring a circuit so minimization techniques could be more powerfully applied;

Preface xxix 5. 6. 7. The PODEM algorithm for automatic test pattern generation, [116], and the learning/implication heuristic used to make it widely applicable, [122]; The development and deployment of the theory of don t care conditions, [15], [204]; The deployment of BDD-based symbolic processing as discussed above along with modified ATPG techniques which made sequential synthesis and ATPG practical for large circuits, [63]; It was very difficult for a VLSI CAD group to teach switching theory without covering these subjects. Consequently, we wanted a book which met ABET requirements and had the above developments woven into the fabric of the theory. Equally important was the emergence over the last decade of widely applicable public domain logic synthesis and verification tools, such as ESPRESSO, MIS, SIS, VIS, SMV, BOLD, as well as commercial tools such as SYNOPSIS design compiler, The CADENCE, VIEWLOGIC, IBM (BOOLEDOZER) and MENTOR synthesis tool suites, and Lucent (FormalCheck) and IBM (RULEBASED) verification packages. Many of the solved and unsolved (an answer book is available) problems are based on using easily available tools. All tools used in the book can be obtained from anonymous FTP from the following web sites: IC.berkeley.edu, vlsi.colorado.edu. Also available from the latter site is a link to the NABLE (Network-enabled Action Based Learning Environment) suite of Java applets, which implements and animates many of algorithms discussed in this book. Among those treated are, minimization of boolean functions with K-maps, the binate covering problem, FSM equivalence checking, and Algebraic Factorization. More algorithms will be added on a yearly basis. Thus we wanted the book to reflect the concurrent evolution of switching and automata theory, and of VLSI Logic Synthesis and Verification, over the last decade, while also providing the necessary background in Boolean algebras and discrete mathematics. Our objective from the onset was a senior course, with enough depth to be of interest to first year graduate students as well. It is quite likely that any student who takes a job in the still burgeoning (at publication time INTEL was still planning two $1B fabrication sites) semiconductor industry will use one or more of these tools. Some students may eventually be involved in the design of the tools themselves. A persistent focus of the book is hands-on relation of actual design tools to the theoretical material. Whenever possible, the algorithms covered in the text are the subject of one or more problems based on the use of available synthesis programs. An appendix describes the details of the installation and use of the software at our institution. Problems. The book contains a large collection of solved problems. This is because we generate new homework problems every semester, as part of the development of

xxx Preface the course. We also have another equally large collection of solved problems which will go into the Instructor s Manual. We plan to maintain this manual in the Colorado web site quoted above. Thus it should continue to grow over the years as a resource for all users of the book. Many solved problems require the use of software tools. Much of the assigned work involves the use of Berkeley s sequential/combinational synthesis program SIS- 1.2 [250] and Berkeley-CU-UT formal verification program VIS Whenever possible, the algorithms covered in the text are the subject of one or more problems based on the use of synthesis or verification programs. Itineraries It would be difficult for undergraduates at most institutions to cover the entire book in one semester. We describe here some sample itineraries for efficaciously traversing the book. The Logic Design Option skips Chapters 6-9, and possibly 3 (our experience is that students find this chapter appealing). The Algorithms and Discrete Mathematics Option skips Chapter 2, 5, 8, 12, and 13. Finally, the graduate Introduction to Synthesis and Verification Option takes well prepared and motivated graduate students through the whole text. Convention When theorems have obvious proofs, or are well known theorems from the literature whose proofs are outside the scope of the present text, we omit the proof. In the latter case we give a citation in which the proof may be found. Notation

Preface xxxi Pseudo-Code Conventions We shall adopt the following further notation for pseudo-code description of algorithms and formal procedures. The beginning and end of the statement blocks of procedures, or if or else blocks, or of for, foreach, while, or other loop or branching structures are denoted by matching braces, as in the C/C++ programming languages. Comments are either denoted by /* */ as in C, or are set to the far right of pseudo-code statements without such delimiters when the context is clear. Semicolons will be used as statement separators only generally they are omitted at the end of a line of pseudo-code.

xxxii Preface Acknowledgments We acknowledge the impact of a career s worth of association with Bob Brayton. We acknowledge the impact of a previous book-experience with Bob Brayton, Alberto Sangiovanni-Vincentelli, and Curt McMullen, and of an aborted (so far) book attempt with Bob, Alberto, and Rick Rudell (Rick McGeer may yet save that book). In both of these former endeavors, Carl Harris is to be recognized for his gentle, enlightened, and persistent persuasion. The help of John Hayes was valuable in giving us early feedback on book direction. We acknowledge the many contributions of University of Colorado students and associates, whose work is featured in this book to name just a few: Karen Bartlett, Chris Morrison, Reily Jacoby, Hyunwoo Cho, Sehwoong Jeong, June Rho. In-Ho Moon helped by proofing several chapters of the last draft. We are also indebted in this regard to many other colleagues and friends among others, Richard Newton, Srinivas Devadas, Kurt Keutzer, Aart DeGeus, Randy Bryant, Louise Trevillyan, and Giovanni DeMicheli were particularly impactful. We acknowledge the impact of numerous summer seminars, first at IBM Yorktown, and then rotating between Boulder, Berkeley, and Stanford. The indefatigable help of our administrative assistants Helen Frey, Karen Schneider, and Ruth Major must also be acknowledged. Penultimately, we acknowledge the support (over the last decade) of the National Science Foundation, in particular that of our friend and mentor, Bob Grafton, who helped us see the dawning of a new era in the advent of Computer Aided Verification. Finally, we acknowledge the patience and appetite for learning shown by our undergraduate students in enduring some very rough drafts.