Tools zur Op+mierung eingebe2eter Mul+core- Systeme Bernhard Bauer
Agenda Mo+va+on So.ware Engineering & Mul5core Think Parallel Models Added Value Tooling Quo Vadis?
The Mul5core Era Moore s Law: The number of transistors on integrated circuits doubles approximately every two years.
The Mul5core Era Moore s Law: The number of transistors on integrated circuits doubles approximately every two years. However
The Mul5core Era SuKer, 2005: The free lunch is over & more performance is in demand! Paralleliza5on: Par55oning Synchroniza5on Todays So.ware? Risks: decreasing quality (complexity) much synchroniza5on overhead side effects (emergence) Think Parallel
Granularity & Par55oning How to find an appropriate granularity together with a par55oning strategy that splits the system up into parts that are as independent as possible? fork join
Timing and Scheduling Division of tasks in smaller sub- tasks (with equal execu5on 5me) Sub- tasks get a pseudo- deadline, overlapping- bit and group- deadline, depending on the task- weight Sub- tasks are scheduled by these proper5es Adapted from WEMUCS Tutorial @ ESE 2014
Synchroniza5on How to handle the necessitated synchroniza5on including the reduc5on of exchanged data as well as the detec5on and resolving of conflicts? Aspects: dependency types how & when to include? new problems:» fine- grained synchroniza5on - expensive» side effects: data races, dead locks, priority inversion» automa5on impossible» avoidance fork join
Agenda Mo5va5on So;ware Engineering & Mul+core Think Parallel Models Added Value Tooling Quo Vadis?
SW- Migra5on So.ware Methodologies for distributed systems Sequen5al Program Decomposi5on RE RE RE RE RE RE RE RE RE RE RE Assignment Task Task Task Task Orchestra5on Task Task Task Task Mapping Core Core Core Core Decomposi5on Iden5fy concurrency and decide at what level to exploit it Break up computa5on into REs to be divided among processes REs may become available dynamically Number of REs may vary with 5me Enough REs to keep processors busy Number of REs available at a 5me is upper bound on achievable speedup Assignment (Granularity) Specify mechanism to divide work among core» Balance work and reduce communica5on Structured approaches usually work well» Code inspec5on or understanding of applica5on As programmers, we worry about par55oning first» Independent of architecture or programming model» But complexity o.en affect decisions! Orchestra5on and Mapping (Locality) Computa5on and communica5on concurrency Preserve locality of data Schedule REs to sa5sfy dependences early
Design Examples Decomposi5on Goal: Parallelism on high level of abstraction Could be derived from exis5ng SW? <<algorithm>> Compute Speed Adjustement func1() {.... } func2() {.... } func3() {.... }
Design Examples Decomposi5on and Assignment Task and Data Partitioning Grouping of Tasks with high communication etc. «algorithm>» Compute Speed Adjustement Task 2 Task 3 calculate Task 1 Task 4 «entity» DesiredSpeed & CurrentSpeed Partition 1 «algorithm» Compute Speed Adjustement Task 2 calculate Task 1 Task 3 Task 4 «entity» DesiredSpeed & CurrentSpeed Partition 1 Task 5 Task 6 Task 7 Task 8 Partition 2 Task 5 Task 6 Task 7 Task 8 Partition 2 Task 9 Task 10 Partition 3 Task 9 Task 10 Partition 3 outputthrottlevalue outputthrottlevalue
Design Examples Orchestra5on calculate Nur Lesend Lesend und Schreibend Datenlokalität <<algorithm>> Compute Speed Adjustement Task 1 Taskgruppe B <<entity>> DesiredSpeed and CurrentSpeed Partition 1 Taskgruppe A Task 2 Task 3 Task 4 Partition 2 Task 5 Task 6 Task 7 Taskgruppe C Task 8 Partition 3 Task 9 Task 10 outputthrottle Value
Agenda Mo5va5on So.ware Engineering & Mul5core Think Parallel Models Added Value Tooling Quo Vadis?
Use Case AUTOSAR (image from http://www.autosar.org/about/technical-overview/)
Tool Chain AUTOSAR Modell Tracing Trace- Informa5on OT 1 Voranalysis AUTOSAR Par55oning DDA Deployment Tasks & Scheduling TA Tool Suite
DDA- Tool 15. Januar 2015 17
DDA- Tool
DDA- Tool
DDA- Tool - Par55oning
DDA- Tool: Filter and Metrics
DDA- Tool: Conflict resolu5on
DDA- Tool: Real World Case Study
DDA- Tool: Real World Case Study
HW/SW Co- Simula5on TA Tool Suite HW/SW Co-Simulation Stimulation / Sampling HW/SW Co-Simulation Application SW Operating System Middleware Processor Event-Trace Evaluation
Deployment Approach - Execu5on Runnable Task Mapping Task Core Mapping OS Configuration R1 R3 R2 R4 R11 P(10) R6 R9 R8 R13 R12 P(8) P(5) R5 R10 R7 P(4) Synchronization Placement Core 1 Core 2 Core 3 P(3) Execution Sequence Improvement LM 1 LM 2 LM 3 P(3) R8 R9 R10 Bus / Crossbar P(1) R8 R10 R9 R8 R10 R9 SM Flash R10 R8 R9
Overview of 5ming analysis techniques 25.11.15
Overview of 5ming analysis techniques Pure model based techniques Simulation based techniques Observation of the real world 25.11.15
Agenda Mo5va5on So.ware Engineering & Mul5core Think Parallel Models Added Value Tooling Quo Vadis?
Con5nuous Development & Op5miza5on Analysis Design Adapted from AMALTHEA
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