EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09

EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09 Lab Description Today s lab will introduce you to the Xilinx Integrated Software Environment (ISE) and the Virtex-4, ML40X Eval Board. You will need to access the course website for the design files for today s lab. There is no pre-lab today. The intent of this lab is to have you walk through prototyping a VHDL design on a Virtex-4 FPGA. You will be provided with a 4-bit, Up/Down counter that was designed in VHDL. You will first verify its functionality using ModelSim. You will then implement the design on a Virtex-4 FPGA using Xilinx ISE and download it to the ML40X Eval Board. The counter will be visible on the LED s of the Eval board. You will be able to change the direction of the counter by pressing the GPIO_SW_S button and also reset the counter using the CPU Reset switch. Part 1 Simulate the Design Using ModelSim 1. Create a folder for today s lab on your drive called Lab_01_Introduction with a subfolder called ModelSim. 2. Download the four VHDL design files from the course website into your folder: - http://www.coe.montana.edu/ee/rosss/courses/ee367_spring_2009/ee367_labs.html (or go to my homepage at http://www.coe.montana.edu/ee/rosss and click on the EE367 link on the right). - Download files top.vhd, counter.vhd, clock_div.vhd, & test_top.vhd into your ModelSim directory. 3. Start ModelSim - Start Programs ModelSim XE III 6.2c ModelSim 4. Start a new ModelSim Project - File New Project - Give a Project Name such as 4bit_counter - Browse to your /Lab_01_Introduction/ModelSim folder - leave the library name work - Click OK - a dialog will appear in order to add files to the project - Click on Add Existing File - Click Browse - Highlight the four.vhd files that you just downloaded and click OK - Click Open - Click OK - Close the Add items dialog 5. Inspect/Edit the VHDL files - Click on the Project tab (bottom left in the left middle window) - highlight the counter.vhd file, Right Click, and select Edit - inspect the file and see if it makes sense? - highlight the clock_div.vhd file, Right Click and select Edit - inspect the file to see what it does? - what is the DIVISOR set to? 1

- when we download this design onto the FPGA, we will need to change the divider to slow the clock down to <1HZ. What do you think we should set n to if the input clock is 100MHz? - highlight the top.vhd file, Right Click, and select Edit - this is the TOP level design module and calls and connects counter and clock_div. - highlight the test_top.vhd file, Right Click, and select Edit - this is the TEST BENCH for this design. This file calls the Unit Under Test (UUT), provides stimulus to the inputs, and observes the outputs. 6. Compile the VHDL files - Click on the Project tab (bottom left, probably still on top) - Right click in the Workspace and select Compile Compile All - If the compile is successful, a green check will appear by the file. If there was an error, a Red X will appear. You can double click on the Red X to see the error messages. - You can experiment with errors by altering a letter or two in one of the VHDL files. Just remember to put it back to its original form before simulation. 7. Simulate the Design - Click on the Library tab (bottom left) - Our source files were compiled into the work library. - Expand the work library by clicking on its + - Double Click on test_top to load it into the simulator as the Top Level Testbench - A new tab will appear in the Workspace called sim - With test_top highlighted, place the mouse over it and Right Click. - Select Add Add to Wave - Change the Simulation Run Length from 100ps to 2us by typing 2us into the Run Length dialog at the top of the window. - Click the Run button (the button immediately to the right of the Run Length dialog) 8. Inspect the Waveforms - Zoom out Full by clicking once in the waveform window and typing f - Change the Radix of count_tb by Highlighting it, Right Clicking, and selecting Radix Unsigned - You can zoom in and out using the + and - magnifying buttons. - Verify that the counter looks OK to you? Does it change directions and reset properly? Demo #1 : Show the lab instructor the counter waveforms in ModelSim and have the verification sheet signed off (see last page). You should be able to easily zoom in and out on portions of the simulation. 9. Close ModelSim - You must quit the simulation before you can close the project. Click in the bottom command window and type quit sim - Click on the Project tab - Right click in the Workspace window and select Close Project, select OK on the confirmation dialog. - Close the ModelSim program. You have now simulated and verified the functionality of this counter design. Now we are going to Implement the design using an FPGA and verify its operation in hardware. 2

Part 2 Implement the Design on a Xilinx Virtex-4 FPGA 1. Create a sub folder under Lab_01_Introduction called Xilinx 2. Start Xilinx ISE - Start Programs Xilinx ISE 9.1i Project Navigator 3. Start a new project - File New Project - In the New Project Wizard, enter the following: - Under Project Name, enter 4bit_counter - Under Project Location, browse to your Lab_01_Introduction\Xilinx subfolder - Under Top-Level Source Type, select HDL - Click Next - Fill in the following Device Properties : - Product Category = All - Family = Virtex4 - Device = XC4VFX12 - Package = FF668 - Speed = -10 - Synthesis Tool = XST (VHDL/Verilog) - Simulator = ISE Simulator (VHDL/Verilog) - Preferred Language = VHDL - Check the box for Enable Enhanced Design Summary NOTE : If you look at the top of the FPGA, you will see the device properties printed on the top Eval Board. - Click Next - We are NOT going to create a new source, we are going to add existing sources - Click Next on the Create New Source window - In the Add Existing Sources window, click Add Source - Browse to your Lab_01_Introduction/ModelSim directory - Highlight the top.vhd, counter.vhd, and clock_div.vhd files (DO NOT SELECT test_top.vhd). - Click Open - Ensure that the Copy to Project boxes are checked. This is going to copy our VHDL files from our ModelSim project directory into our Xilinx project directory. We can now edit the source code in the Xilinx environment if we need to make small adjustments to the design (i.e., changing the clock divider) without altering our original VHDL source. You can immediately see that you need to be very careful about keeping track of where files are and what revision they are at. - Click Next - A Project Summary window appears to let you confirm your selections. - Go through the information and make sure it looks like what you wanted. - Click Finish - A window will appear that lets you declare what you are going to do with your source files. You can choose to Simulate Only, Synthesis/Implement Only, or do both. We will do both. - Make sure that Synthesis/Imp + Simulation is chosen for each of the three design files under Association - Click OK 3

4. Check the Syntax of the Designs - Verify that Synthesis/Implementation is selected from the drop-down list in the Sources window. - Select the Top design source in the Sources window - In the Processes portion of ISE, click the + next to the Synthesize-XST process to expand the group. - Double Click on the Check Syntax process to start it. - You will see the status of what ISE is doing in the bottom console. You should see that the Check Syntax process completed successfully. NOTE: If you have ERRORS, the tool will not allow you to go any further. The reason is that Xilinx ISE is going to convert your VHDL into real hardware so you do not want errors! 5. Edit the Source Code We know the design is functionality correct. Now we want to slow the clock divider circuit to the point where a human eye can see the counter on the Eval Board LEDs. Unfortunately we can t simulate this situation because it takes way to long (100MHz / 1 HZ = 100 Million clocks for each count on the LED). We will change the DIVISOR in the source code and re-check the syntax, but we will not re-simulate. - In the Sources section of ISE, you will see your project, device, and what designs are targeted for that device. ISE automatically figures out the hierarchy of the design (i.e., that TOP is the top level in our design). - Click on the + sign next to TOP to see the two lower level components (counter and clock_div) - Double Click on D1 clock_div to open the source. - The VHDL source will appear in the right hand window. - Change the value of n generic from 2 to 25. This will give us a clock frequency of <1 Hz going into our counter. This will be slow enough that a human can see the count on the Eval Board LEDs. - Save the File - Recheck the Syntax of the Design by Highlighting the TOP source in the Sources window and double clicking on Check Syntax in the Processes window. 6. Assign Package Pins We need to tell ISE how we want the signals in our design mapped to the pins of the FPGA. This information is kept in a Constraints File. On the course website, there is a document titled ML40X User s Guide which has the pinout of all of the useful I/O on the FPGA (i.e., LEDS, switches, etc ). This is where we find the pinouts to enter into ISE. - In the Processes section, click the + next to the User Constraints process to expand it - Double Click the Assign Package Pins process. - Click Yes if it asks you if it is ok to create a UCF file. This will bring up a new windows titled PACE. This shows a graphical representation of what devices we are using inside the FPGA and also what pins on the package we are assigning to. - Click on the Package View tab to look at the Virtex-4 FF668 package. As we assign package locations to our signal nets, the pins will be highlighted in the package graphic. 4

- In the Design Object List, the I/O signals are listed for our design. Assign the LOC as follows: - Clock = AE14 (100MHZ oscillator on the Eval Board) - Count_Out<0> = G5 (GPIO LED s on the Eval Board) - Count_Out<1> = G6 - Count_Out<2> = A11 - Count_Out<3> = A12 - Direction = A6 (Push Button South on the Eval Board) - Reset = D6 (CPU Reset Button on the Eval Board) Notice how as you enter a package location it is highlighted in the graphic. - Save and Close the PACE window. (If prompted for a Bus Delimiter, choose VHDL, and Do Not Prompt Again ). 7. Verify the Constraints - In the Processes section, click the + next to the User Constraints process to expand it - Double Click the Edit Constraints (Text) process. This brings up a text version of the constraints you ve entered. You should see the package pin constraints that you entered using the graphical input dialogs. Verify that everything is present. Notice some of the other constraints that are available. - Close the Text UCF file. 8. Implement the Design We are now ready to map our design into the FPGA. - In the Processes section, Double Click on the Implement Design process. This process will take some time while the design is synthesized, mapped, placed and routed into the FPGA. There will be some timing warnings that you can ignore for now. Once completed, we have a design that is implemented in real Hardware (i.e., gates in the FPGA). Since we have the timing information about the gates being used, we can re-simulate the design with actual timing data to see if it meets spec (later ) 9. View Report of Implementation - In the processes window, Double Click on the View Design Summary process. This will bring up a window with all of the information about the hardware used to create the design. - Things to notice: - What is our utilization? - Click on some of the report links to see how they appear? - Close the Design Summary 5

10. Generate Programming File for the FPGA and Program At this time, you can connect the USB cable and power up the ML40X Eval Board. - In the Processes section, click the + next to the Generate Programming File process to expand it - Double Click the Configure Device (impact) process. The Configure Device process creates a TOP.bit file for the FPGA that can be downloaded. It will also bring up the downloading tool impact. If prompted with a web talk dialog, choose later or Decline. send In the impact Welcome Dialog : - Make sure the Configure devices using Boundary-Scan (JTAG) is selected. - Make sure the pull down dialog has Automatically connect to a cable. - Click Finish The impact tool goes out and communicates with the Eval Board. It will graphically show the programmable devices that it has found in its programming chain. Our Eval Board has 4 devices. We only care about the Virtex-4 FPGA. For each device in the programming chain, it will ask for a programming file. If we are not going to program a device, we will click Bypass. If we are going to program a device, we will choose a programming file (i.e., TOP.bit). - Click Bypass for the 1st device (xccace) - Click Bypass for the 2nd device (xcf32p) - Select top.bit for the 3 rd device (xc4vfx12 = our FPGA), click open, - click OK in the Object window. - click OK in the Warning window that says the Startup Clock has been changed to JTAG. - Click Bypass for the 4 th device - Put your mouse over the Virtex-4 FPGA icon, Right Click, and select Program - Click OK on the Program Properties window. You will see a status bar indicating that the device is programming. Once complete, the FPGA will begin operating. If you save the impact file, it will save the configuration of the programming chain so that the next time you program the FPGA, you will not have to choose Bypass and can go directly to programming the Virtex-4 11. Verify Hardware Operation - The Eval Board should have a binary counter running on the GPIO LEDs. - You should be able to change the direction of the counter by pressing and holding the GPIO_SW_S button. - You should be able to reset the counter by pressing the CPU Reset button Demo #2 : Show the lab instructor the counter operating on the Eval Board and have the verification sheet signed off (see last page). 6

Instructor Verification Sheet Staple this page to the end of you Lab Report. EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Name : Partner : Section: Date: Demo #1 : Counter waveforms shown in ModelSim. Verified : Demo #2 Counter operating on the ML403 eval board. Verified : 7