ISSN 2319-8885 Vol.03,Issue.32 October-2014, Pages:6436-6440 www.ijsetr.com Design and Modeling of Arithmetic and Logical Unit with the Platform of VLSI N. AMRUTHA BINDU 1, M. SAILAJA 2 1 Dept of ECE, UCEK, JNTUK, Kakinada, Anshrapradesh, India, E-mail: amruthabindu.n@gmail.com. 2 Dept of ECE, UCEK, JNTUK, Kakinada, Andhrapradesh, India. Abstract: ALU is used to perform both arithmetic and logical operations. The arithmetic logic unit (ALU) is the core of a CPU in a computer. The adder cell is the elementary unit of an ALU. The constraints the adder has to satisfy the area, power and speed requirements. Full adder is the vital part of digital circuits employing arithmetic operation and this also basic building block like ALU, CPU etc. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also adder for address generation in processors and microcontrollers. Here describes full adder circuits to make it more reliable to be used with high speed system and using this building block full adder, we are going to design and model the ALU which is core for CPU which place vital role in high speed systems. Here we are going to design two types of ALU s in which one of it can be designed using Back-end implementation that is through gate level implementation and other can be designed using Front-end implementation that is through a soft core processor (Micro Blaze Processor) with the help of serial interface. A soft core processor is used to handle the operations in ALU by using select inputs with the help of serial peripheral interface. Keywords: Soft Core Processor, Arithmetic and Logical Unit, Back End Implementation and Front End Implementation. I. INTRODUCTION The full adder circuit adds three one-bit binary numbers (C in, A, B) and outputs two one-bit binary numbers, a sum (SUM) and a carry (COUT). Due to the important role played by Full adder in various arithmetic units, optimized design of Full adder to achieve low power, small size and delay is needed. The primary concern to design Full adder is to obtain low power consumption and delay in critical path and full output swing with low number of transistors to implement it. The micro processors available for use in Xilinx FPGA s with Xilinx EDK software tools can be broken down into Soft core microprocessors (Micro Blaze) and Hard core micro processors (Power PC). The Micro Blaze is a virtual microprocessor that is built by combining blocks of code called cores inside a Xilinx FPGA. In this paper, we propose an ALU design using Full adder and by using Soft core processor. The soft core processor is used to control the serial peripheral interface to handle the operations in ALU. Here using UART as the serial peripheral. A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the reception and transmission of information, in a serial and asynchronous way. II. ALU DESIGN USING SIMULINK The performance of many applications such as digital signal processing depends upon the performance of the arithmetic circuits. Fast arithmetic computation cells including adders and multipliers are the most frequently and widely used circuits in very-large-scale integration (VLSI) systems. This chapter explains in detail the 2-bit ALU design. All of the multiplexers and full adder have been implemented using logic gates. The ALU implementation must be depends on the select inputs which are to be given for multiplexer is as shown in Fig.1. Suppose if the select inputs are one bit (S 0 ) then the ALU perform two operations, similarly if the select inputs are two (S 1 and S 0 ) then it performs four operations. Fig.1. 1-bit ALU with adder, AND and OR operations. Truth table design is the efficient method compiling all those functions that are needed. Following table indicates the combination of 4 control input bits with their respective operation to be performed for the corresponding function to be implemented. Copyright @ 2014 IJSETR. All rights reserved.
N.AMRUTHA BINDU, M.SAILAJA TABLE I: Truth Table for 2 bit ALU Hence, we can add two bits together taking a carry from the next lower order of magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit blocks. Hence, the two bit full adder can be implemented using Matlab-Simulink as shown as below Fig.4. A basic Full adder cell in digital computing systems is the 1-bit full adder which has three 1-bit inputs (A, B, and Cin) and two 1-bit outputs (sum and carry) is as shown in Fig.2. The relations between the inputs and the outputs are expressed as: (1) (2) Fig.4. A Full adder design using simulink. Also to design subtraction, multiplication and complement blocks like this. A Multiplexer can use addressing bits to select one of several input bits to be the output. A 4X1 multiplexer uses two control signals S0 and S1 to connect one of the four input data lines IN1, IN2, IN3 and IN4 to a single output F. The pictorial view of 4X1 multiplexer and the corresponding truth table are show in below Fig.5. Fig.2. A Conventional full adder. The gate level implementation of full adder is shown below Fig.3. Fig.3. A Gate level full adder. Fig.5. A 4:1 MUX. Hence we have to implement the 2-bit ALU with adder, subtractor, multiplier and complement operations in simulink as shown below Fig.6.
Design and Modeling of Arithmetic and Logical Unit with the Platform of VLSI Fig.6. A 2-bit ALU design using simulink. III. ALU DESIGN USING SOFT CORE PROCESSOR ALU is used to perform both arithmetic and logical operations and is the core for CPU. Here we have to implement a ALU using soft core processor (MicroBlaze) with the help of serial peripheral interface. Here the 4-bit ALU is designed and implemented by using the behavioral model to describe how the operation of ALU is being processed. This is accomplished by using VHDL (Very High Speed Integrated Circuits Hardware Description Language) in Xilinx platform. The ALU implementation can be done by three modules. They are Processor implementation to interface with UART. ALU design. A. Processor implementation In this the MicroBlaze soft core processor can be developed depends on data handling manipulations, that is to handle the serial peripheral interface (UART) and to accessing the operations in the ALU. SPI (Serial Peripheral Interface) bus, which is commonly used for communication between integrated circuits or sensors. SPI is a synchronous serial data link that operates in full duplex. Devices communicate using a master/slave protocol (shown in Fig.4), in which the master starts the data frame. When the master generates a clock then selects a slave device, data may be transferred in either or both directions simultaneously.
N.AMRUTHA BINDU, M.SAILAJA that are needed. Following table indicates the combination of 4 control input bits with their respective operation to be performed for the corresponding function to be implemented. Truth table shows the list of 15 arithmetic and logical operations performed in this design. TABLE II: Truth Table for 4 bit ALU Fig.7. Block diagram of MicroBlaze processor to interface with UART. The above Fig.7 is the soft core processor implementation to interface with serial peripheral UART(Universl Asynchonous Receiver and Transmitter). The UART is used to control the registers and is handled by the processor. The below fig.8 shows the bus interfaces of MicroBlaze processor. IV. RTL SCHEMATIC DIAGRAM OF ALU This is a schematic representation of an NGC file shown in terms of logic elements optimized to the target architecture or "technology," for example, in terms of LUTs, carry logic, I/O buffers, and other technology-specific components. It is generated after the optimization and technology targeting phase of the synthesis process. Viewing this schematic allows you to see a technology-level representation of your HDL optimized for a specific Xilinx architecture, which may help you discover design issues early in the design process is as shown in Fig.9. Fig.8. Bus Interfaces of MB. Fig.8 shows bus interfaces of Micro Blaze processor. A PLB (Processor Local Bus) connects the UART. B. ALU Design ALU is capable of calculating a wide variety of basic arithmetic and logical computations and some shift operations including rotate operations. The ALU takes as input the data to be operated on (called operands) and a code from the control unit indicating which operation to perform. The output is the result of the computation. The ALU designed will perform some of the arithmetic and logical operations of the various available operations. Truth table design is the efficient method compiling all those functions Fig.9. RTL schematic of ALU. V. RESULTS Design simulation involves testing your design using software models. It is most effective when testing the functionality of your design and its performance under worstcase conditions. Simulation is performed using Xilinx or third-party tools that are linked to the Xilinx Development System. The software models provided for your simulation tools are designed to perform detailed characterization of your design. You can perform functional or timing simulation is as shown in Fig.10.
Design and Modeling of Arithmetic and Logical Unit with the Platform of VLSI Fig.10. Simulation Result of 4 bit ALU. VI. CONCLUSION The 2 bit Arithmetic and Logical Unit can be design through Back end implementation and the Front end implementation of a 4 bit Arithmetic and Logical Unit can be designed through a Soft Core Processor implementation. VII. REFERENCES [1] A Text book Modern VLSI Design 4 th edition by Wayne Wolf. [2] XILINX Spartan User Manual. [3] Xilinx Incorporated Website, www.xilinx.com, June 2006. [4] MicroBlaze Processor Reference Guide, Xilinx Corporation, October5, 2011.