Data Sheet. Tranma Alphanumeric dot matrix liquid crystal displays with backlighting ATTENTION

Data Pack F Issued September 2001 287-0536 Data Sheet Tranma Alphanumeric dot matrix liquid crystal displays with backlighting LED type - stock numbers 184-8538, 184-8544 184-8572, 184-8825, 184-8847 Intelligent, alphanumeric, dot matrix modules with integral CMOS controller and driver ICs. The modules utilise a 5 x 7 dot matrix format with cursor and are capable of displaying 160 different alphanumeric characters and symbols. The modules have LED back lighting. Applications Word processing equipment Electronic typewriters Medical instruments Point of sale terminals Test instruments Data terminals. Features High contrast and a wide viewing angle Compact and lightweight LED backlighting CMOS controller and driver ICs Interfaces to 4 or 8-bit MPU. ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES Absolute maximum ratings VSS = OT, Ta = 25 C Parameter Symbol Min. Max. Unit Logic circuit power supply voltage VDD - VSS 0 7.0 V LC driver circuit supply voltage VDD - VEE 0 13.5 V Input voltage V1 VSS VDD V Operating temp. Top 0 +50 C Storage temp. Tstg -20 +60 C Electrical characteristics 1 line module VDD = 5.0V ± 0.25V, Ta = 25 C Parameter Symbol Test condition Min Typ. Max. Unit Input High voltage VIH 2.2 - VDD V Input Low voltage VIL - 0.6 V Output High voltage VOH -IOH = 0.205mA 2.4 - - V Output Low voltage VOL IOL = 1.2mA - - 0.4 V Power supply voltage for Top = 0 C 7.9 8.0 8.1 V LCD (recommended) VDD - VEE Top = 25 C 6.7 6.8 6.9 V ( 1 16 duty) Top = 50 C 5.7 5.8 5.9 V 2 line modules VDD = 5.0V ± 0.25V, Ta = 25 C Parameter Symbol Test condition Min Typ. Max. Unit Input High voltage VIH 2.2 - VCC V Input Low voltage VIL -0.3-0.6 V Output High voltage VOH -IOH = 0.205mA 2.4 - - V Output Low voltage VOL IOL = 1.6mA- - 0.4 - V Ta = 0 C - 4.2 - V Duty = 1 11 Ta = 25 C - 3.8 - V Power supply Ta = 50 C - 3.3 - V for LCD (recommended) VDD-VEE Ta = 0 C - 3.9 - V Duty = 1 8 Ta = 25 C - 3.6 - V Ta = 50 C - 5.2 - V

Power supply current IDD Display type Size Typ. Max. Units STN LED backlit 1 x 16, 2 x 16 0.5 2.0 ma STN LED backlit 2 x 20 1.5 3.0 ma STN LED backlit 2 x 40 2.0 5.0 ma Power supply Figure 1, Single +5V power supply LCD Module V DD V0 + 5V Backlighting characteristics Device Backlight stock no. VF IF (ma) 184-8538 4.2 (typ.) 168 (typ.) 184-8544 4.2 (typ.) 168 (typ.) 184-8572 4.2 (typ.) 168 (typ.) 184-8825 5.0 (max.) 500 (max.) 184-8847 5.0 (max.) 500 (max.) VR V SS 0V VR: 10kΩ ~ 20kΩ VR: Suitable multiturn stock no. 186-536 or stock no. 162-243 Optical characteristics Ta = 25 C Item Symbol Condition Min Typ. Max. Unit Notes Viewing angle area Ø2 - Ø1 K = 1.4 20 - - degree 1,2 Contrast ratio K Ø = 20, 0 = 0 3 - - - 3 Rising time tr Ø = 20, 0 = 0-150 250 ms 4 Falling time tr Ø = 20, 0 = 0-150 250 ms 4 Figure 2, Definitions Note 1. Definition of 0 and Ø Z(Ø=0 ) Ø1 Y' Ø2 X Y(0=0 ) X' Note 3. Definition of contrast ratio K K= 100 Brightness (%) 0 Brightness of non-selection dot (B 2 ) Brightness of selection dot (B 1 ) Brightness curve of selection dot B2 B1 Driving voltage (V) Brightness curve of non-selection dot Note 2. Definition of viewing angles Ø 1 and Ø 2 Contrast ratio K K Ø1<20 < Ø2 1.4 Ø1 20 Ø2 Note 4. Definition of optical response Non-selection state Selection state Off On Off Brightness 100% 90% 10% Viewing angle t r Rising time t f Falling time 2

Figure 3, 16 x 2 110.50 98.0 83.0 15.0 max. 10.48 76.69 4 - Ø2.5 4.6 39.7 35.0 2.5 15.24 14 13 15 11.5 18.6 35.6 2.54 2 1 16 14 - Ø1.0 115.57 1.6 3.25 0.61 6.03 5.63 0.66 0.05 0.61 0.05 stock no. 184-8544 Pin Assignment Pin Assignment 1 V SS 9 DB2 2 VDD 10 DB3 3 V O 11 DB4 4 12 DB5 5 13 DB6 6 E 14 DB7 7 DB0 15 VLED- 8 DB1 16 VLED+ Figure 4, 20 x 2 170.0 153.5 15 max. 8.52 147.5 4 - Ø2.8 4.6 2.5 13 34.54 29.46 15.24 2.54 2 1 11.5 16.5 34.2 14 - Ø1.0 181.1 1.6 186.2 0.65 0.4 5.69 0.07 3.28 0.5 0.6 0.07 stock no. 184-8572 Pin Assignment Pin Assignment 1 V SS 9 DB2 2 VDD 10 DB3 3 V O 11 DB4 4 12 DB5 5 13 DB6 6 E 14 DB7 7 DB0 15 VLED- 8 DB1 16 VLED+ 3

Figure 5, 40 x 2 170.0 153.5 15 max. 8.52 147.5 4 - Ø2.8 4.6 2.5 13 34.54 29.46 15.24 2.54 2 1 11.5 16.5 34.2 14 - Ø1.0 181.1 1.6 186.2 0.65 0.4 5.69 0.07 9.0±0.5 98.0±1.0 2.5±0.5 93.0±0.3 10.0±0.5 2.54 4 - Ø2.5 16 - Ø1.0 1 16 40.0±0.5 8.4±0.5 2.2±0.5 20.8±0.3 25.2±0.3 55.2±0.3 60.0±0.1 3.28 0.5 0.6 0.07 stock no. 184-8572 Pin Assignment Pin Assignment 1 V SS 9 DB2 2 VDD 10 DB3 3 V O 11 DB4 4 12 DB5 5 13 DB6 6 E 14 DB7 7 DB0 15 VLED- 8 DB1 16 VLED+ Figure 6 4 x 20 2.54±0.5 2.5±0.5 15.0 (max.) 5.8 (max.) 2.8±0.5 70.4±0.3 76.0±0.3 11.0±0.5 1.6±0.2 5.35 4.75 0.55 0.6 0.55 2.95 0.6 Stock no. 184-8825 Pin 1 2 3 4 5 6 7 8 Assignment VSS Vdd VO E DB0 DB1 Pin 9 10 11 12 13 14 15 16 Assignment DB1 DB3 DB4 DB5 DB6 DB7 VLED+ VLED- 4

Figure 7 4 x 20 2.5 1 2 4 -R1.0 190.0 183.0 15.0 (max.) 4.6 54.0 47.0 17.78 23.16 29.5 43.1 2.54 15 16 16 -Ø1.0 140.45 147.0 166.6 4 - Ø3.3 1.6 0.55 0.5 2.78 0.07 4.89 1.2 0.07 Stock no. 184-8847 Pin 1 2 3 4 5 6 7 8 9 Assignment DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E1 Pin 10 11 12 13 14 15 16 17 18 Assignment VO VSS Vdd E2 NC VLED+ VLED- Symbol I/O Level Functions VDD - - +5V VSS - - 0V Power supply VO - - Power supply for LC drive Register selection signal L : Instruction register (for write) I H/L flag, address counters (for read) H : Data register (for Write and Read) Register/Write () selection signal I H/L L : Write H : Read H Enabling signal (activates the module H L to write or read data) Lower-order 4-line data bus (bi-directional). Data is transferred between the module and MPU DB0~DB3 I/O H/L through this 4-line data bus. During 4-bit operation, these 4 lines are not used. Higher-order 4-line data bus (bidirectional). Data is transferred DB4~DB7 I/O H/L between the module and MPU through these 4-lines. DB7 can also be used as busy flag Timing characteristics Notes: 1. In order that the module can accommodate both 4-bit and 8-bit MPUs, the data may be sent in either a repeated 3-bit or a single 8-bit operation. 2. When the module is in the 4-bit mode, DB4~DB7 are used for data transfer, DB0~DB3 are not used. A complete data transfer consists of loading the higher order bits of the 8- bit instruction first, followed by the lower order bits. The second transfer completes the sequence. 3. When the interface data is 8 bits wide, data is transferred using all 8 data lines of DB0~DB7. Item Symbol Test condition Min. value Max. value Unit Enable cycle time tcyc fig 2, fig 3 1.0 - µs Enabling pulse width PWEH fig, fig 3 450 - ns Enable rising/falling time ter tef fig, fig 3-25 ns, setup time tas fig 2, fig 3 140 - ns Data delay time tddr fig 3-320 ns Data setup time tdsw fig 2 195 - ns Hold time th (tdhr) fig 2, fig 3 10 (20) - ns 5

Figure 8 Writing operation interface timing (data write) Reading operation interface timing (data read) t AS t H t AS t H RW RW E t Er PW EH t DSW t H t H t Ef E PW EH t 0.06V Er t DDR t H t DHR t Ef DB 0 ~DB 7 Valid date DB 0 ~DB 7 2.4V 0.4V Valid date 2.4V 0.4V t cyc t cyc Instruction set Code Max. execution time Instruction Description DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (fcp or fosc = 250kHz) Clear display 0 0 0 0 0 0 0 0 0 1 Clears entire display and sets cursor to 82µs~1.64ms home position (DD RAM address=0). Sets cursor to home position (DD RAM address= Return home 0 0 0 0 0 0 0 0 1 * 0). Also returns shifted display to original position. 40µs~1.6ms Contents of DD RAM remain unchanged. Sets direction of cursor's movement and Entry mode set 0 0 0 0 0 0 0 1 I/D S determines display shift. These operations are 40µs performed during data Read/Write. Sets on/off of the entire display by D=0 (off) or D= Display ON/OFF 0 0 0 0 0 0 1 D C B 1(on), cursor on/off by C=0 (off) or C=1 (on), and 40µs control the blink section of the cursor position character by B=0 (off) or B=1 (on) Cursor or Moves cursor and shifts display without changing 40µs 0 0 0 0 0 1 S/C R/L * * display shift the contents of DD RAM Function set 0 0 0 0 1 D/L N F * * Sets length of interface data (DL), number of 40µs display lines (L) and character font (F) CG RAM Sets CG RAM address. CG RAM data is sent and 40µs address set 0 0 0 1 A CG received after CG RAM address is set DD RAM Sets DD RAM address. DD RAM data is sent and 40µs address set 0 0 1 A DD received after DD RAM address is sent Read Flag Reads Flag (BF) which indicates that internal 0 1 BF AC and address operations are in progress. Also reads contents of address counter 1µs Write data into 40µs the CG RAM or 1 0 Write Data Writes data into DD RAM or CG RAM the DD RAM Read data from the CG RAM or 1 1 Read Data Reads data from DD RAM or CG RAM 40µs the DD RAM ID=1: Increment (+1) DD RAM: Display data RAM Execution time I/D=0: Decrement ( 1) CG RAM: Character generator RAM dependent on S=1: Acompanies display shift ACG: CG RAM address frequency. When fcp S/C=0: Display shift ADD: DD RAM address. Corresponds to cursor or fosc=270khz, S/C=0: Cursor move address R/L=1: Shift to the right AC: Address counter used for both DD RAM R/L=0: Shift to the left CG RAM addresses 40µsx x 250 =37µs 270 DL=1: 8-bit DL=0: 4-bit N=1: 2 lines N=0: 1 Line F=1: 5 10 dots F=0: 5 7 dots BF=1: Internally operating BF=0: Can accept instruction : (Note): *Don't Care 6

Devices: Stock nos. 184-8538 184-8544 184-8572 184-8825 184-8847 Higher -Order Bits 4 bit Lower- Order Bits 4 bit xxxx0000 xxxx0001 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 CG RAM (1) (2) xxxx0010 (3) xxxx0011 (4) xxxx0100 (5) xxxx0101 (6) xxxx0110 (7) xxxx0111 (8) xxxx1000 (1) xxxx1001 (2) xxxx1010 (3) xxxx1011 (4) xxxx1100 (5) xxxx1101 (6) xxxx1110 (7) xxxx1111 (8) Note: The character patterns are stored in the CG (character generator) RAM. The user can change these patterns freely by reprogramming the CG RAM. 7

Instruction description 1. Clear display DB 7 DB 0 Code 0 0 0 0 0 0 0 0 0 1 Writes hexadecimal space code '20' into all DD RAM addresses. (Pattern for character code '20' must be blank.) Sets DD RAM address in address counter to 0. Returns shifted display to original position, ie. any characters in the display are erased and the cursor (or blinking character) returns to the left edge of the display (to the first line if 2 lines are displayed). 2. Return home DB 7 DB 0 Code 0 0 0 0 0 0 0 0 1 * Sets the DD RAM address in the address counter to 0. Returns shifted display to original position. Contents of DD RAM remain unchanged. Cursor (or blinking character) returns to the left edge of the display (to the first line if 2 lines are displayed). *Don't Care 3. Entry mode set DB 7 DB 0 Code 0 0 0 0 0 0 0 1 I/D S* I/D: Increases (I/D=1) or decreases (I/D=0) the value in the DDRAM address by 1 when a character code is written into or read from the DD RAM. When increased by 1, the cursor or blinking character moves to the right, and when decreased by 1, the cursor or blinking character moves to the left. This also applies to writing into the reading from the CG RAM. S: When S=1, the entire display shifts to either the right or left, depending on the value of I/D. When I/D=1, the display shifts to the left, and when I/D=0, the display shifts to the right. The display appears to move while the cursor remains in one place. The display does not shift while reading data from the DD RAM, nor when writing into or reading out from the CG RAM will it shift when S=0. 4. Display ON/OFF control DB 7 DB 0 Code 0 0 0 0 0 0 1 D C B D: The display is on when D=1 and off when D=0. When the display is off (D=0), the display data remains in the DD RAM, but can be immediately displayed by setting D to 1. C: The cursor is displayed when C=1, but not displayed when C=0. Even when the cursor is not displayed, the function of I/D, etc, will remain unchanged while writing the display data. The cursor consists of 5 dots in either the 8th line (for 5x7-dot character font) or the 11th line (for 5x10-dot character font). B: When B=1, the character indicated by the cursor blinks on and off. The blinking effect is created by switching back and forth between all blank dots and the display character at 409.6 ms intervals (when fcp or fosc=250khz - the blinking interval varies in accordance with the reciprocal of fcp or fosc, eg. 409.6 250 270 + 379.2 ms when fcp = 270kHz The cursor and the blinking character can be made to blink on and off simultaneously. 5 x 8 - dot character font A) example of cursor display Cursor 5 x 7 - dot character font 5. Cursor or display shift Cursor B) example of blinking display Blinking display 5 x 10 - dot character font DB 7 DB 0 Code 0 0 0 0 0 1 S/C R/L * * The position of the cursor or the display is shifted to the right or left without writing or reading the display data. This function is used to correct the display or to search for certain characters or information in the display. In a 2-line display, the cursor moves to the 2nd line when it passes the 40th position in the 1st line. Note that the displays for both the 1st and 2nd lines will shift at the same time. When the displayed data in one line is shifted repeatedly, only that line will move horizontally, ie. the data in the 2nd line will not shift into the 1st line. S/C R/L 0 0 Cursor shifts to the left. (AC decreases by 1) 0 1 Cursor shifts to the right (AC increases by 1) 1 0 Entire display shifts to the left. Cursor shifts with the display 1 1 Entire display shifts to the right. Cursor shifts with the display The contents of the address counter (AC) remain unchanged when only the display is shifted. 6. Function set DB 7 DB 0 Code 0 0 0 0 1 D/L N F * * DL: Sets the length of the interface data (4 bits or 8 bits). When DL=1, data is sent or received in 8-bit lengths (DB 7 ~DB 0 ), and when DL=0, data is sent or received in 4-bit lengths (DB 7 ~DB 4 ). When the data length is set at 4 bits, the data must be sent or received twice. N: Sets the number of display lines. F: Sets the character font. Note: The function should be set at the beginning of the program before any other instruction (except '' flag/address read). 8

No. of Character Duty NF display font factor Remarks lines 00 1 5 x 7-dot 1/8 01 1 5 x 10-dot 1/11 1* 2 5 x 7-dot 1/16 2 lines cannot be displayed when the 5 x 10-dot character font is used *Don't Care 7. Set CG RAM address DB 7 DB 0 Code 0 0 0 1 A A A A A A 8. Set DD RAM address DB 7 DB 0 Code 0 0 1 A A A A A A A Higher order bits Lower order bits Sets the DD RAM address into the address counter as binary AAAAAAA. Data for the DD RAM is then written into or read from the MPU. Note, however, that when N=0 (1-line display), AAAAAAA is written in hexadecimal as a value from '00' to '4F', and when N=1 (2-line display), AAAAAAA is written in hexadecimal as a value from '00' to '27' for the 1st line and as a value from '40' to '67' for the 2nd line. 9. Read '' flag and address DB 7 DB 0 Code 0 1 BF A A A A A A A Higher order bits Lower order bits Reads the Flag which indicates that the system is currently operating under a previous instruction. When BF=1, an internal operation is in progress and the next instruction will not be accepted until BF is set to 0. Check the value of BF before starting the next Write operation. At the same time the Flag is read, the value of the address counter (expressed in binary AAAAAAA) is read out. The address counter is determined by the preceding instruction and is used by both the CG RAM and DD RAM addresses. The contents of the address remain unchanged from items above (7 and 8). 10. Write data into CG RAM or DD RAM DB 7 DB 0 Code 1 0 D D D D D D D D Higher order bits Lower order bits Writes 8-bit binary data DDDDDDDD into the CG RAM or DD RAM. Previous specification of the CG RAM or DD RAM address setting determines whether the CG RAM or the DD RAM is to be written into. After the data is written into the appropriate RAM, the RAM address is automatically increased or decreased by 1, according to the Entry Mode. The Entry Mode also determines the display shifting. 11. Read data from CG RAM or DD RAM DB 7 DB 0 Code 1 1 D D D D D D D D Higher order bits Lower order bits Reads 8-bit binary data DDDDDDDD from the CG RAM or the DD RAM. The previous designation determines whether the CG RAM Address Set instruction or the DD RAM Address Set instruction must be executed before the Read Data instruction is executed. If it isn t, the first Read Data instruction serially, the next address data is normally read from the second Read operation. The Address Set instruction when shifting the Cursor Shift instruction (when reading the DD RAM). The operation of the Cursor Shift instruction is the same as that for the DD RAM s Address Set instruction. After a Read Data instruction is executed, the Entry Mode automatically increases or deceases the value of the address by 1. However, the display will not be shifted no matter what the Entry Mode is. Note: The address counter (AC) is automatically increased or decreased by 1 after a Write instruction to either the CG RAM or the DD RAM. At the time, the RAM data selected by the AC cannot be read out even is a Read instruction is executed. The conditions for correct data readout are; execute either the address set instructions or the cursor shift instruction (only with the DD RAM) and, just before reading out, execute the Read instruction from the second time the Read instruction is serial. 9

Relation between CG RAM addresses, DD RAM charcter codes and CG RAM character patterns Figure 9, 5 x 7-dot character patterns Character codes (DD RAM data) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 CG RAM address 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 Character patterns (CG RAM data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Higher-order bits Lower-order bits * * Higher-order bits Lower-order bits Higher-order bits Lower-order bits 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 Character Pattern#1 Cursor Position Character Pattern#2 0 0 0 0 1 1 1 1 1 1 *Don t care * 1 0 0 1 0 1 1 1 0 1 1 1 Notes: 1. Bits 0~2 of the character code correspond to bits 3~5 of the CG RAM address (3 bits: 8 patterns). 2. Bits 0~2 of the CG RAM address designate the line position of the character pattern. The 8th line is the cursor position and the display is logically OR'd with the cursor. In order to display the cursor, the 8th line data corresponding to the cursor display position must be kept at 0. When the data in the 8th line is '1', bit 1 will turn on, whether or not the cursor exists. 3. The row position of the character pattern corresponds to bit 0~4 of the CG RAM data, as shown in the figure, with bit '4' locating the left end. Bits 5Ø7 of the CG RAM data are not used for the display, so they can be used for general data RAM. 4. The CG RAM character patterns are selected when bits 4~7 of the character code are all '0'. However, since bit '3' of the character code is an effective bit, the 'R' display in the character pattern example is selected by the character code '00' or '08' (hexadecimal). 5. In the CG RAM data, '1' corresponds to selection for display and '0' for non-selection. Figure 10, 5 x 10-dot character patterns Character codes (DD RAM data) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 CG RAM address 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 Character patterns (CG RAM data) 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Higher-order bits Lower-order bits * * Higher-order bits Lower-order bits Higher-order bits Lower-order bits 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 Character Pattern#1 Cursor Position Character Pattern#2 0 0 0 0 1 1 1 1 1 1 *Don t care * 1 0 0 1 0 1 1 1 0 1 1 1 10

Notes: 1. Bits 1 and 2 of the character code correspond to bits 4 and 5 of the CG RAM address (2 bits: 4 patterns). 2. Bits 0~3 of the CG RAM address designate the line position of the character pattern. The 11th line designates the position of the cursor, and the logically OR of the 11th line and cursor are displayed. In order to display the cursor, the 11th line data corresponding to the cursor display position must be kept at 0. When the data in the 11th line is 1, bit 1 will turn on, whether or not the cursor exists. Since the 12th ~ 16th lines are not used for display, they can be used for the general data RAM. 3. The row position of the 5 7-dot character pattern. 4. The CG RAM character patterns are selected when bits 4~7 of the character code are all '0'. However, since 0 and '3' of the character code are ineffective bits, the 'P' display in the character pattern example is selected by the character code '00', 01 or '09' (hexadecimal). 5. In the CG RAM data, '1' corresponds to selection for display and '0' for non-selection. DD RAM address maps The control ICs used in these modules have a DD RAM with a capacity of 80 characters. For 1-line displays, when the Function Set instruction has N=0, the DD RAM addresses are 00 to 4F (hexadecimal). For 2-line displays, when N=1, DD RAM addresses for the first line are '00'~'27' (hexadecimal) while the addresses for the second line are '40'~'67' (hexadecimal). The modules can display all of the character codes starting from the first address, up to the capacity of the display. Figure 11 Digit 1 Line 1 stock nos. 585-006, 585-084 585-012, 585-090 184-8437, 184-8443 184-8516 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Figure 12 Digit 1 Line 1 Line 2 stock nos. 585-040,585-129 184-8487,184-8572 1 2 3 - - - - - - - - - - 38 39 40 00 01 02 - - - - - - - - - - 25 26 27 40 41 42 - - - - - - - - - - 65 66 67 Digit 1 Line 1 Line 2 Digit 1 Line 1 Line 2 stock nos. 585-028, 585-107 184-8459, 184-8538 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F stock nos. 585-034, 585-113 184-8471 1 2 3 - - - - - - - - - - 22 23 24 00 01 02 - - - - - - - - - - 15 16 17 40 41 42 - - - - - - - - - - 55 56 57 Digit 1 Line 1 Line 2 Line 3 Line 4 stock nos. 585-056, 184-8500 1 2 3 - - - - - - - - - - 38 39 40 00 01 02 - - - - - - - - - - 25 26 27 40 41 42 - - - - - - - - - - 65 66 67 00 01 02 - - - - - - - - - - 25 26 27 40 41 42 - - - - - - - - - - 65 66 67 Note: stock nos. 585-056 and 184-8500 contain 2 control ICs. The upper 2 lines of the display are controlled by control IC1, while the lower 2 lines are controlled by control IC2. The instructions for the upper 2 and lower 2 lines are executed separately using different enabling signals (E1 and E2). Figure 13 stock nos. 184-8465, 184-8544 N=1 : 2= Line display F=Ø : 5x7 Dots Digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Line 1 ØØ Ø1 Ø2 Ø3 Ø4 Ø5 Ø6 Ø7 Ø8 Ø9 ØA ØB ØC ØD ØE ØF 1Ø 11 12 13 Line 2 4Ø 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 5Ø 51 52 53 stock no. 184-8819 N=1 : 2= Line display F=Ø : 5x7 Dots Digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Line 1 ØØ Ø1 Ø2 Ø3 Ø4 Ø5 Ø6 Ø7 Ø8 Ø9 ØA ØB ØC ØD ØE ØF 1Ø 11 12 13 Line 2 4Ø 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 5Ø 51 52 53 Line 3 14 15 16 17 18 19 1A 1B 1B 1D 1E 1F 2Ø 21 22 23 24 25 26 27 Line 4 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 6Ø 61 62 63 64 65 66 67 11

Reset function 1. Initialising by the internal reset circuit When the power is turned on, the module is automatically initialised (reset) by means of the internal reset circuit. The following instructions are executed during initialisation. The Flat (BF) will be kept in a busy state until initialisation is completed (BF=1). The busy state is 10ms after the VCC rises to 4.5V. a. Display Clear b. Function Set DL=1: 8-bit long interface data N=0: 1-line display F=0: 5 7-dot character font c. Display ON/OFF D=0: display OFF C=0: Cursor OFF B=0: Blinking OFF d. Entry Mode Set I/D=1: +1 (increment) S=0: No shift Power supply conditions when using the internal reset circuit Test Limit Item Symbol Condition Min. Typ. Max. Unit Power supply *CC - 0.1-10 msd rise time Power supply *OFF - 1 - - ms off time Figure 14 4.5V 0.2V V CC t rcc 0.2V 0.2V t OFF Note: t OFF is the time that the power is off when the power supply voltage dips instantaneously or when the voltage turns on and off repeatedly Figure 15 a) For 8-bit long interfaces: Power on Wait more than 15ms after Vcc rises to 4.5V DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 0 0 0 0 1 1 BF cannot be checked prior to this instruction Wait more than 4.1ms DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 0 0 0 0 1 1 BF cannot be checked prior to this instruction Wait more than 100µs Function set (8-bit long interface) Function set (8-bit long interface) DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 0 0 0 0 1 1 BF cannot be checked prior to this instruction Function set (8-bit long interface) flag check DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 0 0 0 0 1 1 N F Function set (8-bit long interface) The number of display lines and the flag check DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 0 0 0 0 0 0 1 0 0 0 flag check character font must be specified 2.Resetting by instructions In case the preceding conditions are not met and the internal reset circuit does not operate normally, the reset operation will have to be done by instruction, according to the following procedure. DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 0 0 0 0 0 0 0 0 0 1 flag check DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 0 0 0 0 0 0 0 0 I/D S End of Reset operation 12

Figure 16 b) For 4-bit long interfaces: Figure 17, Timing sequence for 8-bit data transfer Power on Wait more than 15ms after Vcc rises to 4.5V DB 7 DB 6 DB 5 DB 4 0 0 0 0 1 1 Wait more than 4.1ms BF cannot be checked prior to this instruction Function set (8-bit long interface) E Internal DB 2 IR 2 Internal operation Not DR 2 DB 7 DB 6 DB 5 DB 4 0 0 0 0 1 1 Wait more than 100µs DB 7 DB 6 DB 5 DB 4 0 0 0 0 1 1 BF cannot be checked prior to this instruction Function set (8-bit long interface) BF cannot be checked prior to this instruction Function set (8-bit long interface) DB 6 DB 0 IR 6 IR 0 Instruction Register (R) Write AC 6 Flag Address Counter (AC) Read AC 6 AC 6 DR 6 AC 0 AC 0 AC 0 DR 0 Flag Address Counter (AC) Read Flag Check Flag Address Counter (AC) Read Data Register (DR) Write flag check DB 7 DB 6 DB 5 DB 4 0 0 0 0 1 0 flag check DB 7 DB 6 DB 5 DB 4 0 0 0 0 1 0 0 0 N F Function set (Set interface to 4-bits long) Interface is 8-bits long) Function set (4-bit long interface) The number of display lines and the character font must be specified Figure 18, A 0 A 14 A 15 VMA O 2 6800 D 0 ~ D 2 Interfacing with the 6800 MPU 8 E DISPLAY DB 0 ~ DB 7 flag check O 2 DB 7 DB 6 DB 5 DB 4 0 0 0 0 0 0 0 0 1 0 0 0 flag check Interfacing with an MPU When looked at from the perspective of an MPU, the module can be considered as either a RAM or an I/O device. Basically, the MPU first executes the test on the module in order to confirm that the prior instruction has been executed and completed, then commands the module to execute the next instruction. The module is activated by an enabling signal (E). In those modules which contain several control ICs (ie, stock no. 585-056) each control IC is activated by a separate enabling signal, while every control co-uses the control signals (, ) and the data buses (DB0~DB7). The module can be interfaced with an 8-bit MPU by either connecting it directly to the MPU's bus line, or by connecting it through a PIA. The width of the enabling signal (E) pulse should be a minimum of 450n sec. DB 7 DB 6 DB 5 DB 4 0 0 0 0 0 0 0 0 0 0 0 1 flag check DB 7 DB 6 DB 5 DB 4 0 0 0 0 0 0 0 0 0 0 I/D S End of Reset operation Display off Display clear Entry mode set VMA A 14, A 15 DB 0 ~DB 7 Read Write Data Address or Inst. Code When is high and is low, a Flag signal is output on the data bus DB7. The module can function as either a RAM or an I/O device A0 selects either the Instruction Register (IR) or the Data Register (DR) The addresses for the module are as follows: 1. IR Write #'Fxx0' (=0) 2. DR Write #'Fxx1' (=0) 3. Flat (DB7) and Address Counter (DB0~DB6 Read #'Fxx0' (=1) 4. DR Read #'Fxx1' (=1) The timing between the enabling signal (E) and the other control signals ( and ) should be satisfied with standard criteria. When the module is connected through a PIA and the control signals of the E, and are generated at the I/O port of the PIA, it is especially important that each of the signals should not appear simultaneously (minimum 140nsec is required for address setup time). The module can also be connected to a 4-bit MPU through the 4-bit MPU I/O port. If the I/O port has enough bits, data can be transmitted in an 8-bit length. However, if the bits are insufficient, the transmission is conducted in operations of 4 bits each (with designation of interface data length for 4 bits). When transmitting 4-bit long interface data, 2 cycles are required for the data transfer, as well as for the Flag check. 13

Figure 19, Timing sequence for 4-bit data transfer E Internal DB 2 DB 6 DB 4 DB 1 IR 2 IR 6 Internal operation Not IR AC 1 1 AC 1 DR 2 DR 1 IR 2 AC 6 AC 2 AC 6 AC 2 DR 6 DR 2 IR 5 IR 1 AC 5 AC 1 AC 5 AC 1 AC 5 DR 1 IR 4 IR 0 AC 4 AC 0 AC 4 AC 0 DR 4 DR 0 Instruction Register (R) Write Flag Address Counter (AC) Read Flag Check Flag Address Counter (AC) Read Data Register (DR) Write The module functions as a RAM The 8048 and 8049 MPUs do not generate a signal which corresponds to the signal, therefore, the signal is generated as the RD and RW signals A capacitor and a resistor shown in Figure 17 are used to generate the setup time (min. of 140ns) of the -E. It is necessary to decide the value of the capacitors and the resistors so that the pulse width of the E signal is maintained at minimum 450ns The addresses for the module are as follows: 1. IR Write #'F0' (=0) 2. DR Write #"'F1' (=0) 3. Flag (DB7) and Address Counter (DB0~DB6) Read #'F0' (=1) 4. DR Read #'F1' (=1) Figure 20, Interfacing stock no. 585-056 with a 6800 MPU 6800 A 0 A 11 A 14 A 15 VMA O 2 D 0 D 1 stock no. 639-399 A Y B 4 C Y 5 D G 1 G 2 8 E 1 E 2 DB 0 DB 2 DISPLAY Figure 22, Interfacing with an 8085A MPU S 1 RD WR IO/M A 15 A 14 A 13 8085A A 12 AD 0 AD 1 ALE CLK READY D Q CLK RD D CLK Q E DISPLAY MODULE DB 0 DB 1 (1) IR Write # 9xx0 (=0) (2) DR Write # 9xx1 (=0) Enable signal E1 (3) Flag (DB7) and Address Counters (DB0~DB0) Read # 9xx0 (=1) (4) (DR) Read # 9xx1 (=1) (1) IR Write # Bxx0 (=0) (2) DR Write # Bxx1 (=0) Enable signal E2 (3) Flag (DB7) and Adress Counters (DB0~DB0) Read # Bxx0 (=1) (4) (DR) Read # Bxx1 (=1) Figure 21, Interfacing with 8048 or 8049 MPU RD WR 8048 (8049) ALE DB 0 ALE RD WR DB 0 DB 2 DB 2 EN 1D1O stock no. 5O 639-765 6O 7O 8D8O Address Floating Data Floating Floating 8 E DISPLAY MODULE DB 0 DB 1 CLK IO/M S 1 A 12 A 15 ALE RD, WR READY T 1 T 2 T WAIT T 3 The module functions as an I/O device Because the 8085A's RD and WR signals are each 400ns, the TWAIT cycle is set so that the width of the E signal can be satisfied with minimum 450 ns The addresses for the module are as follows: 1. IR Write #'EX' (=0) 2. DR Write #'FX' (=0) 3. Flag (DB7) and Address Counter Read #'EX' (E/W=1) DR Read #'FX" (=1) Typical problems Q. Why can only 1 character line be driven on a 2 character line module? A. The module has either failed to initialise or has been initialised as a 1 line display. Q. Why are some rows and/or columns of pixels missing? A. The module has been mounted in a way which is applying pressure to the bezel supporting the LCD glass. Q. Why does the display remain blank after initialisation and ASCII data sent? A. Vlcd (V0) incorrectly set. Timing incorrect. Check that all the set up times have been followed. Check that the enable pulse width is 450nS minimum. 14

Q. Why can only characters 1 to 8 be addressed on a one line by sixteen character module? A. A 1 line by 16 character module must be treated electrically as a 2 line by 8 character display module. After initialisation line 1 will address characters 1 to 8 (RAM address 00h to 07h) and line 2 will address characters 9 to 16 (RAM address 40h to 47h). Precaution for using 1. Handling a) Do not touch, press or rub the display panel with a hard, stiff tool or object (e.g. tweezers) as the polarisers in the panel are easily scratched. b) Never use organic solvents to clear the display panels as these solvents may adversely affect the polariser. To clean the display panel and dampen a bit of absorbent cotton with petroleum and gently wipe the panel. c) Never touch terminals of electrodes of PCB or LSI leads. d) Avoid using or storing the LCM under high temperature and high humidity conditions. When in storage it is recommended that the device is packaged in a conductive polyethylene bag and placed under the condition where the temperature is relatively lower (10-30 C), and direct sunlight or fluorescent lamp must be cut off. 2. Operation a) Never connect or disconnect the LCM from the main system while power is being supplied. b) If the operating temperature drops below the temperature limits, the blinking speed of the display will decrease, while if it rises above the prescribed limits, the entire display will turn black. When the temperature returns to within normal limits, the display will operate normally. 3. Workmanship a) Never disassemble the module. b) Anti-static precautions must be taken, as the circuit of the module contains a CMOS LSI. 15

The information provided in technical literature is believed to be accurate and reliable; however, Components assumes no responsibility for inaccuracies or omissions, or for the use of this information, and all use of such information shall be entirely at the user s own risk. No responsibility is assumed by Components for any infringements of patents or other rights of third parties which may result from its use. Specifications shown in Components technical literature are subject to change without notice. Components, PO Box 99, Corby, Northants, NN17 9 Telephone: 01536 201234 An Electrocomponents Company Components 1998