ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS MC71PD506. USER S MANUAL (Ver. 1.0)

ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS MC71PD506 USER S MANUAL (Ver. 1.0)

TABLE OF CONTENTS 1. PRODUCT OVERVIEW... 1 2. MEMORY ORGANIZATION... 12 3. INTERRUPT... 26 4. INSTRUCTIONS SET... 30 5. CLOCK CIRCUIT... 72 6. RESET AND POWER-DOWN MODE... 78 7. I/O PORTS... 84 8. WATCHDOG TIMER... 106 9. 8-BIT TIMER 0... 110 10. 16-BIT TIMER 1 (8-BIT TIMER A/B)... 114 11. REAL TIMER... 122 12. SERIAL INTERFACE... 126 13. LCD CONTROLLER/DRIVER... 130 14. ELECTRICAL DATA... 140 15. MECHANICAL DATA... 152 16. MC71PD506 OTP... 154 17. DEVELOPMENT TOOLS... 156

1. PRODUCT OVERVIEW 1.1 KEY FEATURES CPU Main clock Sub clock Instruction set ROM capacity RAM capacity Instruction execution times I/O Port Programmable timer LCD driver GMC14 core (8-bit RISC CPU) 0.4MHz 12MHz (Crystal, ceramic, or RC) 32.768kHz (Crystal) 35 instructions single word instructs 14-bit wide instruction word 6,144 x 14-bits (10,752-Byte) 176 x 8-bits (30 x 8-bits including LCD display RAM) 167nS at 12MHz fx (main) 61uS at 32.768kHz fxt (sub) I/O: 47 bits Normal I/O: 13bits LCD shared I/O: 34 bits One 8-bit timer/counter One 16-bit timer/counter (Shared with two 8-bit timer/counters) 26 segments x 2/ 3/ 4/ 5/ 6/ 8 commons (Internal or external resistor bias) Bias selectable (1/2, 1/3, 1/4) Watchdog timer function Time interval generation Serial Interface Interrupt Power supply voltage 0.25, 0.5, 1S and 10mS at 32.768KHz Eight-frequency output to BUZ pin Mode0: synchronous Mode1: asynchronous External: Twelve external interrupts Internal: WDT interrupt : Timer 0 interrupt (8-bit) : Timer 1/A interrupt (16/8-bit) : Timer B interrupt (8-bit) : Real timer interrupt 2.4 V to 5.5 V at 4MHz 2.7 V to 5.5 V at 8MHz 4.0 V to 5.5 V at 12MHz SEP.2007 VER 1.0 1

1.1 KEY FEATURES (CONTINUED) Operating temperature -20 to +85 Power-saving Idle: only CPU clock stop Stop: System clock and CPU clock stop Package 64-pin LQFP, Pallet 2 SEP.2007 VER 1.0

1.2 Ordering Information MC71PD506E MC71PD506C Device ROM Size RAM size Package 6K words OTP 6K words OTP 176 bytes 176 bytes 64 LQFP Pellet(Probe tested wafer) SEP.2007 VER 1.0 3

1.3 BLOCK DIAGRAM XIN nmclr XTIN XOUT XTOUT VDD VSS T0PWM/P4.4 T1OUT/P0.1 T1CLK/P0.0 T1CLK/P0.0 T1OUT/P0.1 P0.2 P0.3 INT0 INT3/P0.4 P0.7 SEG29 SEG22/ INT4 INT11/P1.0 P1.7 8-Bit Timer/ Counter 0 16-Bit Timer/ Counter 1 Port 0 Port 1 SEG21 SEG14/P2.0 P2.7 Port 2 SEG13 SEG6/P3.0 P3.7 Port 3 Port I/O and Interrupt Control 6,144 X 14-bit ROM GMC14Core (8-bit RISC CPU) 176 X 8-bit Register File Watchdog Timer Real Timer LCD Driver/ Controller Serial Interface Port 5 Port 4 BUZ/P4.3 COM0 COM3/P5.7 P5.4 COM4 COM7/SEG0 SEG3/P5.3 P5.0 SEG4 SEG5/P4.6 P4.5 SEG6 SEG13/P3.7 P3.0 SEG14 SEG21/P2.7 P2.0 SEG22 SEG29/P1.7 P1.0 VLC0 VLC3 SCK/P4.0 SO/P4.1 SI/P4.2 P5.4 P5.7/COM3 COM0 P5.0 P5.3/SEG3 SEG0/ COM7 COM4 P4.0/SCK P4.1/SO P4.2/SI P4.3/BUZ P4.4/T0PWM P4.5 4.6/SEG5 SEG4 Figure 1-1. Block Diagram 4 SEP.2007 VER 1.0

1.4 PIN ASSIGNMENTS 1.4.1 64-PIN PACKAGE NC P4.0/SCK P4.1/SO P4.2/SI P4.3/BUZ P4.4/T0PWM P1.0/INT4/SEG29 P1.1/INT5/SEG28 P1.2/INT6/SEG27 P1.3/INT7/SEG26 P1.4/INT8/SEG25 P1.5/INT9/SEG24 P1.6/INT10/SEG23 P1.7/INT11/SEG22 P2.0/SEG21 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 MC71PD506 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC P2.1/SEG20 P2.2/SEG19 P2.3/SEG18 P2.4/SEG17 P2.5/SEG16 P2.6/SEG15 P2.7/SEG14 P3.0/SEG13 P3.1/SEG12 P3.2/SEG11 P3.3/SEG10 P3.4/SEG9 P3.5/SEG8 P3.6/SEG7 P3.7/SEG6 P0.7/INT3 P0.6/INT2 VSS P0.5/INT1 P0.4/INT0 XOUT XIN NMCLR (Vpp) XTIN XTOUT P0.3 (SDATA) P0.2 (SCLK) VDD P0.1/T1OUT P0.0/T1CLK NC NC P5.7/COM0 P5.6/COM1 P5.5/COM2 P5.4/COM3 P5.3/COM4/SEG0 P5.2/COM5/SEG1 P5.1/COM6/SEG2 P5.0/COM0/SEG3 VLC3 VLC2 VLC1 VLC0 P4.6/SEG4 P4.5/SEG5 NC Figure 1-2. MC71PD506 Pin Assignments (64-Pin) SEP.2007 VER 1.0 5

1.5 PIN DESCRIPTIONS Pin Names I/O Pin Description After RESET Alternative Functions P0.0 I/O 1-bit programmable I/O pin. Schmitt trigger input, Pushpull output, or Open-drain output port. Used as an input Input T1CLK P0.1 T1OUT port, a Pull-up resistor can be programmed as 1-bit. P0.2 - P0.3 - P0.4 INT0 P0.5 INT1 P0.6 INT2 P0.7 INT3 P1.0 I/O 1-bit programmable I/O pin. Schmitt trigger input, Pushpull output, or Open-drain output port. Used as an input Input INT4/SEG29 P1.1 INT5/SEG28 port, a Pull-up resistor can be programmed as 1-bit. P1.2 INT6/SEG27 P1.3 INT7/SEG26 P1.4 INT8/SEG25 P1.5 INT9/SEG24 P1.6 INT10/SEG23 P1.7 INT11/SEG22 P2.0 I/O Pair-bit programmable I/O pin. Input, Push-pull output, or Input SEG21 P2.1 Open-drain output port. Used as an input port, a Pull-up SEG20 resistor can be programmed as pair-bit. P2.2 SEG19 P2.3 SEG18 P2.4 SEG17 P2.5 SEG16 P2.6 SEG15 P2.7 SEG14 P3.0 I/O Pair-bit programmable I/O pin. Input, Push-pull output, or Input SEG13 P3.1 Open-drain output port. Used as an input port, a Pull-up SEG12 resistor can be programmed as pair-bit. P3.2 SEG11 P3.3 SEG10 P3.4 SEG9 P3.5 SEG8 P3.6 SEG7 P3.7 SEG6 6 SEP.2007 VER 1.0

1.5 PIN DESCRIPTIONS (CONTINUED) Pin Names I/O Pin Description After RESET Alternative Functions P4.0 I/O 1-bit programmable I/O pin. Input, Push-pull output, or Input SCK P4.1 Open-drain output port. Used as an input port, a Pull-up SO resistor can be programmed as 1-bit. P4.2 SI P4.3 BUZ P4.4 T0PWM P4.5 SEG5 P4.6 SEG4 P5.0 I/O 1-bit programmable I/O pin. Input, Push-pull output, or Input SEG3/COM7 P5.1 Open-drain output port. Used as an input port, a Pull-up SEG2/COM6 resistor can be programmed as 1-bit. P5.2 SEG1/COM5 P5.3 SEG0/COM4 P5.4 COM3 P5.5 COM2 P5.6 COM1 P5.7 COM0 T1CLK I/O Timer 1/A external clock input Input P0.0 T1OUT I/O Timer 1/A data output Input P0.1 INT0 I/O External interrupt input pins Input P0.4 INT1 P0.5 INT2 P0.6 INT3 P0.7 SCK I/O Serial clock Input P4.0 SI I/O Serial data input Input P4.2 SO I/O Serial data output Input P4.1 BUZ I/O Buzzer signal output Input P4.3 T0PWM I/O Timer 0 PWM output Input P4.4 INT4 I/O External interrupt input pins Input P1.0 INT5 P1.1 INT6 P1.2 INT7 P1.3 INT8 P1.4 INT9 P1.5 INT10 P1.6 INT11 P1.7 SEP.2007 VER 1.0 7

1.5 PIN DESCRIPTIONS (CONTINUED) Pin Names I/O Pin Description After RESET Alternative Functions SEG29 SEG22 I/O LCD Segment signal output Input P1.0 P1.7 SEG21 SEG14 P2.0 P2.7 SEG13 SEG6 P3.0 P3.7 SEG5 SEG4 P4.5 P4.6 SEG3 SEG0 P5.0 P5.3 COM0 COM7 I/O LCD common signal output Input P5.7 P5.0 VLC0 VLC3 - LCD bias voltage input pins - - nmclr I System reset pin - - XIN,XOUT - Main oscillator pins - - XTIN,XTOUT - Sub oscillator pins. - - VDD,VSS - Power input pins - - 8 SEP.2007 VER 1.0

1.6 PIN CIRCUITS In Schmitt Trigger Figure 1-3. Pin Circuit Type 1 (nmclr) VDD Pull-up Enable OPEN-DRAIN ENABLE DATA OUTPUT DISABLE VDD P- Channel N- Channel I/O VSS Figure 1-4. Pin Circuit Type 4-1 (P0) SEP.2007 VER 1.0 9

VDD OPEN-DRAIN ENABLE Pull-up Enable VDD P- Channel DATA OUTPUT DISABLE VSS N- Channel I/O Figure 1-5. Pin Circuit Type 4-0 (P4.0-P4.4) V LC0 V LC1 COM/ SEG OUTPUT Disable OUT VLC2 VLC3 VSS Figure 1-6. Pin Circuit Type 7-5 10 SEP.2007 VER 1.0

VDD Open Drain Data Output Disable 1 VDD P-CH N-CH Pull-Up Resistor I/O Resistor Enable COM/SEG Output Disable 2 Circuit Type 7-5 Figure 1-7. Pin Circuit Type 7-1 (P1) VDD Open Drain Data Output Disable 1 VDD P-CH N-CH Pull-Up Resistor I/O Resistor Enable COM/SEG Output Disable 2 Circuit Type 7-5 Figure 1-8. Pin Circuit Type 7-2 (P2, P3, P4.5-P4.6, P5) SEP.2007 VER 1.0 11

User Memory Space MC71PD506 2. MEMORY ORGANIZATION 2.1 PROGRAM MEMORY ORGANIZATION The GMC14 series have a 16-bit program counter capable of addressing a 64k x 14-bit program memory space. The reset vector is at 0000H and the interrupt vector is at 0004H. The program memory size of the MC71PD506 is 6k words (6k x 14-bit, from the address 0000H to 17FFH). PC<15:0> 16 Stack Level 1 Stack Level 8 Reset Vector 0000H Interrupt Vector On-chip program Memory (page 0) On-chip program Memory (page 1) On-chip program Memory (page 2) 0004H 0005H 07FFH 0800H 0FFFH 1000H 17FFH 1800H On-chip program Memory (page 30) On-chip program Memory (page 31) EFFFH F000H F7FFH F800H FFFFH Figure 2-1. Program Memory Map and Stack 12 SEP.2007 VER 1.0

2.1.1 PC AND PCLATH REGISTERS The Program Counter (PC) is 16-bit wide. The lower bits (PC<7:0>) come from PCL register, which is a readable and writable register. The upper bits (PC<15:8>) are not directly readable (or writable), but are indirectly writable through the PCLATH register. On any reset, (the upper bits of) the PC is (will be) cleared. Figure 2-2 shows the two situations for PC loading. The upper example in the figure 2-2 shows how the PC is loaded by writing to PCL (PCLATH<7:0> PCH). The lower example in the figure 2-2 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<7:3> PCH). Write to PCL PCH PCL 15 8 7 0 PC PCLATH ALU RESULT 7 0 GOTO, CALL PCH PCL 15 11 10 0 PC OPCODE[10:0] PCLATH 7 3 2 0 Figure 2-2. Loading of PC in different situations A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When reading a table using a computed GOTO method, pay attention if the table location crosses a PCL memory boundary (each 256 byte block). SEP.2007 VER 1.0 13

2.1.2 Program memory paging The GMC14 series devices are capable of addressing a continuous 64k words block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2k words program memory page. When doing a CALL or GOTO instruction the upper 5 bits of the address are provided by PCLATH<7:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If RETURN, RETLW, or RETFIE instructions are executed, the entire 16-bit PC is popped from the stack. Therefore, manipulation of the PCLATH<7:3> bits is not required for the return instructions (which pops the address from the stack). NOTE: Because the MC71PD506 use only PCLATH<4:0> bit, the PCLATH<7:5> bits should be always logic 000b. 2.2 STACK The GMC14 series has an 8 level depth x 16-bit width hardware stack. The stack space is neither part of program nor data space and the stack pointer is not readable or writable. The PC is pushed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is popped in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a push or pop operation. The stack operates as a circular buffer. This means that after the stack has been pushed eight times, the ninth push overwrites the value that stored from the first push. The tenth push overwrites the second push (and so on). NOTES: 1. There are no STATUS bits to indicate stack overflow or stack underflow conditions. 2. There are no instructions/mnemonics called push or pop. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address. 14 SEP.2007 VER 1.0

2.3 DATA MEMORY The data memory for the MC71PD506 is partitioned onto two banks which contain the general purpose registers and the special function registers. Bank 0 is selected when the RP1:RP0 bits in status register are 00b and bank 1 when RP1:RP0 are 01b. 00H Indirect addr 80H Indirect addr 1FH Special Function Register 9FH Special Function Register 20H A0H General purpose Register 7FH General purpose Register D1H D2H LCD Display RAM EFH F0H Mapped in Bank 0 70H - 7FH FFH Bank 0 Bank 1 Figure 2-3. Register File Organization (MC71PD506) The lower locations of each bank are reserved for the special function registers. The upper locations of each bank are general purpose registers implemented as static RAM. All two banks contain special function registers. Some of the special function registers are mirrored in other banks for code reduction and quicker access. The register file can be accessed either directly, or indirectly through the File Select Register (FSR). Refer to 2.3.3 addressing mode. 2.3.1 GENERAL PURPOSE REGISTER The size of the MC71PD506 s general purpose register is 176 bytes (20H~7FH and A0H~EFH(30-byte including LCD display RAM)). The following general purpose registers are not physically implemented: - 0F0H-0FFH of Bank 1 These locations are used for common access across banks. SEP.2007 VER 1.0 15

2.3.2 SPECIAL FUNCTION REGISTER There are 51 bytes of special function register. Some of the special function registers are visible on any of two memory banks. As is shown in figure below; 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 7FH CONFIG CPUCLK PCL STATUS FSR SICR SIDAT SIPS WTSCR WTCR PCLATH INTCON IPND TSCR0 TCR0 TDR0H TDR0L TSCRA TCRA TDRA TSCRB TCRB TDRB RTSCR LCDR - - - - - - - RAM Memory Space Bank 0 CONFIG OSCSEL PCL STATUS FSR DDR0H DDR0L PUR0 EINT0 EPND0 PCLATH - DDR1H DDR1L PUR1 EINT1 EPND1 DDR2 DDR3 PUR2n3 DDR4H DDR4L PUR4 DDR5H DDR5L PUR5 P0 P1 P2 P3 P4 P5 RAM Memory Space Bank 1 Figure 2-4. Data memory map The special function registers are the registers used by the cpu and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral). The special function registers associated with the core functions are described below. The rest of special function registers are described in the corresponding peripheral section. 16 SEP.2007 VER 1.0

2.3.2.1 CONFIG Register The CONFIG register contains configuration bits, which defines additional the MC71PD506 core features. To change it s contents, the FSR register should be cleared first, and then a particular instruction using indirect addressing mode should be executed. CONFIG REGISTER (CONFIG) (00H, 80H) 7 6 5 4 3 2 1 0 CONFIG - - - - - - DEC INC (Initial value : - - - - - -00) Read/Write - - - - - - R/W R/W Bit7-2 DEC INC Not available for the MC71PD506 Indirect addressing mode with post decrement FSR contents Indirect addressing mode with post increment FSR contents 0: Post FSR decrement disabled 1: Post FSR decrement enabled 0: Post FSR increment disabled 1: Post FSR increment enabled NOTE: Both DEC and INC bits set disable auto increment/decrement function. SEP.2007 VER 1.0 17

2.3.2.2 STATUS Register The STATUS register contains the arithmetic status of the ALU and the bank selection bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then writing to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the nto and npd bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different from intended. STATUS REGISTER (STATUS) (03H, 83H) 7 6 5 4 3 2 1 0 STATUS IRP RP1 RP0 nto npd Z DC C (Initial value : NOTE ) Read/Write R/W R/W R/W R R R/W R/W R/W IRP RP1 RP0 nto npd Z DC Register Bank Selection Bit (used for indirect addressing) Register Bank Selection Bits (used for direct addressing) Time-out Bit Power-down Bit Zero Bit Digit Carry/nBorrow Bit 0: Bank 0, 1 (00H 0FFH) 1: Bank 2, 3 (100H 1FFH); (Not used for the MC71PD506) 00: Bank 0 01: Bank 1 10: Bank 2; (Not used for the MC71PD506) 01: Bank 3; (Not used for the MC71PD506) 0: A WDT time-out occurred 1: After power-up, CLRWDT instruction, or SLEEP instruction. 0: By execution of the SLEEP instruction 1: After power-up or by the CLRWDT instruction 0: The result of an arithmetic or logic operation is not zero 1: The result of an arithmetic or logic operation in zero 0: No carry-out from the 4 th low order bit of the result occurred 1: A carry-out from the 4 th low order bit of the result occurred C Carry/nBorrow Bit 0: No carry-out from the most significant bit of the result occurred 1: A carry-out from the most significant bit of the result occurred NOTE: Refer to the Table 6-3 in the Chapter 6. RESET AND POWER DOWN for the initial value of STATUS register. 18 SEP.2007 VER 1.0

2.3.2.3 Internal Interrupt Control Register (INTCON) The INTCON register is able to select enable or disable global interrupt, watchdog timer interrupt, timer 0 interrupt, timer 1/A interrupt, timer B interrupt, real timer interrupt, and SI interrupt. INTERNAL INTERRUPT CONTROL REGISTER (INTCON) (0BH) 7 6 5 4 3 2 1 0 INTCON GIE WTIE T0IE TAIE TBIE RTIE SIIE - (Initial value : 0000 000 -) Read/Write R/W R/W R/W R/W R/W R/W R/W - GIE WTIE T0IE TAIE TBIE RTIE SIIE Bit0 Global Interrupt Enable Bit Watchdog Timer Interrupt Enable Bit Timer 0 Interrupt Enable Bit Timer 1/A Interrupt Enable Bit Timer B Interrupt Enable Bit Real Timer Interrupt Enable Bit SI Interrupt Enable Bit Not available for the MC71PD506 0: Disable all interrupt 1: Enable all un-masked interrupts 0: Disable interrupt 1: Enable interrupt 0: Disable interrupt 1: Enable interrupt 0: Disable interrupt 1: Enable interrupt 0: Disable interrupt 1: Enable interrupt 0: Disable interrupt 1: Enable interrupt 0: Disable interrupt 1: Enable interrupt SEP.2007 VER 1.0 19

2.3.2.4 Internal Interrupt Pending Register (IPND) The IPND register is a readable and writable register, which contains various pending bits for internal interrupt. INTERNAL INTERRUPT PENDING REGISTER (IPND) (0CH) IPND - 7 6 5 4 3 2 1 0 WT PND T0 PND TA PND TB PND RT PND SI PND Read/Write - R/W R/W R/W R/W R/W R/W - - (Initial value : - 000 000 -) Bit7 WTPND T0PND TAPND TBPND RTPND SIPND Bit0 Not available for the MC71PD506 Watchdog Timer Interrupt Pending Bit Timer 0 Interrupt Pending Bit Timer 1/A Interrupt Pending Bit Timer B Interrupt Pending Bit Real Timer Interrupt Pending Bit PWM Interrupt Pending Bit Not available for the MC71PD506 0 : interrupt request is not pending (when read); pending bit clear when write 0 1 : interrupt request is pending (when read) 0 : interrupt request is not pending (when read); pending bit clear when write 0 1 : interrupt request is pending (when read) 0 : interrupt request is not pending (when read); pending bit clear when write 0 1 : interrupt request is pending (when read) 0 : interrupt request is not pending (when read); pending bit clear when write 0 1 : interrupt request is pending (when read) 0 : interrupt request is not pending (when read); pending bit clear when write 0 1 : interrupt request is pending (when read) 0 : interrupt request is not pending (when read); pending bit clear when write 0 1 : interrupt request is pending (when read) 20 SEP.2007 VER 1.0

2.3.2.5 Special Function Register s Map Register Name Address Hex Table 2-1. BANK0 Register s Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG 00H - - - - - - DEC INC CPUCLK 01H IDLE - - - - CCLK PCL 02H Program counter (PC) Least Significant Byte STATUS 03H IRP RP1 RP0 nto npd Z DC C FSR 04H Indirect data memory address pointer SICR 05H SIMOD CSEL DAT SIOP SIPRE C3CLR SIEDGE - SIDAT 06H SI Data Register SIPS 07H SI Pre-scaler Register WTSCR 08H WTFUN WT3C WTCS WTCC WTCR 09H 8-bit Watchdog Timer Counter Register PCLATH 0AH - - - Write buffer upper 5 bits of PC INTCON 0BH GIE WTIE T0IE TAIE TBIE RTIE SIIE - IPND 0CH - WTPND T0PND TAPND TBPND RTPND SIPND - TSCR0 0DH T0SS T0TS T0MS T0FF T0CS TCR0 0EH Timer0 Counter Register TDR0H 0FH Timer0 Data Register High Byte TDR0L 10H Timer0 Data Register Low Byte TSCRA 11H - - TARL TACE TACS T1MOD TCRA 12H Timer 1/A Counter Register TDRA 13H Timer 1/A Data Register TSCRB 14H - - TBRL TBCE TBCS - TCRB 15H Timer B Counter Register TDRB 16H Timer B Data Register RTSCR 17H LBRS RTEN RTSS BUZ RTCS LCDR 18H LCDDR BIAS and DUTY LCD Clock DISP 19H 1FH are not mapped NOTE: A dash ( ) means that the bit is neither used nor mapped. SEP.2007 VER 1.0 21

Register Name Address Hex Table 2-2. BANK1 Register s Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG 80H - - - - - - DEC INC OSCSEL 81H - - - - - MOSC SOSC SCLK PCL 82H Program counter (PC) Least Significant Byte STATUS 83H IRP RP1 RP0 nto npd Z DC C FSR 84H Indirect data memory address pointer DDR0H 85H P07 P06 P05 P04 DDR0L 86H P03 P02 P01 P00 PUR0 87H PUR07 PUR06 PUR05 PUR04 PUR03 PUR02 PUR01 PUR00 EINT0 88H INT3 INT2 INT1 INT0 EPND0 89H - - - - PND3 PND2 PND1 PND0 PCLATH 8AH - - - Write buffer upper 5 bits of PC 8BH is not mapped DDR1H 8CH P17 P16 P15 P14 DDR1L 8DH P13 P12 P11 P10 PUR1 8EH PUR17 PUR16 PUR15 PUR14 PUR13 PUR12 PUR11 PUR10 EINT1 8FH INT1011 INT89 INT67 INT45 EPND1 90H PND11 PND10 PND9 PND8 PND7 PND6 PND5 PND4 DDR2 91H P267 P245 P223 P201 DDR3 92H P367 P345 P323 P301 PUR2n3 93H PUR267 PUR245 PUR223 PUR201 PUR367 PUR345 PUR323 PUR301 DDR4H 94H - - P46 P45 P44 DDR4L 95H P43 P42 P41 P40 PUR4 96H - PUR46 PUR45 PUR44 PUR43 PUR42 PUR41 PUR40 DDR5H 97H P57 P56 P55 P54 DDR5L 98H P53 P52 P51 P50 PUR5 99H PUR57 PUR56 PUR55 PUR54 PUR53 PUR52 PUR51 PUR50 P0 9AH Port 0 Data Register P1 9BH Port 1 Data Register P2 9CH Port 2 Data Register P3 9DH Port 3 Data Register P4 9EH Port 4 Data Register P5 9FH Port 5 Data Register NOTE: A dash ( ) means that the bit is neither used nor mapped. 22 SEP.2007 VER 1.0

2.3.3 ADDRESSING MODES The MC71PD506 supports two addressing modes: direct or indirect. In Direct Addressing, the 9-bit direct address is concatenated from RP [1:0] bits of STATUS (03H) register and a 7LSB of instruction word. Indirect addressing is possible by using the CONFIG (00H) register. Any instruction using CONFIG (00H) register actually accesses data pointed by the File Select Register (FSR (04H)). The 9-bit address is concatenated from IRP bit from STATUS (03H) register and 8 bits of FSR (04H) register. Both Direct and indirect addressing modes are shown in figure below. Direct Addressing Indirect Addressing RP1RP0 6 Opcode 0 IRP 7 6 FSR register 0 Bank select Location select Bank select Location select 00H 00 01 10 11 00H 7FH Bank0 Bank1 Bank2 Bank3 7FH NOTE: The Bank2 and Bank3 are not used for the GM120BP Figure 2-5. Direct/Indirect addressing SEP.2007 VER 1.0 23

2.3.3.1. Indirect Addressing Mode Indirect addressing mode is applied when the instruction point directly to the CONFIG (00H) register. Any instruction pointing directly the CONFIG (00H) register as a source/destination, actually accesses data pointed by the FSR (file select register, 04H). In indirect addressing mode, user can select three of supported indirect addressing mode: - Simple indirect: the indirect address comes from concatenated IRP and FSR. - Indirect with post increment: the content of FSR register is post incremented, after execution of any instruction using indirect addressing mode. - Indirect with post decrement: the content of FSR register is post decremented, after execution of any instruction using indirect addressing mode. A simple program to clear RAM locations 20H-2FH using indirect addressing is shown in Example 2-1. EXAMPLE 2-1: INDIRECT ADDRESSING MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM NEXT: CLRF CONFIG ;clear CONFIG register INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next CONTINUE: : ;yes continue 24 SEP.2007 VER 1.0

NOTES SEP.2007 VER 1.0 25

3. INTERRUPT 3.1 INTERRUPT STRUCTURE The MC71PD506 has 18 interrupt sources: - 12 external interrupts (Port 0.4~Port 0.7, Port 1.0~Port 1.7) - Watchdog timer interrupt - Timer 0 underflow interrupt - Timer 1/A underflow interrupt - Timer B underflow interrupt - Real timer interrupt - SI interrupt The interrupt vector address is located at 0004H of ROM address area. Please be careful not to overwrite any of the stored vector addresses. P0.4 External Interrupt PND0 INT0 P0.5 External Interrupt PND1 INT1 P0.6 External Interrupt PND2 INT2 P1.0 ExternalInterrupt P1.1 ExternalInterrupt P1.2 External Interrupt P1.3 External Interrupt P1.4 ExternalInterrupt P1.5 ExternalInterrupt P1.6 ExternalInterrupt P1.7 ExternalInterrupt P0.7 External Interrupt PND4 PND5 PND6 PND7 PND8 PND9 PND10 PND11 Watchdog Timer Interrupt PND3 INT3 INT45 INT67 INT89 INT1011 WTPND WTIE GIE Power-down Release Interrupt Vector 0004H Timer 0 Interrupt T0PND T0IE Timer 1/A Interrupt TAPND TAIE Timer B Interrupt TBPND TBIE Real Timer Interrupt RTPND RTIE SI Interrupt SIPND SIIE Figure 3-1. Interrupt Structure 26 SEP.2007 VER 1.0

The interrupt control registers, INTCON, EINT0 and EINT1 have enable bit of individual interrupt, and INTCON has global interrupt enable bit. The interrupt pending registers, IPND, EPND0 and EPND1 record individual interrupt requests in corresponding bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When GIE bit is set, and an interrupt s pending bit and interrupt enable bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in the INTCON, EINT0 or EINT1. The watchdog timer interrupt, timer 0 underflow interrupt, timer 1/A underflow interrupt, timer B underflow interrupt, real timer interrupt, and SI interrupt control bits are contained in the INTCON register and their corresponding interrupt pending bits are in the IPND register. 12 external interrupts are contained in the EINT0 and EINT1 registers and their corresponding interrupt pending bits are in the EPND0 and EPND1 registers. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupts, the return address is pushed onto the stack and the PC is loaded with vector address 0004H. At the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt pending bits. The interrupt pending bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. SEP.2007 VER 1.0 27

3.2 SAVING KEY REGISTERS DURING AN INTERRUPT SERVICE During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers like W register or STATUS register during an interrupt. This will have to be implemented in software. Ex 3-1) shows how to store and restore the STATUS, W, and PCLATH registers. The register, W_TEMP, must be defined in each bank at the same offset from the bank base address. The example: 1) Stores the W register. 2) Stores the STATUS register in bank 0. 3) Stores the PCLATH register. 4) Executes the Interrupt Service Routine code. 5) Restores the PCLATH register. 6) Restores the STATUS and W registers. EX 3-1) SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS, W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP, RP1, RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page : :(Interrupt Service Routine) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP, W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP, F ;Swap W_TEMP SWAPF W_TEMP, W ;Swap W_TEMP into W 28 SEP.2007 VER 1.0

NOTES SEP.2007 VER 1.0 29

INSTRUCTION SET MC71PD506 4. INSTRUCTIONS SET Each MC71PD506 instruction has 14-bit word length divided into an OPCODE, which specifies the instruction type and operands. The instruction set is grouped into the three basic categories: - Byte-oriented operations - Bit-oriented operations - Literal and control operations Figure below shows three general formats that the instruction can have. Byte-oriented file register operations 13 8 7 6 OPCODE d f(file#) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b(bit#) f(file#) 0 b = 3-bit bit address f = 7-bit file register address Literal and Control operation 13 8 7 0 OPCODE k(literal) k = 8-bit immediate value CALL and GOTO 13 11 10 0 OPCODE k(literal) k = 11-bit immediate value Figure 4-1. General Format of Instructions All instructions are executed within 2 Clock cycles. Except the instructions using indirect addressing mode which are executed within 4 CLK periods (two instruction cycles). 30 SEP.2007 VER 1.0

Field f W b k Table 4-1. Opcode Filed Descriptions Description Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label x Don't care location (=0 or 1) d Destination selected; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 label TOS PC PCLATH GIE WDTCNT nto npd destination Register file address (0x00 to 0x7F) Label name Top of Stack Program Counter Program Counter High Latch Global Interrupt Enable bit Watchdog Timer Counter Time-out bit Power-down bit Destination either the W register or the specified register file location SEP.2007 VER 1.0 31

4.1 INSTRUCTION SET SUMMARY 4.1.1 BYTE-ORIENTED INSTRUCTIONS Table 4-2. Byte-Oriented Operations Mnemonic, 14-bit opcode Description operands MSB LSB Status Cycles ADDWF f, d Add W and f 0 0 0 1 1 1 d f f f f f f f C, DC, Z 2 d Add W and (FSR) 0 0 0 1 1 1 d 0 0 0 0 0 0 0 C, DC, Z 4 ANDWF f, d AND W and f 0 0 0 1 0 1 d f f f f f f f Z 2 d AND W and (FSR) 0 0 0 1 0 1 d 0 0 0 0 0 0 0 Z 4 CLRF f Clear f 0 0 0 0 0 1 1 f f f f f f f Z 2 Clear (FSR) 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Z 4 CLRW f, d Add W and f 0 0 0 0 0 1 0 x x x x x x x Z 2 COMF f, d Complement f 0 0 1 0 0 1 d f f f f f f f Z 2 d Complement (FSR) 0 0 1 0 0 1 d 0 0 0 0 0 0 0 Z 4 DECF DECFSZ f, d f, d Decrement f Decrement f, Skip if 0 0 0 0 0 0 0 1 1 1 0 1 1 d f f f d f f f f f f f f f f f Z - 2 2 d d Decrement (FSR) Decrement (FSR), Skip if 0 0 0 0 0 0 0 1 1 1 0 1 1 d 0 0 0 d 0 0 0 0 0 0 0 0 0 0 0 Z - 4 4 INCF INCFSZ IORWF MOVF MOVWF f, d f, d f, d f, d f, d Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 d f f f d f f f d f f f d f f f 1 f f f f f f f f f f f f f f f f f f f f f f f Z - Z Z - 2 2 2 2 2 d d d d Increment (FSR) Increment (FSR), Skip if 0 Inclusive OR W with (FSR) Move (FSR) Move W to (FSR) 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 d 0 0 0 d 0 0 0 d 0 0 0 d 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z - Z Z - 4 4 4 4 4 NOP No Operation 0 0 0 0 0 0 0 x x 0 0 0 0 0-2 RLF RRF SUBWF f, d Rotate Right f through Carry 0 0 1 1 0 0 d f f f f f f f C 2 d Rotate Right (FSR) through Carry 0 0 1 1 0 0 d 0 0 0 0 0 0 0 C 4 f, d f, d Rotate Left f through Carry Subtract W from f 0 0 0 0 1 1 0 1 0 0 1 0 d f f f d f f f f f f f f f f f C C, DC, Z 2 2 d d Rotate Left (FSR) through Carry Subtract W from (FSR) 0 0 0 0 1 1 0 1 0 0 1 0 d 0 0 0 d 0 0 0 0 0 0 0 0 0 0 0 C C, DC, Z 4 2 SWAPF f, d Swap nibbles in f 0 0 1 1 1 0 d f f f f f f f - 2 d Swap nibbles in (FSR) 0 0 1 1 1 0 d 0 0 0 0 0 0 0-2 XORWF f, d Exclusive OR W with f 0 0 0 1 1 0 d f f f f f f f Z 2 d Exclusive OR W with (FSR) 0 0 0 1 1 0 d 0 0 0 0 0 0 0 Z 4 32 SEP.2007 VER 1.0

4.1.2 BIT-ORIENTED INSTRUCTIONS Table 4-3. Bit-Oriented Operations Mnemonic, 14-bit opcode Description operands MSB LSB Status Cycles BCF f, b Bit Clear f 0 1 0 0 b b b f f f f f f f - 2 b Bit Clear (FSR) 0 1 0 0 b b b 0 0 0 0 0 0 0-4 BSF f, b Bit Set f 0 1 0 1 b b b f f f f f f f - 2 b Bit Set (FSR) 0 1 0 1 b b b 0 0 0 0 0 0 0-4 BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 0 1 0 1 1 0 b b 1 1 b b b f f f b f f f f f f f f f f f - - 2 2 b b Bit Test (FSR), Skip if Clear Bit Test (FSR), Skip if Set 0 1 0 1 1 0 b b 1 1 b b b 0 0 0 b 0 0 0 0 0 0 0 0 0 0 0 - - 4 2 4.1.3 LITERAL AND CONTROL OPERATIONS Mnemonic, operands Table 4-4. Literal and Control Operations Description MSB 14-bit opcode LSB Status ADDLW imm Add literal and f 1 1 1 1 1 x k k k k k k k k C, DC, Z 2 ANDLW imm Add literal and f 1 1 1 0 0 1 k k k k k k k k Z 2 CALL imm Call subroutine 1 0 0 k k k k k k k k k k k - 4 CLRWDT - Clear Watchdog Timer 0 0 0 0 0 0 0 1 1 0 0 1 0 0 nto, npd 2 GOTO imm Go to address 1 0 1 k k k k k k k k k k k - 4 IORLW imm Inclusive OR literal with W 1 1 1 0 0 0 k k k k k k k k Z 2 MOVLW imm Move literal to W 1 1 0 0 x x k k k k k k k k - 2 RETFIE - Return from Interrupt 0 0 0 0 0 0 0 0 0 0 1 0 0 1-4 RETLW imm Return with literal in W 1 1 0 1 x x k k k k k k k k - 4 RETURN - Return from subroutine 0 0 0 0 0 0 0 0 0 0 1 0 0 0-4 SLEEP - Go into standby mode 0 0 0 0 0 0 0 1 1 0 0 0 1 1 nto, npd 2 SUBLW imm Subtract W from literal 1 1 1 1 0 x k k k k k k k k C, DC, Z 2 XORLW imm Exclusive OR literal with W 1 1 1 0 1 0 k k k k k k k k Z 2 Cycles SEP.2007 VER 1.0 33

4.2 INSTRUCTIONS DESCRIPTION 4.2.1 ADDLW ADD LITERAL AND W Operands: 0 imm (k) 255 Operation: Status Affected: W <= W + imm (k) C, DC, Z Description: The contents of W register are added to the eight bit immediate data 'imm' and the result is placed in the W register. Encoding: 1 1 1 1 1 x k k k k k k k k Cycles: DIR : 2 Example: ADDLW 0x15 Before Instruction W = 0x10 After Instruction W = 0x25 34 SEP.2007 VER 1.0

4.2.2 ADDWF ADD W AND F Operands: 0 f 127 d [0, 1] Operation: Status Affected: destination <= W + f destination <= W + FSR C, DC, Z Description: ADDWF instruction add contents of the W register with register specified by f operand. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Encoding: 0 0 0 1 1 1 d f f f f f f f 0 0 0 1 1 1 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: ADDWF FSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0XC2 SEP.2007 VER 1.0 35

4.2.3 ANDLW AND LITERAL WITH W Operands: 0 imm (k) 255 Operation: Status Affected: W <= W and imm (k) Z Description: The contents of W register are AND'ed with the eight bit immediate data 'imm'. The result is placed in the W Encoding: 1 1 1 0 0 1 k k k k k k k k Cycles: DIR : 2 Example: ANDLW 0x5F Before Instruction W = 0xA3 After Instruction W = 0x03 36 SEP.2007 VER 1.0

4.2.4 ANDWF AND W WITH F Operands: 0 f 127 d [0, 1] Operation: Status Affected: destination <= W and f destination <= W and FSR Z Description: ANDWF instruction AND the W register with register specified by 'f' operand. The result is stored in W or back in f register respectively to the d value. Encoding: 0 0 0 1 0 1 d f f f f f f f 0 0 0 1 0 1 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: ANDWF FSR, 1 Before Instruction W = 0x17 FSR = 0XC2 After Instruction W = 0X17 FSR = 0x02 SEP.2007 VER 1.0 37

4.2.5 BCF BIT CLEAR F Operands: 0 f 127 0 b 7 Operation: f.b <= 0 FSR.b <= 0 Status Affected: - Description: Encoding: Bit 'b' in register 'f' is cleared. 0 1 0 0 b b b f f f f f f f 0 1 0 0 b b b 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: BCF Flag_Buf, 1 Before Instruction Flag_Buf = 0x17 After Instruction Flag_Buf = 0x16 38 SEP.2007 VER 1.0

4.2.6 BSF BIT SET F Operands: 0 f 127 0 b 7 Operation: f.b <= 1 FSR.b <= 1 Status Affected: - Description: Encoding: Bit 'b' in register 'f' is cleared. 0 1 0 1 b b b f f f f f f f 0 1 0 1 b b b 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: BSF Flag_Buf, 7 Before Instruction Flag_Buf = 0x17 After Instruction Flag_Buf = 0x97 SEP.2007 VER 1.0 39

4.2.7 BTFSC BIT TEST, SKIP IF CLEAR Operands: 0 f 127 0 b 7 Operation: skip if, f.b = 0 skip if, FSR.b = 0 Status Affected: - Description: Check the b bit in f register and skip next instruction when b is 0. If bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. Encoding: 0 1 1 0 b b b f f f f f f f 0 1 1 0 b b b 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: aaa: BTFSC Flag_Buf, 1 bbb: GOTO ccc ddd: Before Instruction After Instruction PC = address aaa If Flag_Buf <1> = 0, PC = address ddd If Flag_Buf <1> = 1, PC = address bbb 40 SEP.2007 VER 1.0

4.2.8 BTFSS BIT TEST, SKIP IF SET Operands: 0 f 127 0 b 7 Operation: skip if f.b = 1 skip if FSR.b = 1 Status Affected: - Description: If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1' then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a twocycle instruction. Encoding: 0 1 1 1 b b b f f f f f f f 0 1 1 1 b b b 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: aaa: BTFSC Flag_Buf, 1 bbb: GOTO ccc ddd: Before Instruction After Instruction PC = address aaa If Flag_Buf<1> = 0, PC = address bbb If Flag_Buf<1> = 1, PC = address ddd SEP.2007 VER 1.0 41

4.2.9 CALL CALL SUBROUTINE Operands: 0 imm (k) 2047 Operation: TOS <= PC + 1, PC [10:0] <= imm (k), PC [12:11] <= PCLATH [4:3] Status Affected: - Description: Call Subroutine. First, return address PC+1 is pushed onto the stack. The eleven bit immediate address is loaded into PC [10:0]. The upper bits of the PC are loaded from PCLATH. CALL is two-cycle instruction. Encoding: 1 0 0 k k k k k k k k k k k Cycles: 4 Example: aaa: CALL bbb Before Instruction PC = address aaa After Instruction PC = address bbb SP = address aaa+1 42 SEP.2007 VER 1.0

4.2.10 CLRF CLEAR F Operands: 0 f 127 Operation: Status Affected: f <= 0x00 FSR <= 0x00 Z Description: Encoding: The contents of register 'f' is cleared and the Z bit in STATUS register is set 0 0 0 0 0 1 1 f f f f f f f 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: CLRF Flag_Buf Before Instruction Flag_Buf = 0xAA After Instruction Flag_Buf = 0x00 SEP.2007 VER 1.0 43

4.2.11 CLRW CLEAR W Operands: - Operation: Status Affected: W <= 0x00 Z Description: The contents of working register W is cleared and the Z bit in STATUS register is set Encoding: 0 0 0 0 0 1 0 x x x x x x x Cycles: 2 Example: CLRW Before Instruction W = 0xAA After Instruction W = 0x00 44 SEP.2007 VER 1.0

4.2.12 CLRWDT CLEAR WATCHDOG TIMER Operands: - Operation: Status Affected: WDTCNT <= Clear nto, npd Description: Encoding: CLRWDT instruction resets the WDTCNT. Status bits nto and npd are set. 0 0 0 0 0 0 0 1 1 0 0 1 0 0 Cycles: 2 Example: CLRWDT Before Instruction WDTCNT =? After Instruction WDTCNT = 0x00 nto = 1 npd = 1 SEP.2007 VER 1.0 45

4.2.13 COMF COMPLEMENT F Operands: 0 f 127 d [0, 1] Operation: Status Affected: destination <= f destination <= FSR Z Description: of the d. Encoding: The contents of register 'f' is complemented and transferred to the destination W or f depending 0 0 1 0 0 1 d f f f f f f f 0 0 1 0 0 1 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: COMF REG1, 0 Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 W = 0xEC 46 SEP.2007 VER 1.0

4.2.14 DECF DECREMENT F Operands: 0 f 127 d [0, 1] Operation: destination <= f 1 destination <= FSR 1 Status Affected: Z Description: d value. Encoding: Decrement register f. The result of operation is stored in the destination W or f depending of the 0 0 0 0 1 1 d f f f f f f f 0 0 0 0 1 1 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: DECF REG1, 1 Before Instruction REG1 = 0x1 Z = 0 After Instruction REG1 = 0x0 Z = 1 SEP.2007 VER 1.0 47

4.2.15 DECFSZ DECREMENT F, SKIP IF 0 Operands: 0 f 127 d [0, 1] Operation: destination <= f 1, Skip if result = 0 destination <= FSR 1, Skip if result = 0 Status Affected: - Description: The contents of register f are decremented and stored in the destination. If the result of operation is 0, the next instruction, which is already fetched, is discarded and NOP is executed instead making it two-cycle instruction. Encoding: 0 0 1 0 1 1 d f f f f f f f 0 0 1 0 1 1 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: aaa: DECFSZ REG1, 1 GOTO aaa bbb: Before Instruction PC = address aaa After Instruction REG1 = REG1 1 If REG1 = 0, PC = address bbb If REG1 0, PC = address aaa + 1 48 SEP.2007 VER 1.0

4.2.16 GOTO UNCONDITIONAL BRANCH Operands: 0 imm (k) 2047 Operation: PC [10:0] <= imm (k) PC [12:11] <= PCLATH [4:3] Status Affected: - Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits [10:0]. The upper bits of PC are loaded from PCLATH [4:3]. GOTO is a two-cycle instruction Encoding: 1 0 1 k k k k k k k k k k k Cycles: 4 Example: GOTO Loop After Instruction PC = address Loop SEP.2007 VER 1.0 49

4.2.17 INCF INCREMENT F Operands: 0 f 127 d [0, 1] Operation: destination <= f + 1 destination <= FSR + 1 Status Affected: Z Description: The contents of register f are incremented. The result of operation is stored in the W register or f, depending of the d value. Encoding: 0 0 1 0 1 0 d f f f f f f f 0 0 1 0 1 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: INCF REG1, 1 Before Instruction REG1 = 0xFF Z = 0 After Instruction REG1 = 0x0 Z = 1 50 SEP.2007 VER 1.0

4.2.18 INCFSZ INCREMENT F, SKIP IF 0 Operands: 0 f 127 d [0, 1] Operation: destination <= f + 1, Skip if result = 0 destination <= FSR + 1, Skip if result = 0 Status Affected: - Description: The contents of register f are incremented and stored in the destination. If the result is 0, the next instruction which is already fetched, is discarded, and a NOP is executed instead making it a two-cycle instruction. Encoding: 0 0 1 1 1 1 d f f f f f f f 0 0 1 1 1 1 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: aaa: INCFSZ REG1, 1 GOTO Loop bbb: Before Instruction PC = address aaa After Instruction REG1 = REG1 + 1 If REG1 = 0, PC = address bbb If REG1 0, PC = address aaa + 1 SEP.2007 VER 1.0 51

4.2.19 IORLW INCLUSIVE OR LITERAL WITH W Operands: 0 imm (k) 255 Operation: Status Affected: W <= W OR imm (k) Z Description: register. Encoding: The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W 1 1 1 0 0 0 k k k k k k k k Cycles: 2 Example: IORLW 0x35 Before Instruction W = 0x9A After Instruction W = 0XBF Z = 0 52 SEP.2007 VER 1.0

4.2.20 IORWF INCLUSIVE OR W WITH F Operands: 0 f 127 d [0, 1] Operation: Status Affected: destination <= W OR f destination <= W OR FSR Z Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Encoding: 0 0 0 1 0 0 d f f f f f f f 0 0 0 1 0 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: IORWF REG1 Before Instruction REG1 = 0x13 W = 0x9A After Instruction REG1 = 0X13 W = 0x93 Z = 1 SEP.2007 VER 1.0 53

4.2.21 MOVLW MOVE LITERAL TO W Operands: 0 imm (k) 255 Operation: W <= imm (k) Status Affected: - Description: Encoding: The eight bit immediate data 'imm' is loaded into W register 1 1 0 0 x x k k k k k k k k Cycles: 2 Example: MOVLW 0XAA After Instruction W = 0xAA 54 SEP.2007 VER 1.0

4.2.22 MOVF MOVE F Operands: 0 f 127 d [0, 1] Operation: Status Affected: destination <= f destination <= FSR Z Description: Encoding: The contents of register f are moved to destination dependent of d value. 0 0 1 0 0 0 d f f f f f f f 0 0 1 0 0 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: MOVF REG1, 0 After Instruction W = value in REG1 register Z = 1 SEP.2007 VER 1.0 55

4.2.23 MOVWF MOVE W TO F Operands: 0 f 127 Operation: f <= W FSR <= W Status Affected: - Description: Move data from W register to register 'f'. Encoding: 0 0 0 0 0 0 d f f f f f f f 0 0 0 0 0 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: MOVWF REG1 Before Instruction REG1 = 0x00 W = 0x9A After Instruction REG1 = 0x9A W = 0x9A 56 SEP.2007 VER 1.0

4.2.24 NOP NO OPERATION Operands: - Operation: - Status Affected: - Description: No operation. Encoding: 0 0 0 0 0 0 0 x x 0 0 0 0 0 Cycles: 2 Example: NOP SEP.2007 VER 1.0 57

4.2.25 RETFIE RETURN FROM INTERRUPT Operands: - Operation: PC <= TOS GIE <= 1 Status Affected: - Description: Return from interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON(7)). Encoding: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Cycles: 4 Example: RETFIE After Instruction PC = TOS GIE = 1 58 SEP.2007 VER 1.0

4.2.26 RETLW RETURN WITH LITERAL IN W Operands: 0 imm (k) 255 Operation: PC <= TOS W <= imm (k) Status Affected: - Description: The W register is loaded with eight bit immediate data 'imm'. The program counter is loaded with the return address from the top of stack. Encoding: 1 1 0 1 x x k k k k k k k k Cycles: 4 Example: CALL TABLE TABLE ADDWF RETLW R0 RETLW R1 RETLW R2 PC Before Instruction W = 0x02 After Instruction W = value of R3 SEP.2007 VER 1.0 59

4.2.27 RETURN RETURN FROM SUBROUTINE Operands: - Operation: PC <= TOS Status Affected: - Description: Encoding: Return from subroutine. The stack is POPed and the top of the stack is loaded into the PC. 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Cycles: 4 Example: RETURN After Instruction PC = TOS 60 SEP.2007 VER 1.0

4.2.28 RLF ROTATE LEFT F THROUGH CARRY Operands: 0 f 127 d [0, 1] Operation: C f7 f0 Status Affected: C Description: The contents of register 'f' is rotated one bit to the left through the Carry Flag. Result is stored in to destination respectively to the d value. Encoding: 0 0 1 1 0 1 d f f f f f f f 0 0 1 1 0 1 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: RLF REG1, 0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 SEP.2007 VER 1.0 61

4.2.29 RRF ROTATE RIGHT F THROUGH CARRY Operands: 0 f 127 d [0, 1] Operation: C f7 f0 Status Affected: C Description: The contents of register 'f' are rotated one bit to the right through the Carry Flag. Result is stored in to destination respectively to the d value. Encoding: 0 0 1 1 0 0 d f f f f f f f 0 0 1 1 0 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: RRF REG1, 0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 0111 0011 C = 0 62 SEP.2007 VER 1.0

4.2.30 SLEEP Operands: - Operands: Status Affected: WDTCNT <= Clear nto, npd Description: Status bits nto is set and npd is cleared. WDTCNT is cleared. It will be in STOP mode when CPUCLK.7-.6 value is 10, and the SLEEP instruction is executed. It will be in IDLE mode when CPUCLK.7-.6 value is any values except for 10, and the SLEEP instruction is executed. Encoding: 0 0 1 1 0 0 0 1 1 0 0 0 1 1 Cycles: 2 Example: SLEEP SEP.2007 VER 1.0 63

4.2.31 SUBLW SUBTRACT W FROM LITERAL Operands: 0 imm (k) 255 Operands: Status Affected: W <= imm (k) W C, DC, Z Description: The W register is subtracted (2 complement method) from the eight bit immediate data imm. The result is stored in W register. Encoding: 1 1 1 1 0 x k k k k k k k k Cycles: 2 64 SEP.2007 VER 1.0

4.2.31 SUBLW SUBTRACT W FROM LITERAL(CONTINUED) Example: SUBLW 0x02 Before Instruction W = 1 C =? Z =? After Instruction W = 1 C = 1; result is positive Z = 0 Before Instruction W = 2 C =? Z =? After Instruction W = 0 C = 1; result is zero Z = 1 Before Instruction W = 3 C =? Z =? After Instruction W = 0xFF C = 0; result is negative Z = 0 SEP.2007 VER 1.0 65

4.2.32 SUBWF SUBTRACT W FROM F Operands: 0 f 127 d [0, 1] Operands: Status Affected: destination <= f W destination <= FSR W C, DC, Z Description: Subtract (2's complement method) W register from register 'f'. Result is stored in destination respectively to the value of d. Encoding: 0 0 0 0 1 0 d f f f f f f f 0 0 0 0 1 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 66 SEP.2007 VER 1.0

4.2.32 SUBWF SUBTRACT W FROM F(CONTINUED) Example: SUBWF REG1, 1 Before Instruction REG1 = 3 W = 2 C =? Z =? After Instruction REG1 = 1 W = 2 C = 1; result is positive Z = 0 Before Instruction REG1 = 2 W = 2 C =? Z =? After Instruction REG1 = 0 W = 2 C = 1; result is zero Z = 1 Before Instruction REG1 = 1 W = 2 C =? Z =? After Instruction REG1 = 0xFF W = 2 C = 0; result is negative Z = 0 SEP.2007 VER 1.0 67

4.2.33 SWAPF SWAP NIBBLES IN F Operands: 0 f 127 d [0, 1] Operands: destination [7:4] <= f [3:0], destination [3:0] <= f [7:4] Status Affected: - Description: The upper and lower nibbles of register 'f' are exchanged. Result is stored in destination respectively to the value of d. Encoding: 0 0 1 1 1 0 d f f f f f f f 0 0 1 1 1 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: SWAPF REG1 Before Instruction REG1 = 0xA5 After Instruction REG1 = 0xA5 W = 0x5A 68 SEP.2007 VER 1.0

4.2.34 XORLW EXCLUSIVE OR LITERAL WITH W Operands: 0 imm (k) 255 Operands: Status Affected: W <= imm (k) XOR W Z Description: The Exclusive OR of the contents of W register and 8 bit immediate data is stored in W. Encoding: 1 1 1 0 1 0 k k k k k k k k Cycles: 2 Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction W = 0x1A SEP.2007 VER 1.0 69

4.2.35 XORWF EXCLUSIVE OR W WITH F Operands: 0 f 127 d [0, 1] Operands: Status Affected: destination <= W XOR f destination <= W XOR FSR Z Description: value of d. Encoding: Exclusive OR the W register with register 'f'. Result is stored in destination respectively to the 0 0 0 1 1 0 d f f f f f f f 0 0 0 1 1 0 d 0 0 0 0 0 0 0 Cycles: DIR : 2 INDIR : 4 Example: XORWF REG1 Before Instruction REG1 = 0xAF W = 0xB5 After Instruction REG1 = 0x1A W = 0xB5 70 SEP.2007 VER 1.0

NOTES SEP.2007 VER 1.0 71

5. CLOCK CIRCUIT The MC71PD506 microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware is operated on system clock frequency supplied through these circuits. The maximum CPU clock frequency of the MC71PD506 is determined by CPUCLK register settings. 5.1 SYSTME CLOCK CIRCUIT The system clock circuit has the following components: - External crystal, ceramic resonator, RC oscillation, or an external clock source - Oscillator stop and wake-up functions - Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) - CPU clock control register, CPUCLK - Oscillator select register, OSCSEL 72 SEP.2007 VER 1.0

5.1.1 MAIN OSCILLATOR CIRCUITS XIN XOUT C1 C2 Figure 5-1. Crystal/Ceramic Oscillator (fx) XIN XOUT Figure 5-2. External Oscillator (fx) XIN XOUT R Figure 5-3. RC Oscillator (fx) NOTE: fx means main oscillator clock. SEP.2007 VER 1.0 73

5.1.2 SUB OSCILLATOR CIRCUITS XTIN XTOUT C1 C2 Figure 5-4. Crystal Oscillator (fxt) XTIN XTOUT Figure 5-5. External Oscillator (fxt) NOTE: fxt means sub oscillator clock. 74 SEP.2007 VER 1.0