RAM (1A) Young Won Lim 11/12/13

RAM (1A) Young Won Lim 11/12/13

opyright (c) 2011-2013 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-over Texts, and no Back-over Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave. Young Won Lim 11/12/13

Block Diagram of a Unit Input n-bit word n-bit word Read Unit 2 k words n-bit per word Output n-bit word 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 2 4 words RAM (1A) 3

ontrol Lines Input n-bit word Read Unit 2 k words n-bit per word Enable 1 1 1 0 Read Output n-bit word RAM (1A) 4

Address & Data Buses n-bit Mem_En Input n-bit word Unit 2 k words n-bit per word Address Bus Data Bus 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PU 2 4 words RD/WR WR Output n-bit word n-bit Data Bus Address Bus RAM (1A) 5

RD & WR Operations Input n-bit word PU n-bit Data Bus WR Mem_En RD/WR Unit 2 k words n-bit per word Address Bus PU RD Output n-bit word n-bit Data Bus Address Bus RAM (1A) 6

ycle Input n-bit word PU WR Mem_En RD/WR Unit 2 k words n-bit per word n-bit Data Bus Address Bus 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output n-bit word n-bit 2 4 words lock Address Enable Data PU Initiating WR op PU Valid Address Latch Data Valid Data RAM (1A) 7

Read ycle Input n-bit word PU RD Mem_En RD/WR Unit 2 k words n-bit per word n-bit Data Bus Address Bus lock 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output n-bit word n-bit 2 4 words Address Enable Data PU Initiating RD op Valid Address Valid Data PU RAM (1A) 8

Example 2-bit addr 4-bit word PU 00 01 10 11 0101 1100 n-bit Data Bus Address Bus WR 0111 01 lock 2-bit addr 00 01 10 11 4-bit word 0101 0111 ` 1100 Address Enable Data Initiating WR op PU 01 PU 0111 Latch Data RAM (1A) 9

Read Example 2-bit addr 4-bit word PU 00 01 10 11 0101 1100 n-bit Data Bus Address Bus RD? 10 lock Address PU 10 Enable Initiating RD op Data 1100 PU RAM (1A) 10

Selecting a Word ed 4-bit word 2-bit 4-bit word 00 01 2 4 words 10 11 RAM (1A) 11

Selecting a Word S R = 1 READ op = 0 WRITE op RAM (1A) 12

A Map 00 01 10 11 2-bit addr Bit 3 Bit 2 Bit 1 Bit 0 RAM (1A) 13 4-bit word

4x4 2-bit 4-bit word 00 01 0101 S 10 11 1100 R = 1 READ op = 0 WRITE op 2-bit 00 4-bit word 0 1 0 1 1 01 10 1 1 0 0 11 RAM (1A) 14

Diagram for a 4x4 2-bit addr 4-bit word I3 I2 I1 I0 A1 word0 B outp ut B outp outp outp ut B ut B ut A0 word1 2 x 4 decoder B outp ut B outp outp outp ut B ut B ut word2 B outp ut B outp outp outp ut B ut B ut word3 B outp ut B outp outp outp ut B ut B ut O3 O2 O1 O0 RAM (1A) 15

ycle Example for a 4x4 WR Address: 01 Data: 0111 Data: 0111 PU 2-bit 4-bit word I3 I2 I1 I0 lock Address Enable Data 4-bit Data Bus 2-bit Bus Initiating WR op PU 01 PU 0111 Latch Data 0111 01 Address: 01 A0 A1 word0 word1 2 x 4 decoder word2 word3 O3 O2 O1 O0 Data & Address Buses Output (RD) Data Bus Data: 0111 Input (WR) RAM (1A) 16

Bi-directional Data Bus PU n-bit Data Bus Address Bus RAM (1A) 17

From PU to WR PU n-bit Data Bus Address Bus RD RAM (1A) 18

From to PU RD PU n-bit Data Bus Address Bus RAM (1A) 19

2 to 4 Decoder 2 x 4 decoder : 4 AND gates 10 x 1024 decoder : 1024 AND gates 4 x 16 decoder : 16 AND gates RAM (1A) 20

oincidence Decoder 10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 n-bit word 2 4 words 1024 5 x 32 10 x 1024 5 x 32 10 1024 404 01100 10110 n-bit word RAM (1A) 21

8x256 Decoder Register Time Sharing Address Bus 16 Input n-bit word AS Register Read Unit 2 k words n-bit per word RAS 8x256 Decoder 8 x 256 Output n-bit word PU 8-bit RD n-bit Data Bus Address Bus 8 x 256 Raw Address ol Address RAM (1A) 22

References [1] http://en.wikipedia.org/ [2] M. M. Mano,. R. Kime, Logic and omputer Design Fundamentals, 4 th ed. [3] D.M. Harris, S. L. Harris, Digital Design and omputer Architecture Young Won Lim 11/12/13