Verilog HDL: Behavioral Counter This example describes an 8-bit loadable counter with count enable. The always construct, highlighted in red text, describes how the counter should behave. behav_counter.v module behav_counter( d, clk, clear, load, up_down, qd); // Port Declaration input [7:0] d; input clk; input clear; input load; input up_down; output [7:0] qd; reg [7:0] cnt; assign qd = cnt; always @ (posedge clk) if (!clear) cnt = 8'h00; if (load) cnt = d; if (up_down) cnt = cnt + 1; cnt = cnt - 1; Verilog HDL: Parameterized Counter This example shows how to instantiate an LPM function in Verilog HDL. In this case, an LPM_COUNTER is instantiated using the aclr, clock, and q ports. The parameter values are set with the keyword defparam, as shown in red text. Both the port mapping and the parameter names are referred to by the period (.) operator after the variable name. In this case, the variable is u1. check_lpm.v module check_lpm ( clk, reset, q); // Port Declaration input clk; input reset; output [7:0] q; lpm_counter u1 (.aclr(reset),.clock(clk),.q(q)); defparam u1.lpm_width= 8; defparam u1.lpm_direction= "UP";
Verilog HDL: Synchronous State Machine This is a Verilog example that shows the implementation of a state machine. The first CASE statement defines the outputs that are depent on the value of the state machine variable state. The second CASE statement defines the transitions of state machine and the conditions that control them. statem.v module statem(clk, in, reset, out); input clk, in, reset; output [3:0] out; reg [3:0] out; reg [1:0] state; parameter zero=0, one=1, two=2, three=3; always @(state) case (state) zero: out = 4'b0000; one: out = 4'b0001; two: out = 4'b0010; three: out = 4'b0100; default: out = 4'b0000; case always @(posedge clk or posedge reset) if (reset) state = zero; case (state) zero: state = one; one: if (in) state = zero; state = two; two: state = three; three: state = zero; case
Verilog HDL: Tri-State Instantiation This simple example shows how to instantiate a tri-state buffer in Verilog HDL using the keyword bufif1. The output type is tri. The buffer is instantiated by bufif1 with the variable name b1. tristate.v module Tristate (in, oe, out); input in, oe; output out; tri out; bufif1 b1(out, in, oe); Verilog HDL: Bidirectional Pin This example implements a clocked bidirectional pin in Verilog HDL. The value of OE determines whether bidir is an input, feeding in inp, or a tri-state, driving out the value b. bidir.v module bidirec (oe, clk, inp, outp, bidir); // Port Declaration input oe; input clk; input [7:0] inp; output [7:0] outp; inout [7:0] bidir; reg [7:0] a; reg [7:0] b; assign bidir = oe? a : 8'bZ ; assign outp = b; // Always Construct always @ (posedge clk) b <= bidir; a <= inp;
Instantiating a DFFE This example describes how to generate a D flipflop with enable (DFFE) behaviorally with asynchronous preset and reset signals. Both the preset and reset signals are active low, controlling the output of the DFFE whenever either signal goes low. dffeveri.v module dffeveri (q, d, clk, ena, rsn, prn); // port declaration input d, clk, ena, rsn, prn; output q; reg q; always @ (posedge clk or negedge rsn or negedge prn) //asynchronous active-low preset if (~prn) if (rsn) q = 1'b1; q = 1'bx; //asynchronous active-low reset if (~rsn) q = 1'b0; //enable if (ena) q = d; Verilog HDL: Instantiating MAX+PLUS II Primitives This example describes how to instantiate MAX+PLUS II primitives in Verilog HDL. It instantiates a simple D-type flip-flop, an LCELL primitive, and an open-drain pin. vprim.v module vprim (indata, outdata, clock); input output reg indata, clock; outdata; out_dff, out_lcell; dff d1(.d(indata),.q(out_dff),.clk(clock)); lcell l1(.in(out_dff),.out(out_lcell)); opndrn o1(.in(out_lcell),.out(outdata));
The vprim.v design would look like the following diagram if done in schematic format: Verilog HDL: Parameterized RAM with Separate Input & Output Ports This example shows how to instantiate a memory block using the LPM function lpm_ram_dq. The variable ram uses the lpm_ram_dq function from the LPM library. The ports are initially defined and then mapped to the LPM ports, as shown in red text. The parameter values are then passed through with the keyword defparam. In this example, a 16 x 256 RAM block is instantiated; you can use a similar process to instantiate RAM blocks of other sizes. The lpm_file parameter refers to the Memory Initialization File (.mif) that specifies the initial content of a memory block (RAM or ROM). An MIF is an ASCII text file can be created manually or saved from the output of a simulation. In an MIF, you are required to specify the memory depth and width values and optionally you can specify the radixes used to display and interpret addresses and data values. These values are shown in red text in the extract from the sample file, map_lpm_ram.mif, which is included below. An MIF is used as an input file for memory initialization in the MAX+PLUS II Compiler and Simulator. RAMveri.v // instantiation of lpm_ram_dq, 16-bit data, 256 address location module map_lpm_ram (dataout, datain, addr, we, inclk, outclk); // port instantiation input [15:0] datain; input [7:0] addr; input we, inclk, outclk; output [15:0] dataout; // instantiating lpm_ram_dq lpm_ram_dq ram (.data(datain),.address(addr),.we(we),.inclock(inclk),.outclock(outclk),.q(dataout)); // passing the parameter values defparam ram.lpm_width = 16; defparam ram.lpm_widthad = 8; defparam ram.lpm_indata = "REGISTERED"; defparam ram.lpm_outdata = "REGISTERED"; defparam ram.lpm_file = "map_lpm_ram.mif";
----------------------------------------------------------------------------- Extract from the MIF file Download map_lpm_ram.mif WIDTH = 16; DEPTH = 256; ADDRESS_RADIX = HEX; DATA_RADIX = HEX; CONTENT BEGIN 0 : ffff; 1 : 0000; 2 : bbf3; 3 : 0000; 4 : 0000;... fb : 0000; fc : 0000; fd : 0000; fe : 0000; ff : 0000; END;