Cyclone V SoC Dev Kit User Guide Rev 1.5 02/06/2013 Mini-USB 2.0 On-Board USB Blaster TM II & USB Interface LED (3:0) DIPSW (3:0) PB (3:0) USB2 OTG UART CAN LTC Power I2C Header Real-Time Clock 1024MB DDR3 + ECC Buttons Switches LED 50M / 100M Fixed OSC 10/100 Ethercat 10/100 Ethercat REFCLK VCXO JTAG Chain 9 Blaster Accelerator Bus 0 x6 x8 x8 I2C 0 0 SDI Video Control Port Character LCD LTC Power Monitor 1024MB DDR3 + ECC 128MB QSPI FLASH SD Card Socket GigE PHY LTC SPI Exp Header ADDR 6 x8 Config XCVR x80 CLKIN x3 CLKOUT x3 XCVR x8 XCVR 128MB NOR FLASH CPLD Port A SDI SMA
1.1. Board Setup 1.1.1. Board-Specific DIP Switch Settings Figure 1 shows the switches, jumpers, and connectors used in configuring the Cyclone V SoC dev kit over the JTAG chain. JTAG HPS SEL J6 Clock/Security switch SW2 MSEL switch SW3 JTAG Enable SW4 9V Flash J5 Mictor J4 JTAG SEL J8 OSC1 CLK SEL J13 Figure 1 USB Blaster J24 USB Blaster II J37 CLK_SEL 0,1 BOOT_SEL 1,0,2 J26,J27,J28,J29,J30 JTAG MIC SEL J15 The JTAG chain for the Cyclone V SoC dev kit is shown in the figure 2 on the following page. The dev kit can be programmed in the following configurations:
1) Source: USB Blaster (J24) Destination: HPS FPGA HSMA MAX II (with option to bypass any item in the chain 2) Source USB Blaster II (J37) Destination: HPS FPGA HSMA MAX II (with option to bypass any item in the chain) 3) Concurrent Configuration 1: a. Source 1: USB Blaster (J24) Destination: FPGA HSMA MAX II (with option to bypass any item in the chain) b. Source 2 Mictor (J4) Destination: HPS 4) Concurrent Configuration 2: a. Source 1: USB Blaster II (J37) Destination: FPGA HSMA MAX II (with option to bypass any item in the chain) b. Source 2 Mictor (J4) Destination: HPS Figure 2
If the Cyclone V SoC dev kit is to be programmed under configuration 1 or 2 with all items in the chain then set the switches as shown in Tables 1, 2 and 3. Table 1 SW3 MSEL Strapping Pins Switch Name Description Switch Setting* MSEL0 FPGA Configuration Strapping Pin 0 SW3.1 ON MSEL1 FPGA Configuration Strapping Pin 1 SW3.2 ON MSEL2 FPGA Configuration Strapping Pin 2 SW3.3 OFF MSEL3 FPGA Configuration Strapping Pin 3 SW3.4 ON MSEL4 FPGA Configuration Strapping Pin 4 SW3.5 OFF n/a n/a SW3.6 n/a *ON is the switch in the UP position. OFF is in the DOWN position Table 2 SW4 JTAG Chain Control Switch Name Description Switch Setting** HPS_JTAG_EN HPS JTAG Enable (ON = Bypass) SW4.1 OFF FPGA_JTAG_EN FPGA JTAG Enable (ON = Bypass) SW4.2 OFF HSMA_JTAG_EN HSMC JTAG Enable (ON = Bypass) SW4.3 ON MAX_JTAG_EN MAX CPLD JTAG Enable (ON = Bypass) SW4.4 OFF JTAG_MIC_SEL TRST on JTAG 10 HDR or MICTOR TRST J15 ON JTAG_HPS_SEL HPS in full chain or only connect HPS to Mictor J6 ON JTAG_SEL JTAG 10 HDR or Mictor JTAG source J8 ON **ON is the switch in the UP position. OFF is in the DOWN position Table 3 - Clock and Security Control Switch Name Description Switch Setting*** CLK125A_EN SW2.1 OFF Si570_EN SW2.2 OFF FACTORY_LOAD SW2.3 OFF SECURITY_MODE SW2.4 OFF OSC1_CLK_SEL ON selects the on board 25MHz clock / OFF selects SMA ***ON is the switch in the LEFT position. OFF is in the RIGHT position J13 ON If the Cyclone V SoC dev kit is to be programmed under configuration 3 or 4 then alter the settings in table 1, 2, and 3 in the following manner: A) Remove the shunt on J6. B) Remove the shunt on J15 C) Be sure that SW4.1 for HPS_JTAG_EN is in the ON position.
1.1.2. User DIP Switch Settings Table 4 - User DIP Switch Switch Name Description Switch Setting USER_DIPSW_HPS0 HPS User DIP 0 SW1.1 N/A USER_DIPSW_HPS1 HPS User DIP 1 SW1.2 N/A USER_DIPSW_HPS2 HPS User DIP 2 SW1.3 N/A USER_DIPSW_HPS3 HPS User DIP 3 SW1.4 N/A USER_DIPSW_FPGA0 FPGA User DIP 0 SW1.5 N/A USER_DIPSW_FPGA1 FPGA User DIP 1 SW1.6 N/A USER_DIPSW_FPGA2 FPGA User DIP 2 SW1.7 N/A USER_DIPSW_FPGA3 FPGA User DIP 3 SW1.8 N/A 1.1.3. Jumper Settings Jumper Name Description Ref Des Setting 9V Test circuit (DO NOT USE or JUMPER) J5 OFF JTAG_HPS_SEL HPS in full chain or only connect HPS to Mictor J6 ON JTAG_SEL JTAG 10 HDR or Mictor JTAG source J8 ON UART NOT A JUMPER Just TX and RX brought to header J9 OFF OSC1_CLK_SEL ON = On-board OSC HPS, OFF = SMA input HPS J13 ON JTAG_MIC_SEL ON = TRST from Blaster, OFF = TRST from MICTOR J15 OFF SPI I2C I2C or SPI bus connection to LTC expansion header J31 OFF
Jumper Name Description Ref Des Setting CLKSEL0 J26 2-3 CLKSEL1 J27 2-3 BOOTSEL0 J28 2-3 BOOTSEL1 J29 2-3 BOOTSEL2 J30 1-2
1.1.4. Clock Control An application is provided in the installer package under examples\board_test_system called ClockControl.exe that can program the on-board oscillators Si570 (X2), Si571 (X3), and Si5338 (U29). This application requires 12.1.X be installed on the user s PC and set as the current version via environment variable $QUARTUS_ROOTDIR. One way to do this is to launch this version of Quartus II (32bit is more reliable to set this apparently). Make sure the board is plugged in via JTAG and the Max CPLD is programmed with the POF found in the installer examples/max directory (should be preprogrammed). 1.1.5. SD Card Programming To program an SD card linux image you can use dd on a linux machine, or on a windows machine, you can use a tool called Win32DiskImager.exe. A copy of this is located in demos/autodemo.zip under the zip s autodemo/tools/imagewriter directory. Most images are 2GB once expanded. Make sure the jumper are set to the defaults to boot the image from this source.
1.1.6. USB UART Bridge The Cyclone V SoC Devkit has a USB UART bridge device from Silicon Labs part number CP2104-F03-GM. To use this device you need to install a driver from SI Labs and associate your favorite terminal program s connection to the virtual COM port (on Windows machines). This is often a higher number than those already on your PC (e.g. COM5 or COM6) and can vary by system and sometimes each time you connect. Set the UART for 57600bps 8N1. Drivers can be found at the address below: http://www.silabs.com/products/mcu/pages/softwaredownloads.aspx. 1.1.7. Max System Controller CPLD The Max CPLD currently supports the ClockControl.exe oscillator control block for Si570 (X2), Si571 (X3), and Si5338 (U29). The Max CPLD also support the Parallel Flash Programmer (PFL) Megafunction for FPGA programming via fast-passive parallel (FPP). For this to work the DIP switch SW3 needs to be set to the defaults shown in this document. You can create a custom flash.pof file for programming into this CFI flash following the PFL documentation on www.altera.com. This Max CPLD image PFL implementation supports uncompressed images for CFI flash with an option bits address offset of 08000. This Max CPLD will also support a power monitor function in a future release.
Below is a summary of the clocks. Note that the rev A and B builds SDI clock is slightly off the typical US frequency of 148.5MHz (board had 148M clock) use the ClockControl GUI to set for proper operation. Measured Clock Signal Location io standard Frequency REFCLK_QL2_P C21 2.5V LVDS REFCLK_QL2_N C20 2.5V LVDS CLK_148_P C61 2.5V LVDS CLK_148_N C64 2.5V LVDS PCIE_REFCLK_QL0_P R255 HCSL PCIE_REFCLK_QL0_N R256 HCSL PCIE_REFCLK_SYN_P R251 HCSL PCIE_REFCLK_SYN_N R252 HCSL CLK_ENET_FPGA_P U22.Y26 2.5V LVDS CLK_ENET_FPGA_N U22.Y27 2.5V LVDS CLK_OSC1 R553 3.3V LVCMOS CLK_OSC2 U22.F25 3.3V LVCMOS CLK_BOT1 R451 2.5V TO 1.5V LVCMOS CLK_TOP1 U22.AA26 2.5V LVCMOS CLK_50M_MAX R78 1.8V LVCMOS CLK_50M_FPGA R71 1.8V LVCMOS CLK_100M_MAX R466 2.5V LVCMOS CLK_100M_FPGA R468 2.5V LVCMOS CLKIN_100MHZ U36.2 2.5V LVCMOS