AIAO-0700 3U CompactPCI Analog I/O Card User Manual 13 Altalef St. Yehud, Israel 56216 Tel: 972 (3) 632-0533 Fax: 972 (3) 632-0458 www.tenta.com 919 Kifer Road Sunnyvale, CA 94086 USA Tel: (408) 328-1370 Fax: (408) 328-1371
Document Revision Control Revision Comment BY Date E2.0 Release LL, AF, RH 11/11/99 E2.3 Review and corrections JR 03/10/00 E2.4 Add product revisions table and new format DG 06/06/01 E2.5 Revision table update DG 07/29/01 E3.0 Updated document format TJ 01/02/02 AIAO-0700 User Manual Page 2 of 19
Table of Contents I. Introduction...4 II. Ordering Information...5 III. Specifications...6 A. Physical specifications... 6 B. Environmental specifications... 6 C. Functional Specifications... 7 D. Power Specifications... 7 E. Analog Input Specifications... 8 F. Analog Output Specifications... 10 G. Watchdog timer... 12 H. J2 Signals... 12 IV. Test Procedure...17 V. Block diagram...13 VI. I/O Address Map...14 VII. On Request Built in test (ORB)...15 VIII. Register Definition...16 IX. Product Revision History...18 X. Warranty...19 AIAO-0700 User Manual Page 3 of 19
I. Introduction This document describes the specifications and functionality of Tenta s AI/O board 3U CompactPCI form factor. This board was designed as general-purpose data acquisition board suitable for automatic test, measurement and analysis applications. The board is comprised of 32 single ended analog inputs and 16 analog outputs with 12-bit resolution. Analog circuitry is isolated optically from the CompactPCI signals and power. The board form factor, physical dimension and BUS interface comply with CompactPCI Specification PICMG 2.0 R2.1. The I/O and power signals are distributed through J2 rear connector. The board complies with Y2K requirements. AIAO-0700 User Manual Page 4 of 19
II. Ordering Information Part Number AS00700-02 Description Analog I/O card, 32 inputs, 16 outputs, 3U cpci AIAO-0700 User Manual Page 5 of 19
III. Specifications A. Physical specifications Criteria PCB Dimensions Form Factor Connectors Front Panel Weight Specifications 100mm (3.9370 ) Height X 160mm (6.2992 ) Depth X 1.6mm (0.0629 ) Thickness Plug in Euro card, 3U Height, 8 HP Width (1 slot), IEEE (1101.1, 101.10 and P1101.11) Metric 2.0mm grid, female connector type A is used for J1 (cpci BUS) and J2 (Signal distribution). 128.5mm Height X 20.32mm Depth X 2.5 mm Thickness. 200g B. Environmental specifications Criteria Operating temperature Storage temperature Humidity Specifications 0-70 ºC -40 to +85 ºC 5 to 95% non-condensing AIAO-0700 User Manual Page 6 of 19
C. Functional Specifications Criteria Analog In/Out BUS interface Plug and Play On Request Built in test Front Panel Indicators Watchdog timer Protection circuitry Specifications Isolated 32 single Inputs / 16 outputs Compact PCI, 32 bit (16 bit data transfer) 33MHz Support auto recognition of the board on power-on includes device ID, Vendor ID and configuration registers. ORB loop comprehensive self-test. RUN (HB), Power LEDS (PCI, Analog Power) Disable outputs (set all outputs to Zero) on timeout 0.2A poly-fuse and a suppression diode on each analog output. D. Power Specifications Criteria Digital Section Power Supply Analog Section Power Supply Specifications +3.3VDC@ 20mA, +5VDC@ 1.36mA from J1 +/-15V@ 200mA max from on board 6W DC to DC converter AIAO-0700 User Manual Page 7 of 19
E. Analog Input Specifications The analog input channels are decoded as follows: Bipolar channels are read as 12 bit integer, two s complement notation: Unipolar channels are read as 12 bit unsigned integers. The resolution (value of the lowest significant bit) for both cases is R = 10V/4096 = 2.44mV. Bipolar 12 Bit Input Stream Read Voltage 000 0V 7FF 5V 800-5V FFF -2.44mV Unipolar 12 Bit Input Stream Read Voltage 000 0V 7FF 5V 800 5.00244V FFF 9.99776V AIAO-0700 User Manual Page 8 of 19
Criteria Specifications Number of 32 single ended inputs channels Range 0.00 to +10.00V (Unipolar inputs) or - 5.00V to +5.00V (Bipolar), software selectable for each input Isolation 100V Min. between Analog sense inputs and CompactPCI bus section. No Isolation between Analog inputs and outputs channels. Impedance 10 k-ohm min @10V input Overall Accuracy +/-0.1% FS max. Corrected error, @ 25 C, +/- 0.2% FS max over full operating temp range. Zero volt ±2.5 mv max. @25 C, ±5 mv max. accuracy Over full operating temp range Offset Trim Internal calibration circuit (Factory setting) Gain Trim Internal calibration circuit (Factory setting) Low pass input 100Hz Noise reduction filter for each filter input Cross-talk 80 db minimum below 10 Hz A/D conversion 12-bit (Option for 16-bit) resolution A/D conversion 2.44 mv/bit @12 bit resolution. Gain A/D conversion Less than 100µsec for single input. time A/D conversion Max 0.05 LSB per 1 % change in Sensitivity internal supply. S/N ratio 65 db min AIAO-0700 User Manual Page 9 of 19
F. Analog Output Specifications An application interfacing to the AIO700 analog channels (ports) through the AIO700 driver should be able to access and configure each I/O port independently. The analog output values are decoded as follows: N = (V+10)*4096/20 Desired Output Voltage Required Output 12 Bit Stream -10V 000 +9.995V FFF 0V 800 AIAO-0700 User Manual Page 10 of 19
Criteria Number of channels Range Isolation Output Current: Bipolar Zero offset Overall Accuracy Zero Trim Gain Trim Ripple Settling Time Output Slew Rate Cross talk D/A Conversion resolution D/A Conversion gain D/A Conversion Time D/A Conversion update rate Reset State (Watch Dog) Power Up State Load Impedance Specifications 16 single ended outputs ±10VDC nominal 100V Min. between Analog outputs and CompactPCI bus section. No Isolation between Analog output and input channels. Max. +/- 5 ma. ±2.5 mv max. @25 C, ±5 mv max. over full operating temp range +/-0.1% FS max. Corrected error, @ 25 C, +/- 0.2% FS max over full operating temp range Internal calibration circuit (Factory setting) Internal calibration circuit (Factory setting) Max 1 mv peak to peak @ 500 Hz Max 2 msec 2V/µsec Max 1mV 12-bit 4.88 mv/bit @ 12-bit Max 100µsec Min 500 Hz for all 16 channels Zero Volts on all outputs. Zero Volt on power on Min. 2k Ohm, Typical 10k Ohm less than 1000 pf AIAO-0700 User Manual Page 11 of 19
G. Watchdog timer The Watchdog timer insures that the AI/O board communication with the SBC is alive. The watchdog timer must be reset periodically with the interval configured by software. If a time-out occurs, all analog outputs are set to zero volts. On time-out the watchdog timer latches on watchdog fail state until it is initialized by the SBC. On board jumper (JP3), allows to by-pass this feature (for debugging purposes). H. J2 Signals Z A B C D E F 22 GND Reserved Reserved Reserved Reserved Reserved GND 21 GND +15V 15Vcom (Spare) -15V 15Vcom GND 20 GND AO 0 AO 1 AO 2 AO 3 AO 4 GND 19 GND AO 5 AO 6 AO 7 AO 8 AO 9 GND 18 GND AO 10 AO 11 AO 12 AO 13 AO 14 GND 17 GND Sig. Com Sig. Com Sig. Com Sig. Com Sig. Com GND 16 GND AO 15 AI 0 AI 1 AI 2 AI 3 GND 15 GND AI 4 AI 5 AI 6 AI 7 AI 8 GND 14 GND AI 9 AI 10 AI 11 AI 12 AI 13 GND 13 GND Sig. Com Sig. Com Sig. Com Sig. Com Sig. Com GND 12 GND AI 14 AI 15 AI 16 AI 17 AI 18 GND 11 GND AI 19 AI 20 AI 21 AI 22 AI 23 GND 10 GND AI 24 AI 25 AI 26 AI 27 AI 28 GND 9 GND Sig. Com Sig. Com Sig. Com Sig. Com Sig. Com GND 8 GND AI29 AI 30 AI 31 GND 7 GND GND 6 GND GND 5 GND GND 4 GND 24V 24Vret 24V 24Vret Reserved GND 3 GND Reserved Reserved Reserved Reserved Reserved GND 2 GND Reserved Reserved Reserved Reserved Reserved GND 1 GND 3.3V 3.3V 3.3V 5V 5V GND AIAO-0700 User Manual Page 12 of 19
IV. Block diagram OPTO x2 Busy/Sync Serial Comm. Convert A/D 12 bits MUX 4 INPUT MUXs X4 32 LPF PCI J2 PCI BRIDGE CONTROL LOGIC (DECODING,SERIAL COMM. Heart Bit etc.) OPTO OPTO CS A/D Sync Serial Comm. Isolated Control LOGIC RANGE SELECT CIRCUITRY 1 5-6 REF REFERANCE / GND Loop TEST EEPROM HB RESET OPTO HB RESET QUAD D/A AMP 4 4 BIT LEDS HB POWER OPTO X2 DC to DC CONVERTER Serial Comm. Load ANALOG POWER +/-15V QUAD D/A QUAD D/A QUAD D/A AMP AMP AMP 4 AIAO-0700 User Manual Page 13 of 19
V. I/O Address Map Board base address registers allocate 64 bytes within 32-bit memory space. AIAO-0700 User Manual Page 14 of 19
VI. On Request Built in test (ORB) The AIO700 implements a loop back mechanism to allow on-line testing of the hardware. The board enables to loop some of the analog output (DAC) values and other entities back to the input channels (ADC). The following entities can be tested: Entity Loop back bit (DAC control bit 5) Input Channel (DAC control 0-4) Expected Value AO Channel 0 1 0 Last write to this channel AO Channel 4 1 1 Last write to this channel AO Channel 8 1 2 Last write to this channel AO Channel 12 1 3 Last write to this channel Reference Voltage 1 4 2.5V High GND 1 8 0V AIAO-0700 User Manual Page 15 of 19
VII. Register Definition On power-up or system reset, all on-board control registers are reset to 0. This sets the analog input channel to first channel (0), sets the analog input range to ±5V, and sets all the analog output channels to 0V. Offset Register Description R/W Bit Bit Range Description 0 Reset W 0-31 Reset By writing any value. 4 ADC Control W 0-4 Input Port Number W 5 ORB Request (See ORB mechanism) W 8 Voltage Range, Bipolar = 1, Unipolar = 0 8 ADC Value R 0-11 Input Value R 16-20 Input Channel Number R 21 ORB Indicator R 22 Voltage Range, Bipolar = 1, Unipolar = 0 R 20 BIT Failed Indicator R 24 ADC Busy (Busy = 1, Ready = 0) R 28 Watch Dog Enabled R 29 Reset Occurred (Occurred = 0) R 30-31 Watch dog Time-out interval. 12 DAC Output-Control R/W 0-11 Output Value R/W 12-15 Output Port Number R 16 DAC Busy (Busy = 0, Ready = 1) 16 Watchdog Timer W 0 Watch Dog Enable (Enabled = 1) W 4-5 Watch dog Time-out interval. 100mS = 00 200mS = 01 400mS = 10 800mS = 11 W 8 Report Reset Occurrence (Report = 1) W 12 BIT LED Control AIAO-0700 User Manual Page 16 of 19
VIII. Test Procedure The functionality of all analog outputs and analog inputs are examined by an automatic test procedure (ATP). Each analog output is connected by an external loop back connector to two analog inputs. The automatic test checks the accuracy of each analog I/O, full scale error, offset error and watchdog mechanism. AIAO-0700 User Manual Page 17 of 19
IX. Product Revision History Part Number Rev Functional Change Reason AS00700-01 E1 None -First article Prototype AS00700-01 Functionality same as E2 E1 New PCB AS00700-01 Functionality same as E3 E1 BOM change AS00700-01 Optimization of PCI code Functionality E4 same as E1 Firmware change to 700.20 AS00700-01 Functionality same as E5 E1 BOM change AS00700-01 A RELEASE No change AS00700-01 B N/A N/A Improve Reference Stabilization with Add/Remove components and AS00700-01 C temperature change traces(filtering) AS00700-01 AS00700-02 C1 E1 Improve A/D offset and Gain accuracy; improves manufacturability Implement REV C1 on a new PCB Layout and Improve D/A calibration New PCB Mount Trimmers for A/D Calibration All boards version AS00700-01 Rev. Ex should be discarded. All other boards version AS00700-01 under Rev. C can be returned to Tenta for upgrade. AIAO-0700 User Manual Page 18 of 19
X. Warranty Tenta Technology warrants the original purchaser for two years from the date of delivery for any defect in the product, material or workmanship. Product should be used in suitable installation environment and for the purposes it was designed. Any damages caused by natural disasters such as: fire, flood, wind and lightning are not covered. For more information, please contact Tenta Technology customer support (see locations on front page). Tenta Technology hardware and software are not intended for use in any manner when human life or safety is at risk and not for use in life support equipment. AIAO-0700 User Manual Page 19 of 19