SOC MPEG Decoder Chipset Datasheet System-On-Chip (SOC) Technologies (February 2017) 1 Product Overview The SOC MPEG Codec Chipsets are based on off-the-shelf FPGAs and SOC codec IP cores. The SOC IP cores are prestored into Flash Memories for the target FPGA chip. The FPGA and the pre-configured Flash Memory form the chipset. Customers can purchase both the FPGA and the pre-configured flash memory chip from SOC or purchase the pre-configured flash memory only. In the case of purchasing the pre-configured memory only from SOC, the customer may purchase the target FPGA chips from the FPGA distributors. It should also be noted that an IP core key which is a pre-written (3mmx3mm) one-wire EPROM comes with the flash memory as well for IP protection. Fig. 1 SOC Decoder chipset Fig. 2 SOC Encoder chipset The codec chipsets are available for the following categories: 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 1
1. H.265 video/audio encoders; 2. H.265 video/audio decoders (coming soon); 3. H.264 video/audio encoders; 4. H.264 video/audio decoders; 5. MPEG-2 video/audio encoders; 6. MPEG-2 video/audio decoders; 7. H.264-to-H.265 transcoders; 8. MPEG2-to-H.264 video/audio transcoders; 9. H.264-to-MPEG2 video/audio transcoders; 10. Multiple-channel encoder and/or encoders/decoders; 11. Multiple-standard encoder and/or encoders/decoders. In each of the above categories, a series of standard chips are offered for different applications, from lower-end to high-end. Specifications for standard chips, with different resolutions and frame rates, are provided in Appendix-A Technical and performance details for the encoders, decoders, and transcoders are provided in the Datasheets of the IP cores that are used to configure the chips: Datasheet H.265 Encoder IP Cores Datasheet H.264 Encoder IP Cores Datasheet H.264 Decoder IP Cores Datasheet MPEG-2 Encoder IP Cores Datasheet MPEG-2 Decoder IP Cores Datasheet H.265-to-H.264 Transcoder IP Cores Datasheet MPEG-2-to-H.264 Transcoder IP Cores Datasheet H.264-to-MPEG-2 Transcoder IP Cores User interface for controlling the operations of the chips are provided by the API interface manuals: API Manual - H265 Decoder chipsets API Manual - H264 Encoder chipsets API Manual - H264 Decoder chipsets API Manual MPEG-2 Encoder chipsets API Manual MPEG-2 Decoder chipsets Information for integrating the chips on to user PCBs are provided in this datasheet. SOC also provides PCB design references through its licensing programs. Contact SOC sales for details: sales@soctechnologies.com 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 2
2 Factory Standard Codec Chipsets For each category of the chipsets listed in the previous pages, there are a number of factory standard chipsets according the video resolutions and frame rates. Appendix-A provide the factory standard chipsets as off-the-shelf products in SOC s product offerings. 3 Non-Standard Codec Chipsets Appendix-A provides the information on SOC s factory standard MPEG codec chipsets. Customers can order these chipsets based on the specific requirements as off-the-shelf products. However, SOC also customize the chipset to meet non-standard applications (non-standard chipsets). A one-time engineering fee may apply for customized configurations. Contact SOC sales sale@soctechnologies.com for information. 4 Integrating the Codec Chipsets to a User PCB 4.1 Pin Assignments The decoder pin assignment for Xilinx XC7A200T (Part #: XC7A200T-SBG484/UBGA484) is listed in Table 1. Table 1: Pin Assignment for Xilinx Artix-7 XC7A200T Description Direction FPGA Pin # Voltage IO Standard External Reset Input Y12 3.3v LVCMOS33 SDI Clock Input T5 1.5v LVCMOS15 Video Clock Output Y11 3.3v LVCMOS33 Video Horizontal Sync Output T6 1.5v LVCMOS15 Video Vertical Sync Output AB6 1.5v LVCMOS15 Video Display Enable Output R6 1.5v LVCMOS15 Video Data Luma[0] Output AB16 3.3v LVCMOS33 Video Data Luma[1] Output U18 3.3v LVCMOS33 Video Data Luma[2] Output Y16 3.3v LVCMOS33 Video Data Luma[3] Output AA16 3.3v LVCMOS33 Video Data Luma[4] Output W21 3.3v LVCMOS33 Video Data Luma[5] Output W22 3.3v LVCMOS33 Video Data Luma[6] Output U21 3.3v LVCMOS33 Video Data Luma[7] Output T21 3.3v LVCMOS33 Video Data Luma[8] Output T16 3.3v LVCMOS33 Video Data Luma[9] Output U16 3.3v LVCMOS33 Video Data Chroma[0] Output Y13 3.3v LVCMOS33 Video Data Chroma[1] Output AA14 3.3v LVCMOS33 Video Data Chroma[2] Output N13 3.3v LVCMOS33 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 3
Video Data Chroma[3] Output N14 3.3v LVCMOS33 Video Data Chroma[4] Output AB13 3.3v LVCMOS33 Video Data Chroma[5] Output R18 3.3v LVCMOS33 Video Data Chroma[6] Output AA13 3.3v LVCMOS33 Video Data Chroma[7] Output T18 3.3v LVCMOS33 Video Data Chroma[8] Output AB17 3.3v LVCMOS33 Video Data Chroma[9] Output U17 3.3v LVCMOS33 Video Frame Sync Relock Input Y6 1.5v LVCMOS15 SPDIF Audio Output N20 1.5v LVCMOS15 Transport Stream Clock Input V20 3.3v LVCMOS33 Transport Stream Data Valid Input U6 1.5v LVCMOS15 Transport Stream User Data Valid Input W6 1.5v LVCMOS15 Transport Stream Flash Data Valid Input W5 1.5v LVCMOS15 Transport Stream Data[0] Input M13 1.5v LVCMOS15 Transport Stream Data[1] Input L13 1.5v LVCMOS15 Transport Stream Data[2] Input L15 1.5v LVCMOS15 Transport Stream Data[3] Input L14 1.5v LVCMOS15 Transport Stream Data[4] Input K18 1.5v LVCMOS15 Transport Stream Data[5] Input K19 1.5v LVCMOS15 Transport Stream Data[6] Input K6 1.5v LVCMOS15 Transport Stream Data[7] Input J6 1.5v LVCMOS15 User Data Clock Output U20 3.3v LVCMOS33 User Data Valid Output M20 1.5v LVCMOS15 User Data [0] Output N19 1.5v LVCMOS15 User Data [1] Output N18 1.5v LVCMOS15 Uart_tx Output V5 1.5v LVCMOS15 Uart_rx Input U5 1.5v LVCMOS15 A reference PCB design (design name: MCM-1000A) is provided in Appendix-B. The decoder I/O pins are connected to the edge pins of the MCM-1000A. The connections are listed in Table 2, which can be used as a reference. Table 2: Decoder Module Pin Assignment for MCM-1000A Description MCM-1000A Edge Connector Pin # Direction FPGA Pin # Voltage IO Standard External Reset 107 Input Y12 3.3v LVCMOS33 SDI Clock 159 Input T5 1.5v LVCMOS15 Video Clock 105 Output Y11 3.3v LVCMOS33 Video Horizontal Sync 155 Output T6 1.5v LVCMOS15 Video Vertical Sync 153 Output AB6 1.5v LVCMOS15 Video Display Enable 157 Output R6 1.5v LVCMOS15 Video Data Luma[0] 86 Output AB16 3.3v LVCMOS33 Video Data Luma[1] 87 Output U18 3.3v LVCMOS33 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 4
Video Data Luma[2] 88 Output Y16 3.3v LVCMOS33 Video Data Luma[3] 90 Output AA16 3.3v LVCMOS33 Video Data Luma[4] 121 Output W21 3.3v LVCMOS33 Video Data Luma[5] 123 Output W22 3.3v LVCMOS33 Video Data Luma[6] 125 Output U21 3.3v LVCMOS33 Video Data Luma[7] 127 Output T21 3.3v LVCMOS33 Video Data Luma[8] 156 Output T16 3.3v LVCMOS33 Video Data Luma[9] 158 Output U16 3.3v LVCMOS33 Video Data Chroma[0] 59 Output Y13 3.3v LVCMOS33 Video Data Chroma[1] 61 Output AA14 3.3v LVCMOS33 Video Data Chroma[2] 77 Output N13 3.3v LVCMOS33 Video Data Chroma[3] 79 Output N14 3.3v LVCMOS33 Video Data Chroma[4] 80 Output AB13 3.3v LVCMOS33 Video Data Chroma[5] 81 Output R18 3.3v LVCMOS33 Video Data Chroma[6] 82 Output AA13 3.3v LVCMOS33 Video Data Chroma[7] 83 Output T18 3.3v LVCMOS33 Video Data Chroma[8] 84 Output AB17 3.3v LVCMOS33 Video Data Chroma[9] 85 Output U17 3.3v LVCMOS33 Video Frame Sync Relock 116 Input Y6 1.5v LVCMOS15 SPDIF Audio 69 Output N20 1.5v LVCMOS15 Transport Stream Clock 113 Input V20 3.3v LVCMOS33 Transport Stream Data Valid 135 Input U6 1.5v LVCMOS15 Transport Stream User Data Valid 143 Input W6 1.5v LVCMOS15 Transport Stream Flash Data Valid 145 Input W5 1.5v LVCMOS15 Transport Stream Data[0] 124 Input M13 1.5v LVCMOS15 Transport Stream Data[1] 126 Input L13 1.5v LVCMOS15 Transport Stream Data[2] 128 Input L15 1.5v LVCMOS15 Transport Stream Data[3] 130 Input L14 1.5v LVCMOS15 Transport Stream Data[4] 132 Input K18 1.5v LVCMOS15 Transport Stream Data[5] 134 Input K19 1.5v LVCMOS15 Transport Stream Data[6] 131 Input K6 1.5v LVCMOS15 Transport Stream Data[7] 133 Input J6 1.5v LVCMOS15 User Data Clock 115 Output U20 3.3v LVCMOS33 User Data Valid 67 Output M20 1.5v LVCMOS15 User Data [0] 63 Output N19 1.5v LVCMOS15 User Data [1] 65 Output N18 1.5v LVCMOS15 Uart_tx 137 Output V5 1.5v LVCMOS15 Uart_rx 161 Input U5 1.5v LVCMOS15 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 5
4.2 Signal Format of Data Pins 4.2.1 External Reset (Input) The active high external reset signal can be used to reset the decoder core. An internal pull-down resistor is included, do not connect this pin if external reset is not required. 4.2.2 Clock Signal (Output) The video clock signal varies according to the resolution of the video Output. The following are the clock frequencies for standard video resolutions: 1. 27MHz, for SD resolution 2. 74.25MHz, for 720@60 and 1080@30 3. 148.5MHz, for 1080@60 4.2.3 Video Data Signals (Output) The Output of the decoder module, H.265, H.264 or MPEG-2 listed in Table 1, is in YUV format (4:2:2 or 4:2:0), with 10 Output lines, Video Data Luma[0] to Video Data Luma[9] for Luma, and 10 Output lines, Video Data Chroma[0] to Video Data Chroma[9] for the Chroma. The precision can be either 8 bits or 10 bits. When 8 bits precision is used, Video Data Luma[0], Video Data Luma[1], Video Data Chroma[0], and Video Data Chroma[2] are zeros. If embedded frame synchronization is disabled, the Video Horizontal Sync and Video Vertical Sync signals are output. Video Display Enable signifies the start and stop of the Output video data. 4.2.4 Audio Data Signals (Output, available in Video+Audio Decoder chipset) Output line SPDIF Audio is for PCM audio Output in SPDIF frames. 4.2.5 TS stream Signals (Input) The input of the decoder module is MPEG Transport Stream (TS), which is sent to the module by 8 parallel lines, Transport Stream Data[0] to Transport Stream Data[7], along with the Transport Stream Clock. The frequency of the Transport Stream Clock must be less than or equal to 125MHz. Transport Stream Data Valid Indicates that for the current clock cycle of Transport Stream Clock, Transport Stream Data are to be considered valid data. Transport Stream Flash Data Valid (optional) is the data valid signal for FPGA image data that is muxed into the TS stream input, and can be used by the decoder to update the IP core image stored in flash memory. Tie to ground if not used. Transport Stream User Data Valid (available upon request) is the data valid signal for user-specific data that is muxed into the TS stream input. 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 6
4.2.6 Decoder Control Signals (Input and output) Uart_rx and Uart_tx are the API pins for controlling the operations of the decoder. Uart_rx receives the command from external control device, Uart_tx send the decoder information to the control device. Refer to the Uart standard for details of Uart operations. The SOC API User Manual provides the register map for the API control. Refer to the Decoder API User Manual for details. 4.2.7 User Output data signals (Output, available upon request) The User Data signals can be used to send user-specific data from the decoder. The decoder sends out the User Data on User Data Clock, along with active-high signal User Data Valid. 4.2.8 Video Frame Sync Relock (Input, available upon request) The Video Frame Sync Relock signal can be used to relock the output frame sync to an external source. Note relocking the frame will cause interruption in the video output, and thus should only be used at startup. 4.2.9 SDI Clock (Input, available upon request) If SDI output interface is used for video playback, the SDI interface TX Clock signal can be sent to the decoder as the video clock. 4.3 Power Rails of XC7A200T The XC7A200T-SBG484/UBGA484 has its power requirement. Refer to the datasheet of XC7A200T for the power supplies. The reference design in Appendix-B provide a working design for all of the power rails. Table 3Table 2 lists all of the power rails required and the power pins in the reference design (MCM-1000A). Table 3: Power and Ground Pins of XC7A200T Reference Design (MCM-1000A) Connector Pin Voltage 1,3,5,7,9,11,13,15 3.3V 10,12,14,16 1.2V 22,24,26,28,30,32 1.5V 189,191,193,195,197,199 2.5V 188,190,192,194 1.3V 43,45,47,49,51,53,55,57 1.0V 2,4,6,8,17,18,20,34,35,36,37,39,41,42,44,62,71,72,73,74,75,129,163,16 5,167,168,169,170,172,174,175,176,177,184,185,186,187,200,202,203, 204 Ground 4.4 Power Requirement The total power at operation required by a given decoder ranges from 0.5 to 3 watts, depending on the resolution and frame rate. Overall, it is normally below 3W. 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 7
4.5 Power Supply Amperage All of the power rails, 1.0v, 1.2v, 1.3v, 1.5v, 2.5v, and 3.3v, are required to be supplied via the power pins, as listed in Table 3. These power rails are also shown in the edge connector schematics in Appendix-B. It has been tested that 2A (amps) for each power rail is sufficient, although it could be much lower. 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 8
5 Evaluation Kits SOC offers two evaluation kits for evaluating the codec chipsets (or modules or IP cores). The evaluation kits can also be used as product development platforms. The evaluation kits are: 1. FMC-MCM-1000, Fig. 3; 2. VTR-4000B, Fig. 4. Refer to the User Guides of FMC-MCM-1000 and VTR-4000B for details. User Guide FMC-MCM-1000 User Guide - VTR-4000B For evaluation uses, SOC pre-loads the firmware/software and I/O drivers of the FMC-MCM-1000 or VTR-4000B, which makes the kits plug-and-play. Evaluation Instruction Manual is included in the delivery package. For product development purposes, the IP cores ( netlist format) and the I/O driver executable/source codes are available for licensing. This allows the user to integrate the IP cores and I/O codes into the product designs. Fig. 3 FMC-MCM-1000 evaluation board 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 9
Fig. 4 VTR-4000B evaluation board 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 10
6 Ordering Information Fig. 5 shows the product code naming convention for the SOC MPEG codec chipsets, modules, and IP cores. Users can order the standard configurations listed in Appendix-A. Non-standard codec chipsets can be ordered following the same naming format (A one-time engineering fee may apply for non-standard chipsets). Example code EC-V-H264-10b-60-1080-M EC = Encoder DC = Decoder TC = Transcoder V = Video only A = Audio only VA = Video+Audio H264 = H.264/AVC H.265 = H.265/HEVC MPEG2 = MPEG-2 12b = 12bit Precision 10b = 10bit Precision 8b = 8 bit Precision IP = IP core M = Module C = Chipset 4k=3840X2160 Resolution 1080 = 1080 Resolution (1080X1920,Interlaced or progressive) 720 = 720 Resolution (720X1280, Interlaced or progressive) 480= 480 Resolution (480X640, Interlaced or progressive) 120 = 120 Frames/Sec. 60 = 60 Frames/Sec. 30 = 30 Frames/Sec. Fig. 5 SOC MPEG codec (IP cores, modules, and Chipset) product code naming convention 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 11
7 Contact Information Please Contact SOC head office or distributor for product details or to place an order. Head Office: System-On-Chip (SOC) Technologies Inc. 60 Baffin Place Waterloo, ON, Canada N2V 1Z7 Telephone: 1-519-880-8609 E-mail: sales@soctechnologies.com 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 12
APPENDIX-A Factory Standard Decoder Chipsets Note: H.265 decoder chipsets will be available in the near future. A.1 H.264 Decoder Chipsets The H.264 Decoder chipsets are based on the SOC H.264 decoder IP cores of different specifications. Table 4 lists the product code of the factory standard video decoder chips (video only), along with the specifications for each chip. Table 5 lists the video/audio decoder chips (both video and audio). Customers can order the decoder chipset using the product code, according to the specifications required by the application. Table 4: H.264 Video Decoder Chipsets Product # Specifications Standard Profile Resolution Chroma Precision Frame Rate Audio DC-V-H264-8b-30-720-C H.264 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 30fps no DC-V-H264-8b-60-720-C H.264 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 60fps no DC-V-H264-8b-30-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 30fps no DC-V-H264-10b-30-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 up to 10 bits up to 30fps no DC-V-H264-8b-60-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 60fps no DC-V-H264-10b-60-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 up to 10 bits up to 60fps no DC-V-H264-8b-30-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 up to 8 bits up to 30fps no DC-V-H264-10b-30-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 up to 10 bits up to 30fps no DC-V-H264-8b-60-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 8 bits up to 60fps no DC-V-H264-10b-60-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 10 bits up to 60fps no Table 5: H.264 Video & Audio Decoder Chipsets Product # Specifications Standard Profile Resolution Chroma Precision Frame Rate Audio DC-VA-H264-8b-30-720-C H.264 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 30fps AAC/MPEG2 L-2 DC-VA-H264-8b-60-720-C H.264 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 60fps AAC/MPEG2 L-2 DC-VA-H264-8b-30-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 30fps AAC/MPEG2 L-2 DC-VA-H264-10b-30-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 up to 10bits up to 30fps AAC/MPEG2 L-2 DC-VA-H264-8b-60-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 60fps AAC/MPEG2 L-2 DC-VA-H264-10b-60-1080-C H.264 up to High up to 1080i/p 4:2:0/4:2:2 up to 10 bits up to 60fps AAC/MPEG2 L-2 DC-VA-H264-8b-30-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 8 bits up to 30fps AAC/MPEG2 L-2 DC-VA-H264-10b-30-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 10 bits up to 30fps AAC/MPEG2 L-2 DC-VA-H264-8b-60-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 8 bits up to 60fps AAC/MPEG2 L-2 DC-VA-H264-10b-60-4k-C H.264 High 4k/UHD 4:2:0/4:2:2 10 bits up to 60fps AAC/MPEG2 L-2 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 13
A.2 MPEG-2 Decoder Chipsets Table 6 lists the standard MPEG-2 video decoder chipsets. Table 7 lists the MPEG-2 video/audio decoder chipsets. The 10 bit precision and 60 frames/second chipsets are offered as extensions of MPEG-2 standard. Table 6: MPEG-2 Video Decoder Chispets Product # Specifications Standard Profile Resolution Chroma Precision Frame Rate Audio DC-V-MPEG2-8b-30-720-C MPEG-2 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 30fps no DC-V-MPEG2-8b-60-720-C MPEG-2 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 60fps no DC-V-MPEG2-8b-30-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 30fps no DC-V-MPEG2-10b-30-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 up to 10 bits up to 30fps no DC-V-MPEG2-8b-60-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 60fps no DC-V-MPEG2-10b-60-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 up to 10 bits up to 60fps no Table 7: MPEG-2 Video & Audio Decoder Chispets Product # Specifications Standard Profile Resolution Chroma Precision Frame Rate Audio DC-VA-MPEG2-8b-30-720-C MPEG-2 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 30fps AAC/MPEG2 L-2 DC-VA-MPEG2-8b-60-720-C MPEG-2 up to High up to 720i/p 4:2:0/4:2:2 8 bits up to 60fps AAC/MPEG2 L-2 DC-VA-MPEG2-8b-30-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 30fps AAC/MPEG2 L-2 DC-VA-MPEG2-10b-30-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 up to 10bits up to 30fps AAC/MPEG2 L-2 DC-VA-MPEG2-8b-60-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 8 bits up to 60fps AAC/MPEG2 L-2 DC-VA-MPEG2-10b-60-1080-C MPEG-2 up to High up to 1080i/p 4:2:0/4:2:2 up to 10 bits up to 60fps AAC/MPEG2 L-2 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 14
APPENDIX-B Reference PCB Design (The SOC MCM-1000A) Description: The SOC MCM-1000A is a small PCB card that has the XC7A200T-SBG484/UBGA484. It can be configured into an encoder or decoder by storing a corresponding IP core into the on-board flash memory. SOC supplies the modules to customers, which is another product format in parallel to the chipset. Fig. B.1 shows a photo of the MCM-1000A module. 2.0 2.7 Fig. B.1 SOC MCM-1000A codec module (Size: 2 x2.7 ) Refer to the Datasheet of the codec module Datasheet - Encoder Modules and Datasheet - Decoder Modules for details. 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 15
Revision History Date (MM/DD/YYYY) Version Notes Author 02/14/2017 1.0 Initial Version Mulong Li 2017, System-On-Chip Technologies Inc. www.soctechnologies.com Page 16