128K 8 CMOS FLASH MEMORY GENERAL ESCRIPTION The W29C011A is a 1-megabit, 5-volt only CMOS flash memory organized as 128K 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C011A results in fast program/erase operations with extremely low current consumption (compared other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES Single 5-volt program and erase operations Fast page-write operations 128 bytes per page Page program cycle: 10 ms (max.) Effective byte-program cycle time: 39 µs Software-protected data write Fast chip-erase operation: 50 ms Read access time: 150 ns Page program/erase cycles: 1,000 Ten-year data retention Software and hardware data protection Low power consumption Active current: 25 ma (typ.) Standby current: 20 µa (typ.) Aumatic program timing with internal VPP generation End of program detection Toggle bit ata polling Latched address and data TTL compatible I/O JEEC standard byte-wide pinouts Available packages: 32-pin 600 mil IP, 450 mil SOP and PLCC Publication Release ate: January 31, 2002-1 - Revision A3
PIN CONFIGURATIONS BLOCK IAGRAM V NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin IP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 V # WE NC A14 A13 A8 A9 A11 # OE A10 # CE Q7 Q6 Q5 Q4 Q3 VSS #OE #WE A0.. A16 CONTROL ECOER OUTPUT BUFFER CORE ARRAY Q0. Q7 A A A 12 15 16 N C V # W E N C 4 3 2 1 32 31 30 PIN ESCRIPTION A7 A6 A5 A4 A3 A2 A1 A0 Q0 5 6 7 8 9 10 11 12 13 32-pin PLCC 14 15 16 17 18 19 20 Q 1 Q2 G N Q3 Q4 Q5 Q6 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 #O A10 Q7 SYMBOL A0 A16 Q0 Q7 #OE #WE V PIN NAME Address Inputs ata Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply GN Ground NC No Connection - 2 -
FUNCTIONAL ESCRIPTION Read Mode The read operation of the W29C011A is controlled by and #OE, both of which have be low for the host obtain data from the outputs. is used for device selection. When is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used gate data from the output pins. The data bus is in high impedance state when either or #OE is high. Refer the timing waveforms for further details. Page Write Mode The W29C011A is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is be changed, data for the entire page must be loaded in the device. Any byte that is not loaded will be erased "FFh" during programming of the page. The write operation is initiated by forcing and #WE low and #OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written in the memory array for non-volatile srage. uring the byte-load cycle, the addresses are latched by the falling edge of either or #WE, whichever occurs last. The data are latched by the rising edge of either or #WE, whichever occurs first. If the host loads a second byte in the page buffer within a byte-load cycle time (TBLC) of 200 µs, after the initial byte-load cycle, the W29C011A will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded in the page buffer within 300 µs (TBLCO) from the last byte-load cycle, i.e., there is no subsequent #WE high--low transition after the last rising edge of #WE. A7 A16 specify the page address. All bytes that are loaded in the page buffer must have the same page address. A0 A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously in the memory array. Before the completion of the internal programming cycle, the host is free perform other tasks such as fetching data from other locations in the system prepare write the next page. Software-protected ata Write The device provides a JEEC-approved software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data a specific address) be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C011A is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Publication Release ate: January 31, 2002-3 - Revision A3
Hardware ata Protection The integrity of the data sred in the W29C011A is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 ns in duration will not initiate a write cycle. (2) V Power Up/own etection: The programming and read operation are inhibited when V is less than 3.8V. (3) Write Inhibit Mode: Forcing #OE low, high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. ata Polling (Q7)-Write Status etection The W29C011A includes a data polling feature indicate the end of a programming cycle. When the W29C011A is in the internal programming cycle, any attempt read Q7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. Q7 will show the true data. Toggle Bit (Q6)-Write Status etection In addition data polling, the W29C011A provides another method for determining the end of a program cycle. uring the internal programming cycle, any consecutive attempts read Q6 will produce alternating 0's and 1's. When the programming cycle is completed, this ggling between 0's and 1's will sp. The device is then ready for the next operation. 5-Volt-Only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is aumatically timed and will be completed in 50 ms. The host system is not required provide any control or timing during this operation. Product Identification The product I operation outputs the manufacturer code and device code. Programming equipment aumatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used access the product I. A read from address 0000H outputs the manufacturer code (Ah). A read from address 0001H outputs the device code (C1h). The product I operation can be terminated by a three-byte command sequence. In the hardware access mode, access the product I is activated by forcing and #OE low, #WE high, and raising A9 12 volts. Note: The hardware SI read function is not included in all parts; please refer Ordering Information for details. - 4 -
TABLE OF OPERATING MOES Operating Mode Selection Operating Range = 0 70 C (Ambient Temperature), V = 5V ±10 %, VSS = 0V, VHH = 12V MOE PINS #OE #WE ARESS Q. Read VIL VIL VIH AIN out Write VIL VIH VIL AIN in Standby VIH X X X High Z Write Inhibit X VIL X X High Z/OUT X X VIH X High Z/OUT Output isable X VIH X X High Z 5-Volt Software Chip Erase VIL VIH VIL AIN IN Product I VIL VIL VIH A0 = VIL; A1 A16 = VIL; A9 = VHH VIL VIL VIH A0 = VIH; A1 A16 = VIL; A9 = VHH Manufacturer Code A (Hex) evice Code C1 (Hex) Publication Release ate: January 31, 2002-5 - Revision A3
Command Codes for Software ata Protection Write BYTE SEQUENCE ARESS ATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H Software ata Protection Acquisition Flow Software ata Protection Write Flow Load data AA Load data 55 address 2AAA Load data A0 Load 0 128 bytes of page data Pause 10 ms Exit Notes for software program code: ata Format: Q7 Q0 (Hex) Address Format: A14 A0 (Hex) - 6 -
COMMAN COES FOR SOFTWARE CHIP ERASE BYTE SEQUENCE ARESS ATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H 80H 3 Write 5555H AAH 4 Write 2AAAH 55H 5 Write 5555H 10H Software Chip Erase Acquisition Flow Load data AA Load data 55 address 2AAA Load data 80 Load data AA Load data 55 address 2AAA Load data 10 Pause 50 ms Exit Notes for software chip erase: ata Format: Q7 Q0 (Hex) Address Format: A14 A0 (Hex) Publication Release ate: January 31, 2002-7 - Revision A3
Command Codes for Product Identification BYTE SEQUENCE SOFTWARE PROUCT IENTIFICATION ENTRY SOFTWARE PROUCT IENTIFICATION EXIT ARESS ATA ARESS ATA 0 Write 5555H AAH 5555H AAH 1 Write 2AAAH 55H 2AAAH 55H 2 Write 5555H 80H 5555H F0H 3 Write 5555H AAH - - 4 Write 2AAAH 55H - - 5 Write 5555H 60H - - Pause 10 µs Pause 10 µs Software Product Identification Acquisition Flow Product Identification Entry(1) Product Identification Mode(2,3) Product Identification Exit(1) Load data AA Load data 55 address 2AAA Load data AA Load data 80 Read address = 0 data = A Load data 55 address 2AAA Load data AA Load data FO Load data 55 address 2AAA Read address = 1 data = C1 Pause 10 µsm Load data 60 Normal Mode (4) Pause 10 µ S Notes for software product identification: (1) ata format: Q7 Q0 (Hex); address format: A14 A0 (Hex). (2) A1 A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns standard operation mode. - 8 -
C CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage Vss Potential -0.5 +7.0 V Operating Temperature 0 +70 C Srage Temperature -65 +150 C.C. Voltage on Any Pin Ground Potential except #OE -0.5 V +1.0 V Transient Voltage ( 20 ns) on Any Pin Ground Potential -1.0 V +1.0 V Voltage on #OE Pin Ground Potential -0.5 12.5 V Note: Exposure conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (V = 5.0V ±10%, VSS = 0V, TA = 0 70 C) PARAMETER SYM. TEST CONITIONS LIMITS UNIT Power Supply Current ICC = #OE = VIL, #WE = VIH, all I/Os open Standby V Current (TTL input) Standby V Current (CMOS input) ISB1 ISB2 Address inputs = VIL/VIH, at f = 5 MHz = VIH, all I/Os open Other inputs = VIL/VIH = V -0.3V, all I/Os open Other inputs = V -0.3V/GN MIN. TYP. MAX. - - 50 ma - 2 3 ma - 20 100 µa Input Leakage Current ILI VIN = GN V - - 1 µa Output Leakage Current ILO VIN = GN V - - 10 µa Input Low Voltage VIL - -0.3-0.8 V Input High Voltage VIH - 2.0 - V +0.5 V Output Low Voltage VOL IOL = 2.1 ma - - 0.45 V Output High Voltage VOH IOH = -0.4 ma 2.4 - - V Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up Read Operation TPU.REA 100 µs Power-up Write Operation TPU.WRITE 5 ms Publication Release ate: January 31, 2002-9 - Revision A3
CAPACITANCE (V = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER SYMBOL CONITIONS MAX. UNIT I/O Pin Capacitance CI/O VI/O = 0V 12 pf Input Capacitance CIN VIN = 0V 6 pf AC CHARACTERISTICS AC Test Conditions (V = 5V ±10%) PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load CONITIONS 0V/3V 10 ns 1.5V/1.5V 1 TTL Gate and CL = 100 pf AC Test Load and Waveforms +5V 1.8K ohm OUT 100 pf 1.3K ohm Input Output 3V 0V 1.5V 1.5V Test Point Test Point - 10 -
Read Cycle Timing Parameters (V = 5.0V ±10%, VSS = 0V, TA = 0 70 C) PARAMETER SYMBOL W29C011A-15 UNIT MIN. MAX. Read Cycle Time TRC 150 - ns Chip Enable Access Time TCE - 150 ns Address Access Time TAA - 150 ns Output Enable Access Time TOE - 70 ns Low Active Output TCLZ 0 - ns #OE Low Active Output TOLZ 0 - ns High High-Z Output TCHZ - 45 ns #OE High High-Z Output TOHZ - 45 ns Output Hold from Address change TOH 0 - ns Byte/Page-Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Write Cycle (erase and program) TWC - - 10 ms Address Setup Time TAS 0 - - ns Address Hold Time TAH 50 - - ns #WE and Setup Time TCS 0 - - ns #WE and Hold Time TCH 0 - - ns #OE High Setup Time TOES 10 - - ns #OE High Hold Time TOEH 10 - - ns Pulse Width TCP 70 - - ns #WE Pulse Width TWP 70 - - ns #WE High Width TWPH 150 - - ns ata Setup Time TS 50 - - ns ata Hold Time TH 10 - - ns Byte Load Cycle Time TBLC 0.22-200 µs Byte Load Cycle Time-out TBLCO 300 - - µs Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. Publication Release ate: January 31, 2002-11 - Revision A3
ata Polling and Toggle Bit Timing Parameters PARAMETER SYMBOL W29C011A-15 UNIT MIN. MAX. #OE ata Polling Output elay TOEP - 70 ns ata Polling Output elay TCEP - 150 ns #OE Toggle Bit Output elay TOET - 70 ns Toggle Bit Output elay TCET - 150 ns TIMING WAVEFORMS Read Cycle Timing iagram T RC Address A16-0 TCE #OE TOE #W VIH TOLZ TOHZ TCLZ TOH TCHZ Q7-0 High-Z ata Valid ata Valid High-Z TAA - 12 -
Timing Waveforms, continued Page Write Timing iagram Three-byte sequence for software data protection mode Byte/page load cycle starts TWC Address A16-0 5555 2AAA 5555 Q6 AA 55 A0 #OE #WE TWP TWPH TBLC T BLCO SW0 SW1 SW2 Byte 0 Byte N-1 Byte N (last byte) Internal write starts Note Notes: Refer " (#WE) Controlled Write Cycle Timing iagram" for a detailed timing diagram. #WE Controlled Write Cycle Timing iagram T BLCO T WC T AS T AH Address A16-0 T CS T CH #OE T OES T OEH #WE T WP T WPH T S Q7-0 ata Valid T H Internal write starts Publication Release ate: January 31, 2002-13 - Revision A3
Timing Waveforms, continued Controlled Write Cycle Timing iagram TAS TAH TBLCO TWC Address A16-0 TCP TCPH TOES TOEH #OE #WE Q7-0 High Z TS ata Valid TH Internal Write Starts #ATA Polling Timing iagram Address A16-0 #WE T CEP #OE T OEH TOES Q7-0 T OEP X X X X TWC - 14 -
Timing Waveforms, continued Toggle Bit Timing iagram Address A16-0 #WE #OE TOEH TOES Q6 TWC 5 Volt-Only Software Chip Erase Timing iagram Six-byte code for 5V-only software chip erase TWC Address A16-0 5555 2AAA 5555 5555 2AAA 5555 Q7-0 AA 55 80 AA 55 10 #OE #WE TWP TWPH TBLC TBLCO SW0 SW1 SW2 SW3 SW4 SW5 Internal programming starts Publication Release ate: January 31, 2002-15 - Revision A3
ORERING INFORMATION PART NO. ACCESS TIME (ns) POWER SUPPLY CURRENT MAX. (ma) STANBY V CURRENT MAX. (ma) PACKAGE HARWARE SI REA FUNCTION W29C011A-15 150 50 100 600 mil IP Y W29C011AS-15 150 50 100 450 mil SOP Y W29C011AP-15 150 50 100 32-pin PLCC Y W29C011A-15N 150 50 100 600 mil IP N W29C011AP15N 150 50 100 32-pin PLCC N Notes: 1. Winbond reserves the right make changes its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. In Hardware SI Read column: Y = with SI read function; N = without SI read function. HOW TO REA THE TOP MARKING Example: The p marking of 32L-PLCC W29C011AP-15 W29C011AP-15 2138977A-A12 149OBRA 1 st line: winbond logo 2 nd line: the part number: W29C011AP-15 3 rd line: the lot number 4 th line: the tracking code: 149 O B RA 149: Packages made in 01, week 49 O: Assembly house I: A means ASE, O means OSE,...etc. B: IC revision; A means version A, B means version B,...etc. RA: Process code - 16 -
PACKAGE IMENSIONS 32-pin P-IP E1 A 2 A L 32 17 1 16 S B e1 B1 A1 Base Plane Seating Plane a E ea c Symbol A A1 A2 B B 1 c E E1 e L a e 1 A imension in inches Min. Nom. Max. Min. Nom. Max. 0.010 0.150 0.016 0.048 0.008 0.120 0.155 0.018 imension in mm 0.210 5.33 0.160 0.022 0.25 3.81 0.41 3.94 0.46 0.050 0.054 1.22 1.27 0.010 0.130 0.014 0.590 0.600 0.610 0.140 0.20 3.05 0.25 3.30 0.630 0.650 0.670 16.00 16.51 4.06 0.56 1.37 0.36 1.650 1.660 41.91 42.16 14.99 15.24 15.49 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 0 15 2.29 2.54 2.79 3.56 17.02 S 0.085 2.16 Notes: 1.imensions Max. & S include mold flash or tie bar burrs. 2.imension E1 does not include interlead flash. 3.imensions & E1. include mold mismatch and are determined at the mold parting line. 4.imension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches. 6.General appearance spec. should be based on final visual inspection spec. 0 15 32-pin SO Wide Body 32 1 b 17 16 E HE L e 1 etail F Symbol A A 1 A 2 b c E e H E L y θ imension in Inches Min. Nom. Max. Min. Nom. Max. 0.004 0.101 0.014 0.006 0.440 0.106 0.016 0.008 0.805 0.445 imension in mm 0.118 3.00 0.111 0.020 0.10 2.57 0.36 2.69 0.41 2.82 0.51 0.012 0.15 0.20 0.31 0.817 0.450 0.044 0.050 0.056 0.004 0 10 20.45 20.75 0.546 0.556 0.556 13.87 14.12 14.38 0.023 0.031 0.039 11.18 0 11.30 11.43 1.12 1.27 1.42 0.58 0.79 0.99 L E 0.047 0.055 0.063 1.19 1.40 1.60 S 0.036 0.91 0.10 10 S Seating Plane y e A A 2 A 1 e 1 See etail F L E c Notes: 1. imensions Max. & S include mold flash or tie bar burrs. 2. imension b does not include dambar protrusion/intrusion. 3. imensions & E include. mold mismatch and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. Publication Release ate: January 31, 2002-17 - Revision A3
Package imensions, continued 32-pin PLCC 5 4 H E E 1 32 30 29 Symbol A A A 1 2 b 1 b c E e G imension in Inches Min. Nom. Max. Min. Nom. Max. 0.020 0.105 0.110 0.026 0.028 0.016 0.008 0.547 0.447 0.490 0.018 0.010 0.550 0.450 0.510 0.140 0.115 0.032 0.022 0.014 0.553 0.453 0.044 0.050 0.056 0.530 0.50 imension in mm 3.56 2.67 2.80 2.93 0.66 0.71 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.12 1.27 1.42 12.45 12.95 13.46 13 21 H G GE H H E L y θ Notes: 0.390 0.585 0.485 0.075 0.410 0.590 0.490 0.090 0.430 0.595 0.495 0.095 0.004 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 2.41 0.10 0 10 0 10 L 14 20 c 1. imensions & E do not include interlead flash. 2. imension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. A 2 A e b A 1 Seating Plane b 1 G E y - 18 -
VERSION HISTORY VERSION ATE PAGE ESCRIPTION A1 ec. 1997 Initial Issued A2 Jan. 2001 10 Modify VIH/VIL = 0V/3V and VOH/VOL = 1.5V/1.5V 4, 16 Add in Hardware SI Read function note A3 Jan. 31, 2002 4 Modify VCC Power Up/own etection in Hardware ata Protection 16 Add HOW TO REA THE TOP MARKING Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Taipei Office 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F aini-ueno BLG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject change without notice. All the trade marks of products and companies mentioned in this data sheet belong their respective owners. Publication Release ate: January 31, 2002-19 - Revision A3