Blocking(=) vs Nonblocking (<=) Assignment Lecture 3: Modeling Sequential Logic in Verilog HDL always @ (b) a = b; c = a; final value: a = b =c always @(posedge clk) a <= b; c <= a; final value: a = b c = old a 2 Use non-blocking for flip flop inference posedge/negedge require nonblocking always @ (posedge clock) b <= a; //swap a and b a <= b; If using blocking for flipflop inference, we may not get what you want. always @(posedge clock) b = a; a = b; // b=a, a=a 3 Procedural assignments Blocking assignment = Regular assignment inside procedural block Assignment takes place immediately LHS must be a register Nonblocking assignment <= Compute RHS Assignment takes place at of block LHS must be a register 4
Execution order at Q (in any order) Evaluate RHS of all non-blocking assignments Evaluate RHS and change LHS of all blocking assignments (execution of all blocking assignments is in order) Evaluate RHS and change LHS of all continuous assignments Evaluate inputs and change outputs of all primitives at Q2 Change LHS of all non-blocking assignments at the same time All non-blocking assignments are evaluated using the values the variables have when your design entered the always block. Non-blocking assignment is also known as an RTL assignment if used in an always block triggered by a clock edge all flipflops change together always @(posedge clk) B = A; C = B; D = C; //what does this circuit do? B=A, C=A, D=A always @(posedge clk) B <= A; C <= B; D <= C; //What does this circuit do? a shift register 5 6 Finite State Machine Review A finite state machine has a state register that holds current state some combinational logic that calculates the next state and outputs based on the current state and/or the current inputs Moore machine: output based on current state inputs combinational logic for next state logic for reg outputs outputs state feedback Mealy machine: based on current state and inputs A finite state machine is a feedback system which updates on each clock. inputs logic for outputs combinational logic for next state reg outputs state feedback 7 8 2
Comparison of Mealy and Moore machines Mealy machines t to have less states different outputs on arcs (n 2 ) rather than states (n) Moore machines are safer to use outputs change at clock edge (always one cycle later) in Mealy machines, input change can cause output change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback may occur if one isn t careful Mealy machines react faster to inputs react in same cycle don't need to wait for clock in Moore machines, more logic may be necessary to decode state into outputs more gate delays after clock edge Finite State Machine Design Determine inputs/output Determine machine types (Mealy vs. Moore) Determine machine flow (state diagram) State assignment Implementation 9 A Moore Machine Output Z 2 Z Z Using D flip flops next state logic D = Q x + Q 3 x + Q x D = Q 2 x D 2 = Q x + Q x D 3 = Q 2 x + Q 3 x Output Logic Z 2 =Q 2 ; Z =Q 2 ; Z =Q 2 +Q input x Using D Flip Flops one-hot encoding State Q 3 Q 2 Q Q A B C D Write a complete structural Verilog model of this simple Moore machine. module DFF(q, d, clk, reset, preset); input d, clk, reset, preset; output q; reg q; always @(posedge clk or negedge reset or negedge preset) if (~reset) q <= ; else if (~preset) q <= ; else q <= d; module 2 3
module clock (clk); output clk; reg clk; initial # clk=; always # clk = ~clk; module module OneHotNS(D, Q, x); input x; input [3:] Q; output [3:] D; reg [3:] D; always @(Q or x) D[3] = (Q[2] & x) (Q[3] & ~x); D[2] =(Q[] & ~x) (Q[] & x); D[]= Q[2] & ~x; D[] = (Q[] & ~x) (Q[] & x) (Q[3] & x); module 3 4 module OneHotOutput(Z, Q); input [3:] Q; output [2:] Z; reg [2:] Z; always @ (Q) Z[2] = Q[2]; Z[] = ~Q[2]; Z[] = Q[2] Q[]; module module OneHotFSM(Z, x, clk, reset); input x, clk, reset; output [2:] Z; wire [3:] D, Q; DFF OneHotD3(Q[3], D[3], clk, reset, b), OneHotD2(Q[2], D[2], clk, reset, b), OneHotD(Q[], D[], clk, reset, b), OneHotD(Q[], D[], clk, b, reset); OneHotNS OneHotOutput module NextStateUnit(D, Q, x); OutputUnit(Z, Q); 5 6 4
module testbench (Z, x, clk, reset); input [2:] Z; input clk; output x, reset; reg x, reset; reg[:] data; integer i; initial $monitor ($time,, Z = %b, x = %b, clock= %b, Z, x, clk); reset = ; data = 2 b; // x = (from L to R) # reset = ; for (i = ; i <= ; i = i + ) x = data[i]; #2; # $finish; module 7 module system wire clk, reset, x; wire [2:] Z; testbench testunit (Z, x, clk, reset); clock clockunit (clk); OneHotFSM FSMunit(Z, x, clk, reset); module 8 Z =, x = x, clock= x Z =, x =, clock= Z =, x =, clock= 2 Z =, x =, clock= 3 Z =, x =, clock= 4 Z =, x =, clock= 4 Z =, x =, clock= 5 Z =, x =, clock= 6 Z =, x =, clock= 6 Z =, x =, clock= 7 Z =, x =, clock= 8 Z =, x =, clock= 8 Z =, x =, clock= 9 Z =, x =, clock= Z =, x =, clock= Z =, x =, clock= 2 Z =, x =, clock= 9 2 Z =, x =, clock= 3 Z =, x =, clock= 4 Z =, x =, clock= 4 Z =, x =, clock= 5 Z =, x =, clock= 6 Z =, x =, clock= 7 Z =, x =, clock= 8 Z =, x =, clock= 8 Z =, x =, clock= 9 Z =, x =, clock= 2 Z =, x =, clock= 2 Z =, x =, clock= 2 Z =, x =, clock= 22 Z =, x =, clock= 23 Z =, x =, clock= 24 Z =, x =, clock= 2 5
Another finite state machine given the state transition diagram module sfsm (clk, reset, in, out); input clk, reset, in; output out; parameter zero = 2 b; parameter one = 2 b; parameter twos = 2 b; reg out; reg [2:] state; // state variables reg [2:] next_state; always @(posedge clk) if (reset) state <= zero; else state <= next_state; zero [] one [] twos [] 2 always @(in or state) // generate Next State case (state) zero: //last input was a zero if (in) next_state = one; else next_state = zero; one: // we've seen one if (in) next_state = twos; else next_state = zero; twos: // we've seen at least 2 ones if (in) next_state = twos; else next_state = zero; case zero [] one [] twos [] always @(state) case (state) zero: out = ; one: out = ; twos: out = ; case module 22 A Mealy Machine An always block for a combinational function. A module can have more than one of these always blocks. Partition a design into several modules Tools optimize each module separately always @(state) case (state) zero: out = ; one: out = ; twos: out = ; case Combining several modules into one module, tools optimize this single module. Binary encoding state A = ; state B = ; state C=; state D = 23 24 6
module mealyfsm (out, x, clk, reset); input x, clk, reset; output [:] out; reg [:] out, curstate, nextstate; parameter [:] A=, B=, C=2, D=3; // state transition always @(posedge clk or negedge reset) $display( ); if (~reset) curstate <= ; $display ( state ); else curstate <= nextstate; $display ( state %d, nextstate); 25 // next state logic and output logic combinational always @(curstate or x) case (curstate) A: out = 3; nextstate = D; B: out = ( x ==)? 2 : ; nextstate = ( x == )? A : D; C: out = (x == )? : ; nextstate = (x == )? B : D; D: out = ( x == )? : ; nextstate = ( x== )? C : D; case module 26 module clock(clk); output clk; reg clk; initial clk = ; always # clk = ~clk; module module testbench (out, x, clk, reset); output x, reset; input [:] out; input clk; reg x, reset; reg[:] data; integer I; initial $monitor ($time,, clk = %b, x = %b, out = %d, clk, x, out); reset = ; // set state to A data = 2 b; # reset = ; for ( i = ; i >= ; i = i -) x = data[i]; #2; $finish; module 27 28 7
module system; wire [:] out; wire x, clk, reset; mealyfsm clock testbench module M(out, x, clk, reset); timer(clk); test(out, x, clk, reset); 29 state clk =, x = x, out = 3 clk =, x =, out = 3 clk =, x =, out = 2 clk =, x =, out = 2 clk =, x =, out = 3 clk =, x =, out = 4 clk =, x =, out = 5 clk =, x =, out = 6 clk =, x =, out = 6 clk =, x =, out = state 2 7 clk =, x =, out = 8 clk =, x =, out = 8 clk =, x =, out = copied from Silos output window 3 9 clk =, x =, out = clk =, x =, out = clk =, x =, out = state 2 clk =, x =, out = 2 clk =, x =, out = state 3 clk =, x =, out = 2 4 clk =, x =, out = 2 4 clk =, x =, out = 5 clk =, x =, out = 6 clk =, x =, out = 6 clk =, x =, out = state 2 7 clk =, x =, out = 8 clk =, x =, out = state 9 clk =, x =, out = 2 2 clk =, x =, out = 2 state 2 clk =, x =, out = 3 22 clk =, x =, out = 3 23 clk =, x =, out = 24 clk =, x =, out = 3 8