MIT Nerd Kit. Configurable Application Modules. Switches

Similar documents
Drexel University Electrical and Computer Engineering Department ECE 200 Intelligent Systems Spring Lab 1. Pencilbox Logic Designer

Copyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11. Ver. 1.0web

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Introductory Digital Systems Laboratory

Digital Electronics & Computer Engineering (E85)

7 8 9 C. PRELAB REQUIREMENTS You must adhere to the Lab Rules and Policies document for every lab.

Microcomputer System Design

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000

_ V Intel 8085 Family In-Circuit Emulation. Contents. Technical Notes

ECSE-323 Digital System Design. Lab #1 Using the Altera Quartus II Software Fall 2008

PAD ANALOG / DIGITAL TRAINER OPERATOR S MANUAL

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science

Name EGR 2131 Lab #6 Number Representation and Arithmetic Circuits

8254 is a programmable interval timer. Which is widely used in clock driven digital circuits. with out timer there will not be proper synchronization

NAME EET 2259 Lab 3 The Boolean Data Type

Lab 1: Introduction to Verilog HDL and the Xilinx ISE

Training Kit for HP 1660/70 Series Logic Analyzers

DS1870 LDMOS BIAS CONTROLLER EV KIT

Chapter Operation Pinout Operation 35

Experiment 9: Binary Arithmetic Circuits. In-Lab Procedure and Report (30 points)

University of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA

Programmable Logic Design I

EE 231 Fall Lab 1: Introduction to Verilog HDL and Altera IDE

Getting Started with STK200 Dragon

CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado

and 32 bit for 32 bit. If you don t pay attention to this, there will be unexpected behavior in the ISE software and thing may not work properly!

A B A+B

CHAPTER TWELVE - Memory Devices

If I wanted to connect an LED and little light bulb and have them switch on and off with one switch, my schematic would look like the one below.

Propeller Activity Board (#32910)

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2015

Evaluates: DS28E80. DS28E80 Evaluation System. General Description. Benefits and Features. EV Kit Contents

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 150 Spring 2000

Digital Electronics & Computer Engineering (E85)

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science

User s Guide. LA5034 Operation Manual

Arduino Micro Breadboard Laboratory Interface Processor (Micro BLIP) User Manual

PSIM Tutorial. How to Use SCI for Real-Time Monitoring in F2833x Target. February Powersim Inc.

Bill of Materials: Turn Off the Lights Reminder PART NO

Introduction to LogicWorks (Version 5) by: Kevin Su

Pre-Lab: Part 1 Using The Development Environment. Purpose: Minimum Parts Required: References: Handouts:

Boise State University Digital Systems Laboratory

EE 390 Lab Manual, EE Department, KFUPM. Experiment #7. Introduction to Flight86 Microprocessor Trainer and Application Board

ISP Engineering Kit Model 300

Freeze the Dizz Jameco Part No

INSTALLATION AND OPERATION MANUAL FOR ACC 070 COMM LINK RS485 TO PC INTERFACE AND PRISM SOFTWARE

Goal: We want to build an autonomous vehicle (robot)

Getting Started with the HCS12 IDE

CPLD/FPGA Development System

AVR Board Setup General Purpose Digital Output

EET 1131 Lab #7 Arithmetic Circuits

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado

GammaTron USB Module

Finite State Machine Lab

Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

Introduction to Computer Engineering (E114)

University of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1

University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring Lab 1: Using Nios 2 processor for code execution on FPGA

Table 1 - SDIO Pinout. Pin SD 4-bit Mode SD 1-bit Mode SPI Mode. 1 CD/DAT3 Data Line CS Card Select

Programmable Logic Design I

ESE 150 Lab 07: Digital Logic

KIT-VR4120-TP. User's Manual (Rev.1.01) RealTimeEvaluator

4. Configuring Cyclone II Devices

REQUIRED MATERIALS Reread Lab Rules and Policies document EEL 3744 (upad and upad Proto Base) DAD/NAD Analog Discovery board PRELAB REQUIREMENTS

EECS 140 Laboratory Exercise 4 3-to-11 Counter Implementation

PUSH BUTTON. Revision Class. Instructor / Professor LICENSE

TECH 3821 Lab #2 Relay Driver with Computer Control

DOMAIN TECHNOLOGIES INC. Users Guide Version 2.0 SB-USB2. Emulator

Avnet Zynq Mini Module Plus Embedded Design

Intro to Digital Logic, Lab 5 Sequential Logic. Lab Objectives. Assigned Task Mapping sequential logic to the FPGA

3. The MC6802 MICROPROCESSOR

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

E85: Digital Design and Computer Engineering Lab 1: Electrical Characteristics of Logic Gates

CSEE W4840 Embedded System Design Lab 1

E3940 Microprocessor Systems Laboratory. Introduction to the Z80

CSEE W4840 Embedded System Design Lab 1

EECS 150 Homework 7 Solutions Fall (a) 4.3 The functions for the 7 segment display decoder given in Section 4.3 are:

ice40 Ultra Self-Learning IR Remote User s Guide

NIOS CPU Based Embedded Computer System on Programmable Chip

Lecture-55 System Interface:

1/Build a Mintronics: MintDuino

4408 Digital Audio 8x1 Switch

CPE/EE 421/521 Fall 2004 Chapter 4 The CPU Hardware Model. Dr. Rhonda Kay Gaede UAH. The CPU Hardware Model - Overview

EE 271 Final Project - Towers of Hanoi

KIT-V850E2/MN4-TP-H. User s Manual (Rev. 1.01) RealTimeEvaluator

CSEE W4840 Embedded System Design Lab 1

ENEE245 Digital Circuits and Systems Lab Manual

CS4141 IDL Notes. I. Quick Overview of IDL Prototyping Unit

EE 354 August 1, 2017 Assembly of the AT89C51CC03 board

REQUIRED MATERIALS Reread Lab Rules and Policies document EEL 3744 (upad and upad Proto Base) Digilent Analog Discovery (DAD) PRELAB REQUIREMENTS

Quick Tutorial for Quartus II & ModelSim Altera

E85: Digital Design and Computer Architecture J. Spjut and R. Wang Spring 2014

REQUIRED MATERIALS Reread Lab Rules and Policies document EEL 3744 (upad and upad Proto Base) Digilent Analog Discovery (DAD) PRELAB REQUIREMENTS

475 Electronics for physicists Introduction to FPGA programming

COS 116 The Computational Universe Laboratory 7: Digital Logic I

Halloween Pumpkinusing. Wednesday, October 17, 12

EE261 Computer Project 1: Using Mentor Graphics for Digital Simulation

ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING. EEM Digital Systems II

Transcription:

MIT 6.004 Nerd Kit MIT 6.004 Nerd Kit comes with an array of 16 computational blocks. You can configure these blocks to do anything from computing just ANDs and ORs to being a Beta microprocessor. In addition to those FPGA blocks, there is one breadboard strip, IO block, switches and a few other features of the kit that you need to be know before you get started with the lab asignments that uses the lab kit. Configurable Application Modules Bank of 16 LEDs Detail View I/O connector I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 Each computational block has a 20-pin socket. It s the grey plastic box near the bottom of the computational block with silvery rivets. Each of those rivets is actually a receptacle for the stripped end of a wire. When you run a single wire from one block to another, you are actually making a connection that carries 32 bits. Each of the 32 bits are sent one at a time down the wire, in serial. Thus, we call them serial wires. This is a convenient abstraction which allows you to wire up very complex and powerful circuits without the pain of having to run 32 individual wires for every bussed connection. You can use the same wire to transmit just one bit. Read more on this in Data Transmission section of this document. Switches On the bottom left of the kit right above white breadboard, you will see a row of ten switches. Switches are numbered from right to left (0... 9). Switches 0..7 can be configured to be momentary or push buttons. If a switch is configured to be a momentary button, the wire connected to the switch will carry Vcc only when the switch is pressed. While the same switch configured as a push button will toggle between Vcc and GND at each switch-press. Read about IO block on how to get outputs from a switch. Switch 8: is a push button and can be used to select between free-run and single step mode. When the switch s LED is on, you are in free-run mode. This means that all registers in your circuit are

continuously clocked. When the LED is off, you are in single-step mode. This means that the clock is frozen unless you instruct it to go off with switch #9. Switch 9: single-step advance. Pressing this switch while switch 8 is in single-step mode sends exactly one clock pulse to all the registers that use the clock on the kit. This allows you to step through your circuit slowly to facilitate debugging. Switch 9 is functional only when Switch 8 is in off state. Reset button: does a cold boot of the kit. Initializes computational blocks and the underlying logic. NMI button: halts the on-board processor in case it wedges without initializing the computational blocks. LEDs There is a bank of 16 LEDs in each computational block. Different circuit modules use those LEDs in different ways. For instance, echo block uses those LEDs to output each of its 16 Bit input. There are ten LEDs between breadboard and the row of switches. These LEDs can be configured to output the state of the switch (lit = on, not lit = off). You can also use these LEDs to ouput the state of logic level set though DI lines in the IO module. There is one eight digit hex LED display on the first computational block. You can use this LED to display serialized data. Just run the wire that carries serialized data to the second pin from the right. Clocks The kit comes with an internal clock that runs at 20 MHz. A lot of the circuits have implicit clock inputs (Even some combinational circuits have clock inputs!). Most of the clocked circuits use clock that runs slower than the main clock. You can change the frequency of this clock that is used by clocked components by setting Tpd in JTerm. As you learned in class, the critical path is the longest path in a combinational circuit. On these kits, every module has an identical delay, and the critical path is simply the longest path between register elements multiplied by 2. Thus, if you went from a register to an AND gate, to an adder, and back to a register, the critical path length in this example is 6, one for T c-q of the register, one for T pdand, and one fore T pdadd. Your kit will not produce a correct result in free-run mode if you do not set the critical path length correctly. IO Block The white strip on the bottom of the kit is the I/O block. It has pins for power and ground. You will use these if you want certain inputs to be permanently tied to Vcc or GND. You can use DI[0..7] to use the LEDs to output state of a signal (helpful for debugging). Use DO[0..7] to output the state of the switch to a wire that you can run to other part of the circuitry (user inputs to the modules) IO block also has control ROM outputs, to be used when implementing a Beta at the logic level.

Breadboard The upper white block near the bottom of the kit. General breadboarding space. Might be used to add some additional circuit to the lab kit. For example: D/A Data Transmission Data is transferred between different application modules in serialized or non-serialized format. Serialized format is used whenever there is a need to transmit more than one bit of data with a single wire. Each bit is send sequentially in each clock cycle though the same wire. Our implementation transmits the least significant bit first and then works it way up to the most significant bit (total 32 bits). Following waveform graph shows our implementation of serialized transmission. Non serialized format will let you transmit one bit though one wire. Vcc is logical high and GND is logical low. In order to transmit the data you just tie the wire to GND or Vcc depnding on what you Clk Sync Data: 0x1EE 0 1 1 1 0 1 1 1 1 want to transmit. Using the Lab Kit You will use a program called JTerm on the workstation to configure the kit. There should be an icon for JTerm on win98 desktop. Start JTerm by double clicking on that icon. If JTerm icon is not on your desktop, change to JTerm folder at an MS-DOS prompt and start JTerm by typying java JTerm. JTerm is your window into the kit. The left half has a GUI which allows you to configure the computational blocks of the kit. You can also hack in the terminal window on the right half, which gives you a direct access to the ROM monitor running on the kit. There is one-to-one correspondence between the buttons you see on the left half of JTerm and the computational block array on the kit. In JTerm, when you click on a button labelled comp block n, you are presented with a dialog box. The top pulldown menu in this dialog box allows you to set the function of the block. The constant field in this dialog sets the number that is output on the constant generator port (if applicable). State button is active for some of the circuit modules only. If you are using any of those modules (eg. ROM, RAM, Const generator), select the function from the pulldown menu. Click on OK. When you go to the same block configuration for the second time, the

state button will be enabled. When you click on State, relevant state configuration dialog will show up. You will check on Display binary Input for Display block only. Display block will not function if you forget to check this option. General work flow 1 Start JTerm 2 Click on open port (button on bottom left) 3 Make sure the kit is connected to the host, and power it on 4 Wait until the kit finishes its power-on initialization (about 10-15 seconds) 5 Click on computational block buttons to set their functions. 6 Adjust kit switches and clocking according to your design 7 Click Configure Kit. You can watch what JTerm is doing by looking at the MS-DOS window that you used to start JTerm. Configuration takes about a minute the first time, but after that, as long as Use Dirty Bits is selected, small changes take less than a second to update. 8 After stuff stops scrolling by on the MS-DOS window, your kit is now ready to use. 9 If you are using free-run circuit, don t forget to set appropriate critical-path. 10 If you change any of the configurations (with the exception of setting state, clocking, and switches ), you MUST hit Configure Kit again before the changes are uploaded to the kit. 11 If you power down or reset your kit without restarting JTerm, you will have to clear the Use Dirty Bits box for the first configuration, because the dirty bits maintained by JTerm internally are now all invalid. Be sure to reset Use Dirty Bits after the first configuration for faster configuration updates. Revision History: Omprakash Gnawali, Spring 99 Andrew Huang, Fall 98

JTerm Screen Shots