Chapter 8: Memory Management
Chapter 8: Memory Management Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging 8.2 Silberschatz, Galvin and Gagne 2005
Background Program/Code must be brought into memory and placed within a process for it to be run Input queue collection of processes on the disk that are waiting to be brought into memory to run the program User programs go through several steps before being run 8.3 Silberschatz, Galvin and Gagne 2005
Address Binding Physical addresses are bound at three possible times: Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes Load time: Must generate relocatable code if memory location is not known at compile time Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers). 8.4 Silberschatz, Galvin and Gagne 2005
Multi-Step Processing of a User Program 8.5 Silberschatz, Galvin and Gagne 2005
Logical vs. Physical Address Space Logical address generated by the CPU; also referred to as virtual address. Program only uses the logical address, it never sees the physical address Physical address address seen by the memory unit/controller Logical Physical 8.6 Silberschatz, Galvin and Gagne 2005
Dynamic Loading Concept: Routine is not loaded until it is called Advantages Better memory-space utilization; unused routine is never loaded Useful when large amounts of code are needed to handle infrequently occurring cases No special support from the operating system is required implemented through program design. User program handles the details itself. 8.7 Silberschatz, Galvin and Gagne 2005
Dynamic Linking Concept: Linking postponed until execution time Technique Small stub code locates/loads the library routine Address of loaded routine replaces placeholder address Very useful for reusable libraries 8.8 Silberschatz, Galvin and Gagne 2005
Diagram of Swapping 8.9 Silberschatz, Galvin and Gagne 2005
Swapping Concept: A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution Backing store fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped 8.10 Silberschatz, Galvin and Gagne 2005
Memory Mgmt - Contiguous Allocation (History Lesson) Main memory usually into two partitions: Operating System: usually held in low memory User Processes: then held in high memory Multiple-partition allocation Hole block of available memory; holes of various size are scattered throughout memory Process is placed in a hole large enough to accommodate it OS maintains allocated & free partitions 8.11 Silberschatz, Galvin and Gagne 2005
Contiguous Allocation - Diagram OS OS OS OS process 5 process 5 process 5 process 5 process 9 process 9 process 8 process 10 process 2 process 2 process 2 process 2 8.12 Silberschatz, Galvin and Gagne 2005
Contiguous Allocation - Technique How to satisfy a request of size n from a list of free holes First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. First-fit and best-fit better than worst-fit in terms of speed and storage utilization 8.13 Silberschatz, Galvin and Gagne 2005
Fragmentation External Fragmentation total memory space exists to satisfy a request, but it is not contiguous Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time I/O problem What if DMA is transferring into a memory block? 8.14 Silberschatz, Galvin and Gagne 2005
Paging Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes) Divide logical memory into blocks of same size called pages. Keep track of all free frames To run a program of size n pages, need to find n free frames and load program Set up a page table to translate logical to physical addresses Internal fragmentation 8.15 Silberschatz, Galvin and Gagne 2005
Paging Example 8.16 Silberschatz, Galvin and Gagne 2005
Paging Example 8.17 Silberschatz, Galvin and Gagne 2005
Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page table: valid indicates that the associated page is in the process logical address space, and is thus a legal page invalid indicates that the page is not in the process logical address space 8.18 Silberschatz, Galvin and Gagne 2005
Valid (v) or Invalid (i) Bit In A Page Table 8.19 Silberschatz, Galvin and Gagne 2005
Page Table Too Big? Example: Address space of 2 64 Page Size of 4K Page Table of 450GB (entries)! Solution: Two-Way page table A page table of page tables 8.20 Silberschatz, Galvin and Gagne 2005
Two-Level Page-Table Scheme 8.21 Silberschatz, Galvin and Gagne 2005
Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes Private code and data Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space 8.22 Silberschatz, Galvin and Gagne 2005
Shared Pages Example 8.23 Silberschatz, Galvin and Gagne 2005
Segmentation Memory-management scheme that supports user view of memory A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays 8.24 Silberschatz, Galvin and Gagne 2005
User s View of a Program 8.25 Silberschatz, Galvin and Gagne 2005
Logical View of Segmentation 1 1 4 2 3 4 2 3 user space physical memory space 8.26 Silberschatz, Galvin and Gagne 2005
Example of Segmentation 8.27 Silberschatz, Galvin and Gagne 2005
Sharing of Segments 8.28 Silberschatz, Galvin and Gagne 2005
Intel Pentium Segmentation Supports both pure segmentation and segmentation with paging Page size can be 4KB or 4MB Two level paging scheme with 4KB pages Segment can be up to 4GB Max number of segments per process is 16K Two Partitions in each process 8K segments are private (LDT) 8K segments are shared (GDT) Logical Address is a (selector,offset) Selector is 16 bits [ segment (13), g (1), protection (2) ] Offset is 32 bits 8.29 Silberschatz, Galvin and Gagne 2005
Intel Pentium Segmentation Linear address is formed by looking up the segment in the descriptor table and adding the offset Selector Offset Descriptor Table Base Limit 32 bit linear address 8.30 Silberschatz, Galvin and Gagne 2005
Intel Pentium Segmentation In two level paging scheme, with 4KB pages, linear address looks like this: Page 1 Page 2 Page Offset 10 10 12 8.31 Silberschatz, Galvin and Gagne 2005
End of Chapter 8