Experimentation of a 1-pixel bit reconfigurable ternary optical processor

J Shanghai Univ (Engl Ed), 2011, 15(5): 430 436 Digital Object Identifier(DOI): 10.1007/s11741-011-0764-2 Experimentation of a 1-pixel bit reconfigurable ternary optical processor WANG Hong-jian (fi è), JIN Yi (7 ), OUYANG Shan (î ì), ZHOU Yu ( ü) School of Computer Engineering and Science, Shanghai University, Shanghai 200072, P. R. China Shanghai University and Springer-Verlag Berlin Heidelberg 2011 Abstract A detailed experiment of 1-pixel bit reconfigurable ternary optical processor (TOP) is proposed in the paper. 42 basic operation units (BOUs) and 28 typical logic operators of the TOP are realized in the experiment. Results of the test cases elaborately cover the every combination of BOUs and all the nine inputs of ternary processor. Both the experiment process and results analysis are given in this paper. The experimental results demonstrate that the theory of reconfiguring a TOP is valid and that the reconfiguration circuitry is effective. Keywords ternary optical processor (TOP), decrease-radix design, basic operation units (BOUs), reconfigurability, reconfiguration circuitry Introduction With the increase of the computing demands which involving parallels algorithm and huge amount of data or/and large value data, the current super computers become more and more unsuitable in power consumption, data bus width and reconfigurable hardware. Compared with electronic computers, their optical counterparts with huge data bus and reconfigurable processor are believed to be more suitable for solving complex problems. As one type of optical computers, the ternary optical processor (TOP) uses 3 optical states (2 polarization directions of the light that are orthogonal to each other plus a third state denoting the total darkness) to represent information. A TOP is constructed using liquid crystal and polarizers [1]. From a mass of pixels on liquid crystal the TOP gets a mass of data bits and a huge data bus, which is suited to handle a huge amount of data simultaneously or very large data. On the other hand, with the progress of the decrease-radix design theory [2 8] and management strategy [9 12] of numerous data bits, the research of TOP has entered a practical stage of both implementable and applicable. In 2010, a design of reconfigurable TOP which makes operands with up to thousands bits has been proposed [13],and there is a strict experiment to test the design on validity, effectiveness and applicability. The theory details and simple experiment results of the design will be published in [13]. This paper reported the details of the experiment for a 1 pixel-bit reconfigurable TOP and simply introduced the theory results. The remainder of this paper is organized as follows. Section 1 firstly introduces the basics of TOP s reconfiguration and then focuses on the description of the reconfiguration circuitry. Section 2 illustrates the 1-pixel bit reconfigurable TOP experimental system on which the following tests were carried. Section 3 elaborately chooses 42 basic operation unit (BOU) test cases and 28 typical logic operator test cases that can cover various kinds of BOU combinations. Section 4 discusses the detailed experiment process consisting of both preparation work and operation procedure. Section 5 discusses the experiment results of two concrete test cases. Section 6 gives the conclusion as well as the future work. 1 Reconfiguration of TOP From the decrease-radix design [2] theory, one can know that any tri-value logic operator can be structured via assembling no more than 6 BOUs and that the BOUs have 18 types in total [2]. For TOC the 18 BOU types have the same abstract structure: holding a liquid pixel in the middle of two polaroid sheets. The only differences between them are the polarization directions of the polaroid and the innate optical rotation Received Apr.25, 2011; Revised June 27, 2011 Project supported by the National Natural Science Foundation of China (Grant No.61073049), the Shanghai Leading Academic Discipline Project (Grant No.J50103), and the Doctorate Foundation of Education Ministry of China (Grant No.20093108110016) Corresponding author JIN Yi, Ph D, Prof, E-mail: yijin@shu.edu.cn

J Shanghai Univ (Engl Ed), 2011, 15(5): 430 436 431 of the liquid crystal [3]. Based on the BOU abstract structure, one type of a reconfigurable TOP has been designed, as well as the corresponding reconfiguration commands and processes. With these reconfiguration methods, a TOC can be successfully reconfigured into a specific ternary logic operator according to a user s request. In addition, a compound logic operator that comprises various logic operations can be constructed [13]. Figure 1 depicts a reconfigurable BOU s structure. In Fig.1, transmission paths of the optical signals are denoted by dashed lines, while transmission paths of the electrical signals are denoted by real lines. The main optical path involves a light source (module labeled by μ), an encoder, a sandwich-like structure, and a phototube ( 21) in the front. The encoder [14] consists of 2 liquid crystal pixels (οand ß), and 2 vertical polarizers (fland ffi). The sandwich-like structure consists of 2 polarizers ( 14 and 15) with uncertain type holding a liquid crystal ρin between. With the different polarization direction of polarizers 14 and 15, the main optical path is divided into 4 areas, i.e., VV, VH, HH and HV areas. Four pixels occupying the same site respectively on VV, VH, HH and HV areas are called as one pixel bit. The controlling optical path involves a light source (ν). An encoder consists of two liquid crystal pixels (ffand fi) and two vertical polarizers ( 10 and 11). A vertical polarizer ( 12) followed by a phototube ( 20), and a horizontal polarizer ( 13) followed by a phototube ( 19). The function of the encoder is to convert the binary electrical signals to corresponding ternary optical signals while the function of the decoder is to convert the optical signals to electrical signals. The function of the sandwich-like structure is optical computing. Fig.1 Structure of a reconfigurable BOU To transform a BOU abstract structure into a specific logic optical operator, a reconfiguration process is required. This process follows the TOC s basic principle of light for handling data computation, and electricity for control, and is implemented by a reconfiguration circuitry. The part of reconfiguration circuitry is in the square frame drawn by dotted lines in Fig.1. Modules labeled by 16, 17 and 18 XOR gates, 22, 23 24 tri-state gates, 25 an OR gate, and 26 a grounding current-limiting resistor. A reconfiguration instruction (R 1 R 8 ) is 8-bit including a 6-bit reconfiguration command and a 2-bit addressing code. The reconfiguration of a BOU is carried out by assigning the appropriate values to the 6-bit reconfiguration command register (R 1 R 6 ). The addressing code (R 7 R 8 )is adopted to address the reconfiguration command registers by a 2 4 decoder ( 27). When a main optical path is not in use, the reconfiguration instruction is set to be a closing code. After setting a closing code, the main optical path s output remains in the state of total darkness no matter what values A 1, A 2, B 1 and B 2 take [13]. With the reconfiguration circuitry users can easily configure the abstract BOU structure into any of the 42 specific BOUs (including 18 singleton BOUs, 18 compound BOUs that are composed of 2 singleton BOUs, and 6 compound BOUs that are composed of 3 singleton BOUs) and reconfigure it for every computation task. The corresponding reconfiguration process can be simply summarized as firstly allocating pixel bits for each computation task and then assigning the appropriate values to the reconfiguration instruction registers of appointed pixel bits. In the reconfigurable TOP with a word length of thousands bits, this procedure can be conveniently completed by a program called a reconfiguration routine.

432 J Shanghai Univ (Engl Ed), 2011, 15(5): 430 436 2 1-pixel bit reconfigurable TOP The 1-pixel bit reconfigurable TOP experimental system is shown in Fig.2. The right part forms one processor s main optical path and is made up of 3 identical TN-typed stroke segment LCDs and 4 polarizers among them. When designing this part we firstly put the right polarizers on both sides of the LCD s chosen stroke segments. Then we extracte the chosen stroke segments corresponding control cables out from its DIP encapsulation, and stuck the 3 LCDs together tightly with the corresponding stroke segments in each LCD layer overlap completely. After fixing the device of main optical path on the experimental platform, a filament lamp is used as the light source from the back side of the LCD and 4 phototubes as the decoders on its front side. Each phototube sticks to a chosen stroke segment to sample the output optical signals from it. The 4 segments locate respectively in 4 different areas of LCD: HV area, HH area, VV area, and VH area. Fig.2 1-pixel bit reconfigurable TOP In Fig.2, the left part is a DICE-SEM/digital analogue experiment box, whose programmable logic circuits of ACEX1K can be used to implement the TOP s reconfiguration circuitry and other necessary circuits of the 1-pixel bit reconfigurable TOP experimental system. The switches K 1 K 8 (d 0 d 7 ) at the bottom of the box areusedtoset-upther 1 R 8 of reconfiguration instruction register through data bus. K 9 (CLK1) is for addressing the reconfiguration instruction register and can be viewed as its enable signal. K 10 and K 11 are the input signals to the encoder of the main optical path (i.e., a 2 and a 1 ). K 13 and K 14 are the inputs to the encoder of the controlling optical path (i.e., bh and bv), and they also connect to the controlling port of the LED L 2 and L 1 respectively. K 12 (CLK2) is the output enable signal for the 2 encoders of the main and controlling optical paths. On the left of the switches there are 16 groups of LEDs. Among these groups of LEDs, L 5, L 6,andL 7 are for monitoring the actual output signals, which will directly control the 3 layers of LCD respectively, of the reconfiguration circuitry in VV area. Likewise, L 8, L 9,andL 10 are for monitoring the actual output signals of the reconfiguration circuitry in HV area; L 11, L 12,andL 13 are for monitoring the actual output signals of the reconfiguration circuitry in VH area; L 14, L 15,andL 16 are for monitoring the actual output signals of the reconfiguration circuitry in HH area. The 12 groups of LEDs, whose purposes are run-time state monitoring, are very helpful to diagnose reasons when problems occur. The LED L 1 and L 2 in the left bottom of the experiment box have a phototube sealed on each of them, and in this way the controlling optical path is built. The switches K 14 and K 13 control the states of red LED L 1 and L 2. The 2 phototubes correspond to 19 and 20 in Fig.1 and their output signals connect to the reconfiguration circuitry s relevant ports on the experiment box. Meanwhile, in order to monitor the actual results of them, the 2 phototubes output signals also connect to the 2 digital number tubes LED1 and LED2 in the top left corner of the experiment box. The computation result is shown in the 3 digital number tubes in the middle of the box s top area, where LED4 displays 1 if the computation result is the optical state of a total darkness (W ); LED5 displays 1 if the result is vertically polarized light (V ); and LED6 displays 1 if the result is horizontally polarized light (H). The results are decided by the output signals of the 4 phototubes sticking to the front side of the device of main optical path. 3 Test cases selection To verify the function of the reconfiguration circuitry, a series of experiments of both the BOUs and logic operators are required. In this paper, we choose 50 test cases which involve 22 test cases for BOU and 28 for logic operator. 3.1 Test cases for BOU In general, all the 42 BOUs need to be tested one by one. Every BOU is configured from a pixel of TOP via using time-sharing switches K 1 K 6 to set each reconfiguration command. In order to simplify the experimental procedure, the BOUs with the same reconfiguration command are put together in one test case so that they can be tested in the same time. By this method, the 42 BOUs are included in 22 test cases actually. 3.2 Test cases for logic operators In prior preparing work, we spend about 5 min on testing one logic operator. Thus the time of testing all the 19 683 logic operators would be about 1 640 h. In order to keep the balance between the test time and quality, we choose 28 typical logic operators (see Table 1) that cover every combination of BOUs. According to BOU numbers, the 28 operators are divided into 4 groups, listing in different columns of Table 1. Every BOU included in one operator is located on different area of the main optical path. The typical logic operators are described as follows:

J Shanghai Univ (Engl Ed), 2011, 15(5): 430 436 433 (i) 14 logic operators that listed in the left 4 columns of Table 1 are all made up of 4 BOUs which located on different areas of the main optical path respectively. The operator in the left-most column has same reconfiguration command, marked as X 1, for its 4 BOUs. However, the X 1 is different to each operator. Each operator in the second column has 2 different reconfiguration commands, mark as X 1 and X 2 respectively. Each operator in the third column has 3 reconfiguration commands, X 1, X 2,andX 3. Each operator in the 4th column has 4 reconfiguration commands X 1, X 2, X 3,andX 4.The 14 test cases cover the logic operators that are made up of 4 BOUs among the total 19 683 ones. (ii) Four logic operators that listed in the 5th column of Table 1 are all made up of 3 BOUs. These operators have one closing code, marked as 0, on a certain area and one same reconfiguration command, marked as X 5, for other 3 areas. Similarly, 6 logic operators that are all made up of 2 BOUs with the same reconfiguration command are listed in the 6th column of Table 1, and 4 Table 1 Logic operators composed of 4 BOUs Test cases of 28 typical logic operators Logic operators Logic operators Logic operators composed of 3 BOUs composed of 2 BOUs composed of 1 BOU X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 2 X 1 X 1 X 2 X 3 X 1 X 2 X 3 X 4 0X 5 X 5 X 5 00X 6 X 6 000X 7 X 1 X 1 X 2 X 1 X 2 X 3 X 1 X 1 X 5 0X 5 X 5 0X 6 0X 6 00X 7 0 X 1 X 2 X 1 X 1 X 1 X 2 X 3 X 1 X 5 X 5 0X 5 0X 6 X 6 0 0X 7 00 X 2 X 1 X 1 X 1 X 2 X 1 X 3 X 1 X 5 X 5 X 5 0 X 6 00X 6 X 7 000 X 1 X 1 X 2 X 2 X 1 X 2 X 3 X 1 X 6 0X 6 0 X 1 X 2 X 2 X 1 X 2 X 1 X 1 X 3 X 6 X 6 00 Table 2 Reconfiguration commands of test cases Type HV HH VV VH X 1 X 1 X 1 X 1 01 001000 00 001000 11 001000 10 001000 X 1 X 1 X 1 X 2 01 001000 00 001000 11 001000 10 010000 X 1 X 1 X 2 X 1 01 001000 00 001000 11 001001 10 001000 X 1 X 2 X 1 X 1 01 001000 00 001011 11 001000 10 001000 X 2 X 1 X 1 X 1 01 010000 00 001000 11 001000 10 001000 X 1 X 1 X 2 X 2 01 001100 00 001100 11 001000 10 001000 X 1 X 2 X 2 X 1 01 010000 00 001000 11 001000 10 010000 X 1 X 1 X 2 X 3 01 001100 00 001100 11 001001 10 001000 X 2 X 3 X 1 X 1 01 001100 00 001011 11 001000 10 001000 X 1 X 2 X 3 X 1 01 001000 00 100111 11 010101 10 001000 X 2 X 1 X 3 X 1 01 001100 00 010100 11 001001 10 010100 X 1 X 2 X 3 X 1 01 001000 00 100111 11 010101 10 001000 X 2 X 1 X 1 X 3 01 010000 00 001000 11 001000 10 100000 X 1 X 2 X 3 X 4 01 001100 00 001011 11 010101 10 010000 0X 5 X 5 X 5 Closing code 00 001000 11 001000 10 001000 X 5 0X 5 X 5 01 001000 Closing code 11 001000 10 001000 X 5 X 5 0X 5 01 001000 00 001000 Closing code 10 001000 X 5 X 5 X 5 0 01 001000 00 001000 11 001000 Closing code 00X 6 X 6 Closing code Closing code 11 001000 10 001000 0X 6 0X 6 Closing code 00 001000 Closing code 10 001000 0X 6 X 6 0 Closing code 00 001000 11 001000 Closing code X 6 00X 6 01 001000 Closing code Closing code 10 001000 X 6 0X 6 0 01 001000 Closing code 11 001000 Closing code X 6 X 6 00 01 001000 00 001000 Closing code Closing code 000X 7 Closing code Closing code Closing code 10 001000 00X 7 0 Closing code Closing code 11 001000 Closing code 0X 7 00 Closing code 00 001000 Closing code Closing code X 7 000 01 001000 Closing code Closing code Closing code

434 J Shanghai Univ (Engl Ed), 2011, 15(5): 430 436 logic operators that are all made up of only one BOU are listed in the 7th column. Considering the combinations of BOUs with different reconfiguration commands on different areas have been referred in the former 14 ones, so each of these 14 logic operators is designed to have one same reconfiguration command on different areas. Together with the former 14 ones, 4 logic operators listed in the 5th column cover the logic operators that are made up of 3 BOUs among the total 19 683 ones; 6 logic operators listed in the 6th column cover the logic operators that are made up of 2 BOUs among the total 19 683 ones; 4 logic operators listed in the 7th column cover the logic operators that are made up of only one BOU among the total 19 683 ones. In Table 1, for each operator the default arrangement order of its 4 areas is: HV, HH, VV, and VH. The 28 logic operators specific reconfiguration commands on each area are listed in Table 2. 4 Experiment process 4.1 Preparation According to the test cases in the previous section, a BOU illustration page (BIP), as in the upper left of Figs.3 and 4, for every test case is prepared. The BIP includes the number, name, reconfiguration instruction and truth table of every BOU on every area. In addition, the truth table of logic operator is also included in the right of the BIP. For not using areas, the reconfiguration instruction is the closing code. There are 50 BIPs in total, including 22 for BOU test cases and 28 for logic operator test cases. For each test case of 2-input ternary logic operation there are 9 input combinations. The logic operator must be tested for every input combination. In order to show the input combinations, one experimental-steps page (ESP) is prepared as in the upper right of Figs.3 and 4. The experiment devices should be arranged carefully so that the complete panel of the experimental box, main optical path, BIP, ESP, and a hand signal marking the experiment results (thumb up for success and down for failure) can be pictured within one photo. 4.2 Procedure (i) According to the basic reconfiguration circuitry as shown in Fig.1, the corresponding project circuitries of the 1-pixel bit reconfigurable TOP, which is designed by the computer aided engineering (CAE) software MAX+PLUS II. The circuits include the reconfiguration circuitry in every area of the LCD, outputsuperimposition circuit, and LCD driver circuit. Download the project circuitries into the experimental box to construct the real circuitries. (ii) Settle the BIP of current test case on the experiment box. According to the BIP, set the switches K 1 K 8 to corresponding reconfiguration instruction or closing codes for one area. Then use the switch K 9 to send them into the reconfiguration instruction register. Repeat this procedure 3 times more to complete the configuration of all 4 areas. So far the reconfiguration process is done. Take the test case of operator X 1 X 2 X 3 X 4 as shown in Fig.3 for example. According to the information on its BIP paper, firstly, set K 8 K 1 to 01001100 and enable K 9 to send this reconfiguration instruction into its register in HV area. Then, set K 8 K 1 to 00001011 and enable K 9 to send this reconfiguration instruction into its register in HH area. Subsequently, set K 8 K 1 to 11010101 and enable K 9 to send this reconfiguration instruction into its register in VV area. At last, set K 8 K 1 to 10010000 and enable K 9 to send this reconfiguration instruction into its register in VH area. By far, the TOP is reconfigurated into a specific X 1 X 2 X 3 X 4 type logic operator. (iii) Settle the experimental-steps paper (ESP) of current test case on the experiment box. According to the ESP, configure the encoding commands of main optical path and controlle optical path by setting the switches K 10 (a2), K 11 (a1), K 13 (bh), and K 14 (bv). Take the test case of operator X 1 X 2 X 3 X 4 asshown in Fig.3 for example. According to the information on its experimental-steps paper, stepß is undergone. Set K 10 to 0, K 11 to 1, K 13 to 1, and K 14 to 0. Then enable K 12 to make the settings work. Observe the output light state of c, from both LCD and the experiment box. Record the result, signal it by hand, and have the experimental result pictured. (iv) Change the ESP and repeat step (iii) until all the 9 input combinations of current test case finish their experiments. Through this process, the input of controlling light (b) is successively configured into total darkness (W ), horizontally polarized light (H), and vertically polarized light (V ). Under each of the three states of controlling light, the light of main optical path is successively configured into W, H, andv. (v) Change the test case and repeat steps (ii) (iv), until all the 50 chosen test cases finish their experiments. All the 42 BOUs and 28 typical logic operators have been examined on the 1-pixel bit reconfigurable TOP. 5 Experiment results All the 50 test cases have been tested for all the possible 9 input combinations, and 450 photos have been taken to record the experiment results. The results comply with their theoretical prediction, which proves the correctness of the TOP reconfiguration theory and the effectiveness of the reconfiguration structures. In this section, two experiment results are discussed, including one result for the BOU test and one for the logic operator test.

J Shanghai Univ (Engl Ed), 2011, 15(5): 430 436 435 Figure 3 shows the result of an experiment for the BOU test. The BIP (upper left page) shows that the BOU being examined is with number 13, whose corresponding main optical path has only the HH area set up with reconfiguration instruction of 00100011 and all the other 3 areas set up with closing codes. Right to this page is the ESP listing the 9 experimental steps corresponding to all the possible 9 input combinations. In particular, this photo illustrates the experiment results of step ß, wherea = W and b = H. The correct output state for this input combination should be H, which is verified by the experiment results: Only the HH area of the main optical path has a light dot on it, and at the same time, the LEDs on the experiment box demonstrate the correct decoding for the computation results (i.e., W =0, V =0, and H=1). It is clear that the actual results are consistent with their theoretical prediction, which correspondingly leads to a hand signal marking success. Figure 4 shows the results of an experiment for the logic operator test. The BIP shows that the operator being examined is X 1 X 2 X 3 X 4 type which consists of BOU A 4 with reconfiguration instruction of 01001100 in HV area, BOU A 1 with reconfiguration instruction of 00001011 in HH area, BOU A 8 with reconfiguration instruction of 11010101 in VV area, and BOU A 11 with reconfiguration instruction of 10010000 in VH area. The same as Fig.3, step ßon the ESP is being carried out. The correct output state for this input combination should be V, which is verified by the experimental results: Only the VV area of the main optical path has a light dot on it, and at the same time, the LEDs on the experiment box demonstrate the correct decoding for the computation results (i.e., W =0, V =1, and H=0). Correspondingly, a hand signal marking success is made. 6 Conclusions and future work Elaborate test experiments of the entire 42 BOUs and 28 typical logic operators on 1-pixel bit reconfigurable TOP are given in this paper. The experiment results demonstrate that the theory for reconfiguring a TOP is valid and that the reconfiguration circuitry functions effectively. Based on the achievements of this experimentation, the next step that we are going to take is to build a parallel reconfigurable TOP with numerous data bits. The parallel reconfiguration circuit with thousand data bits has already been studied and will be implemented by FPGA in the future. The design is featured by parallel control, high speed of reconfiguration, flexible scalability, and high integration. Acknowledgments The authors would like to express their sincere gratefulness to Profs. SHEN Yun-fu and PENG Jun-jie for their helpful suggestions and comments. We also thank to Ph D Candidate SONG Kai and Master Candidate GAO Huan, School of Computer Engineering and Science, for their cooperation works of all involved parts. References Fig.4 Fig.3 Result of BOU 00100011 Result of X 1X 2X 3X 4 typeoperator [1] Jin Y, He H C, Lü YT. Ternary optical computer principle [J]. Science in China (Series F), 2003, 46(2): 145 150. [2] Yan JY, Jin Y, Zuo K Z. Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer [J]. Science in China (Series F), 2008, 51(10): 1415 1426. [3] Jin Y, Shen Y F, Peng J J, Xu S Y, Ding G T, Yue D J, You H H. Principles and construction of MSD adder in ternary optical computer [J]. Science China Information Sciences, 2010, 53: 2159 2168. [4] Shen ZY, Jin Y, Peng J J. Experimental system of ternary logic optical computer with reconfigurability [C]// The 4th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Advanced Optical Manufacturing Technologies, Chengdu, China. 2009, DOI: 10.1117/12.831039. [5] Li Mei, Jin Yi, He Hua-can, Teng Liang. Optical vector-matrix multiplication based on ternary optical processor [J]. Application Research of Computers, 2009, 26(8): 2839 2841 (in Chinese).

436 J Shanghai Univ (Engl Ed), 2011, 15(5): 430 436 [6] Wang X C, Peng J J, Jin Y, Li M, Shen Z Y, Ouyang S. Vector-matrix multiplication based on ternary optical computer [C]// The 2nd International Conference on High Performance Computing and Application, Shanghai, China. 2009, DOI:10.1007/978-3-642-11842-5 59. [7] Teng L, Peng J J, Jin Y, Li M. A cellular automata calculation model based on ternary optical computer [C]// The 2nd International Conference on High Performance Computing and Application, Shanghai, China. 2009, DOI:10.1007/978-3-642-11842-5 52. [8] Shen Yun-fu, Fan Xiao-ling. Solving TSP based on ternary optical computer [J]. Application Research of Computers, 2011, 28(6): 2184 2187 (in Chinese). [9] Jin Yi. Management strategy of data bits in ternary optical computer [J]. Journal of Shanghai University (Natural Science Edition), 2007, 13(5): 519 523 (in Chinese). [10] Zhan Xiao-qi, Peng Jun-jie, Jin Yi, Wang Xian-chao. The static allocation strategy of data bits resources of ternary optical computer [J]. Journal of Shanghai University (Natural Science Edition), 2009, 15(5): 528 533 (in Chinese). [11] Zhang Z Y, Jin Y, Yan J Y, Peng J J. Designand realization of remote interactive system of ternary optical computer [J]. Computer Engineering and Design, 2009, 30(10): 2411 2418. [12] LI S F, Jin Y. Mapping technology from componentspixels to data-bits of ternary optical computer [J]. Computer Engineering and Design, 2010, 31(5): 1077 1080. [13] Jin Y, Wang H J, Ouyang S, Zhou Y, Shen Y F, Peng J J, Liu X M. Principles, structures, and implementation of reconfigurable ternary optical processors [J]. Science in China (Series F), 2011, DOI: 10.1007/S11432-011-4446-X. [14] Yan Jun-yong, Jin Yi, Sun Hao. Study on the feasibility of coding and decoding multi-bit ternary optical signal used in ternary optical computer [J]. Computer Engineering, 2004, 30(14): 175 177 (in Chinese). (Editor HONG Ou)