Random-ccess Memory (RM) Lecture 13 The Memory Hierarchy Topics Storage technologies and trends Locality of reference Caching in the hierarchy Key features RM is packaged as a chip. Basic storage unit is a cell (one bit per cell). Multiple RM chips form a. Static RM (SRM( SRM) See Lecture 7B C2 page 12 Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRM. Dynamic RM (DRM( DRM) Each cell stores bit with a capacitor and transistor. Value must be refreshed every 1-1 ms. Sensitive to disturbances. Slower and cheaper than SRM. F13 2 Datorarkitektur 29 SRM vs DRM Summary Conventional DRM Organization d x w DRM: dw total bits organized as d supercells of size w bits Tran. ccess per bit time Persist? Sensitive? Cost pplications 16 x 8 DRM chip cols 1 2 3 SRM 6 1X Yes No 1X cache memories DRM 1 1X No Yes 1X Main memories, frame buffers (to CPU) 2 bits addr 8 bits data rows 1 2 3 supercell (2,1) F13 3 Datorarkitektur 29 internal row buffer F13 4 Datorarkitektur 29
Reading DRM Supercell (2,1) Step 1(a): Row access strobe (RS( RS) ) selects row 2. Step 1(b): Row 2 copied from DRM array to row buffer. RS = 2 2 addr 16 x 8 DRM chip 1 rows 2 cols 1 2 3 Reading DRM Supercell (2,1) Step 2(a): Column access strobe (CS( CS) ) selects column 1. Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. To CPU CS = 1 2 addr 16 x 8 DRM chip 1 rows 2 cols 1 2 3 8 data 3 supercell (2,1) 8 data 3 internal row buffer F13 5 Datorarkitektur 29 supercell internal row buffer (2,1) internal buffer F13 6 Datorarkitektur 29 Memory Modules addr (row = i, col = j) DRM DRM 7 bits bits bits bits bits bits bits bits 56-63 48-55 4-47 32-39 24-31 16-23 8-15 -7 63 56 55 48 47 4 39 32 31 24 23 16 15 8 7 64-bit doubleword at main address 64-bit doubleword : supercell (i,j) 64 MB module consisting of eight 8Mx8 DRMs Memory Enhanced DRMs ll enhanced DRMs are built around the conventional DRM core. Fast page mode DRM (FPM DRM) ccess contents of row with [RS, CS, CS, CS, CS] instead of [(RS,CS), (RS,CS), (RS,CS), (RS,CS)]. Extended data out DRM (EDO DRM) Enhanced FPM DRM with more closely spaced CS signals. Synchronous DRM (SDRM) Driven with rising clock edge instead of asynchronous control signals. Double data-rate synchronous DRM (DDR SDRM) Enhancement of SDRM that uses both clock edges as control signals. Video RM (VRM) Like FPM DRM, but output is produced by shifting row buffer Dual ported (allows concurrent reads and writes) F13 7 Datorarkitektur 29 F13 8 Datorarkitektur 29
Nonvolatile Memories DRM and SRM are volatile memories Lose information if powered off. Nonvolatile memories retain value even if powered off. Generic name is read-only (ROM). Misleading because some ROMs can be read and modified. Typical Bus Structure Connecting CPU and Memory bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. Types of ROMs CPU chip Programmable ROM (PROM) Eraseable programmable ROM (EPROM) Electrically eraseable PROM (EEPROM) Flash system bus bus Firmware Program stored in a ROM Boot time code, BIOS (basic inputouput system) IO bridge main graphics cards, s. F13 9 Datorarkitektur 29 F13 1 Datorarkitektur 29 Memory Read Transaction (1) CPU places address on the bus. Memory Read Transaction (2) Main reads from the bus, retreives word x and places it on the bus. Load operation: movl, Load operation: movl, IO bridge main x IO bridge main x x F13 11 Datorarkitektur 29 F13 12 Datorarkitektur 29
Memory Read Transaction (3) CPU read word x from the bus and copies it into register. Memory Write Transaction (1) CPU places address on bus. Main reads it and waits for the corresponding data word to arrive. Load operation: movl, Store operation: movl, x y IO bridge main IO bridge main x F13 13 Datorarkitektur 29 F13 14 Datorarkitektur 29 Memory Write Transaction (2) CPU places data word y on the bus. Memory Write Transaction (3) Main read data word y from the bus and stores it at address. Store operation: movl, Store operation: movl, y y IO bridge y main IO bridge main y F13 15 Datorarkitektur 29 F13 16 Datorarkitektur 29
Disk Geometry Disk Geometry (Muliple-Platter View) Disks consist of platters,, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. tracks surface track k gaps ligned tracks form a cylinder. surface surface 1 surface 2 surface 3 surface 4 surface 5 cylinder k platter platter 1 platter 2 sectors F13 17 Datorarkitektur 29 F13 18 Datorarkitektur 29 Disk Capacity Capacity: maximum number of bits that can be stored. Vendors express capacity in units of gigabytes (GB), where 1 GB = 1^9. Capacity is determined by these technology factors: Recording density (bitsin): number of bits that can be squeezed into a 1 inch segment of a track. Track density (tracksin): number of tracks that can be squeezed into a 1 inch radial segment. real density (bitsin2): product of recording and track density. Modern s partition tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors, determined by the circumference of innermost track. Each zone has a different number of sectorstrack F13 19 Datorarkitektur 29 Computing Disk Capacity Capacity = Example: 512 bytessector (# bytessector) x (avg. # sectorstrack) x (# trackssurface) x (# surfacesplatter) x (# platters) 3 sectorstrack (on average) 2, trackssurface 2 surfacesplatter 5 platters Capacity = 512 x 3 x 2 x 2 x 5 = 3,72,, = 3.72 GB F13 2 Datorarkitektur 29
Disk Operation (Single-Platter View) Disk Operation (Multi-Platter View) The surface spins at a fixed rotational rate The readwrite head is attached to the end of the arm and flies over the surface on a thin cushion of air. readwrite heads move in unison from cylinder to cylinder arm By moving radially, the arm can position the readwrite head over any track. F13 21 Datorarkitektur 29 F13 22 Datorarkitektur 29 Disk ccess Time verage time to access some target sector approximated by : Taccess = Tavg seek + Tavg rotation + Tavg transfer Seek time (Tavg seek) Time to position heads over cylinder containing target sector. Typical Tavg seek = 9 ms Rotational latency (Tavg rotation) Time waiting for first bit of target sector to pass under rw head. Tavg rotation = 12 x 1RPMs x 6 sec1 min Transfer time (Tavg transfer) Time to read the bits in the target sector. Tavg transfer = 1RPM x 1(avg # sectorstrack) x 6 secs1 min. Disk ccess Time Example Given: Rotational rate = 7,2 RPM verage seek time = 9 ms. vg # sectorstrack = 4. Derived: Tavg rotation = 12 x (6 secs72 RPM) x 1 mssec = 4 ms. Tavg transfer = 672 RPM x 14 secstrack x 1 mssec =.2 ms Taccess = 9 ms + 4 ms +.2 ms Important points: ccess time dominated by seek time and rotational latency. First bit in a sector is the most expensive, the rest are free. SRM access time is about 4 nsdoubleword, DRM about 6 ns Disk is about 4, times slower than SRM, 2,5 times slower then DRM. F13 23 Datorarkitektur 29 F13 24 Datorarkitektur 29
Logical Disk Blocks Modern s present a simpler abstract view of the complex sector geometry: The set of available sectors is modeled as a sequence of b-sized logical blocks (, 1, 2,...) Mapping between logical blocks and actual (physical) sectors Maintained by hardwarefirmware device called. Converts requests for logical blocks into (surface,track,sector) triples. llows to set aside spare cylinders for each zone. ccounts for the difference in formatted capacity and maximum capacity. F13 25 Datorarkitektur 29 IO Bus CPU chip system bus bus IO main bridge IO bus Expansion slots for other devices such USB graphics as network adapters. adapter mouse keyboard monitor F13 26 Datorarkitektur 29 Reading a Disk Sector (1) CPU chip CPU initiates a read by writing a command, logical block number, and destination address to a port (address) associated with. Reading a Disk Sector (2) CPU chip Disk reads the sector and performs a direct access (DM) transfer into main. main main IO bus IO bus USB graphics adapter USB graphics adapter mouse keyboard monitor mouse keyboard monitor F13 27 Datorarkitektur 29 F13 28 Datorarkitektur 29
Reading a Disk Sector (3) CPU chip When the DM transfer completes, the notifies the CPU with an interrupt (i.e., asserts a special interrupt pin on the CPU) Storage Trends SRM metric 198 1985 199 1995 2 2:198 $MB 19,2 2,9 32 256 1 19 access (ns) 3 15 35 15 2 1 main DRM metric 198 1985 199 1995 2 2:198 $MB 8, 88 1 3 1 8, access (ns) 375 2 1 7 6 6 IO bus typical size(mb).64.256 4 16 64 1, metric 198 1985 199 1995 2 2:198 USB mouse keyboard graphics adapter monitor Disk $MB 5 1 8.3.5 1, access (ms) 87 75 28 1 8 11 typical size(mb) 1 1 16 1, 9, 9, F13 29 Datorarkitektur 29 F13 3 Datorarkitektur 29 CPU Clock Rates The CPU-Memory Gap The increasing gap between DRM,, and CPU speeds. 198 1985 199 1995 2 2:198 processor 88 286 386 Pent P-III clock rate(mhz) 1 6 2 15 75 75 cycle time(ns) 1, 166 5 6 1.6 75 ns 1,, 1,, 1,, 1, 1, 1, 1 1 1 198 1985 199 1995 2 Disk seek time DRM access time SRM access time CPU cycle time year F13 31 Datorarkitektur 29 F13 32 Datorarkitektur 29
Locality Principle of Locality: Programs tend to reuse data and instructions near those they have used recently, or that were recently referenced themselves. Temporal locality: Recently referenced items are likely to be referenced in the near future. Spatial locality: Items with nearby addresses tend to be referenced close together in time. Locality Example: Data Reference array elements in succession (stride-1 reference pattern): Spatial locality Reference sum each iteration: Temporal locality Instructions Reference instructions in sequence: Spatial locality Cycle through loop repeatedly: Temporal locality sum = ; for (i = ; i < n; i++) sum += a[i]; return sum; F13 33 Datorarkitektur 29 Locality Example Claim: Being able to look at code and get a qualitative sense of its locality is a key skill for a professional programmer. Question: Does this function have good locality? int sumarrayrows(int a[m][n]) { int i, j, sum = ; } for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum F13 34 Datorarkitektur 29 Locality Example Question: Does this function have good locality? int sumarraycols(int a[m][n]) { int i, j, sum = ; } for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum Locality Example Question: Can you permute the loops so that the function scans the 3-d array a[] with a stride-1 reference pattern (and thus has good spatial locality)? int sumarray3d(int a[m][n][n]) { int i, j, k, sum = ; } for (i = ; i < M; i++) for (j = ; j < N; j++) for (k = ; k < N; k++) sum += a[k][i][j]; return sum F13 35 Datorarkitektur 29 F13 36 Datorarkitektur 29
Memory Hierarchies Some fundamental and enduring properties of hardware and software: Fast storage technologies cost more per byte and have less capacity. The gap between CPU and main speed is widening. Well-written programs tend to exhibit good locality. These fundamental properties complement each other beautifully. They suggest an approach for organizing and storage systems known as a hierarchy. F13 37 Datorarkitektur 29 n Example Memory Hierarchy Smaller, faster, L: registers CPU registers hold words retrieved from and L1 cache. costlier L1: on-chip L1 (per byte) cache (SRM) L1 cache holds cache lines retrieved storage L2: off-chip L2 from the L2 cache. devices cache (SRM) L2 cache holds cache lines retrieved from main. Larger, L3: main slower, (DRM) Main holds and blocks retrieved from local s. cheaper L4: local secondary storage (per byte) (local s) Local s hold files storage retrieved from s on devices remote network servers. L5: remote secondary storage (distributed file systems, Web servers) F13 38 Datorarkitektur 29 Caches Cache: smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device. Fundamental idea of a hierarchy: For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1. Why do hierarchies work? Programs tend to access the data at level k more often than they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus larger and cheaper per bit. Net effect: large pool of that costs as much as the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top. F13 39 Datorarkitektur 29 Caching in a Memory Hierarchy Smaller, faster, more expensive Level k: 48 9 14 1 3 device at level k caches a subset of the blocks from level k+1 Data is copied between 1 4 levels in block-sized transfer units 1 2 3 Level k+1: 4 5 6 7 Larger, slower, cheaper storage device at level k+1 is partitioned 8 9 1 11 into blocks. 12 13 14 15 F13 4 Datorarkitektur 29
Level k+1: General Caching Concepts Level k: 14 12 12 4* Request 14 12 1 2 3 4* 12 9 14 3 Request 12 1 2 3 4* 4 5 6 7 8 9 1 11 12 13 14 15 Program needs object d, which is stored in some block b. Cache hit Program finds b in the cache at level k. Cache miss E.g., block 14. b is not at level k, so level k cache must fetch it from level k+1. E.g., block 12. If level k cache is full, then some current block must be replaced (evicted). Which one is the victim? Placement policy: where can the new block go? E.g., b mod 4 Replacement policy: which block should be evicted? E.g., LRU F13 41 Datorarkitektur 29 General Caching Concepts Types of cache misses: Cold (compulsary) miss Cold misses occur because the cache is empty. Conflict miss Most caches limit blocks at level k+1 to a small subset (sometimes a singleton) of the block positions at level k. E.g. Block i at level k+1 must be placed in block (i mod 4) at level k. Conflict misses occur when the level k cache is large enough, but multiple data objects all map to the same level k block. E.g. Referencing blocks, 8,, 8,, 8,... would miss every time. Capacity miss Occurs when the set of active cache blocks (working set) is larger than the cache. F13 42 Datorarkitektur 29 Examples of Caching in the Hierarchy Cache Type What Cached Where Cached Latency Managed By (cycles) Registers 4-byte word CPU registers Compiler TLB ddress On-Chip TLB Hardware translations L1 cache 32-byte block On-Chip L1 1 Hardware L2 cache 32-byte block Off-Chip L2 1 Hardware Virtual Memory 4-KB page Main 1 Hardware+ OS Buffer cache Parts of files Main 1 OS Network buffer Parts of files Local 1,, FSNFS cache client Browser cache Web pages Local 1,, Web browser Web cache Web pages Remote server 1,,, Web proxy s server F13 43 Datorarkitektur 29