PI6F84A 7.0 INSTRUTION SET SUMMARY Each PI6XX instruction is a 4bit word, divided into an OPODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PI6XX instruction set summary in Table 7 lists byteoriented, bitoriented, and literal and control operations. Table 7 shows the opcode field descriptions. For byteoriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bitoriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the address of the file in which the bit is located. For literal and control operations, represents an eight or eleven bit constant or literal value. TABLE 7: Field f W b OPODE FIELD DESRIPTIONS Description Register file address (0x to 0x7F) Woring register (accumulator) Bit address within an 8bit file register Literal field, constant data or label x Don't care location (= 0 or ) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = : store result in file register f. Default is d = P TO PD Program ounter Timeout bit Powerdown bit The instruction set is highly orthogonal and is grouped into three basic categories: Byteoriented operations Bitoriented operations Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution taes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is µs. Table 7 lists the instructions recognized by the MPASM Assembler. Figure 7 shows the general formats that the instructions can have. Note: All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 7: To maintain upward compatibility with future PI6XX products, do not use the OPTION and TRIS instructions. GENERAL FORMAT FOR INSTRUTIONS Byteoriented file register operations 3 8 7 6 0 OPODE d f (FILE #) d = 0 for destination W d = for destination f f = 7bit file register address Bitoriented file register operations 3 0 9 7 6 0 OPODE b (BIT #) f (FILE #) b = 3bit bit address f = 7bit file register address Literal and control operations General 3 8 7 0 OPODE = 8bit immediate value ALL and GOTO instructions only (literal) 3 0 0 OPODE = bit immediate value (literal) A description of each instruction is available in the PImicro MidRange Reference Manual (DS3303). 0 Microchip Technology Inc. DS357Bpage 35
PI6F84A TABLE 7: PI6XXX INSTRUTION SET Mnemonic, Operands Description ycles MSb 4Bit Opcode LSb Status Affected Notes ADDWF ANDWF LRF LRW OMF DEF DEFS INF INFS IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BF BSF BTFS BTFSS ADDLW ANDLW ALL LRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f f f, b f, b f, b f, b Add W and f AND W with f lear f lear W omplement f Decrement f Decrement f, Sip if 0 Increment f Increment f, Sip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through arry Rotate Right f through arry Subtract W from f Swap nibbles in f Exclusive OR W with f Bit lear f Bit Set f Bit Test f, Sip if lear Bit Test f, Sip if Set Add literal and W AND literal with W all subroutine lear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W BYTEORIENTED FILE REGISTER OPERATIONS () () BITORIENTED FILE REGISTER OPERATIONS () () 0 0 0 0 LITERAL AND ONTROL OPERATIONS 0 0 0 0 0 0 0 0 0 0 0 bb 0bb 0bb bb x 0 0 xx 0xx 0x lfff 0xxx lfff 0xx0 bfff bfff bfff bfff xxxx 0 0,D,,D,,D, TO,PD TO,PD,D, Note : When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, ), the value used will be that value present on the pins themselves. For example, if the data latch is for a pin configured as input and is driven low by an external device, the data will be written bac with a 0. : If this instruction is executed on the TMR0 register (and, where applicable, d = ), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program ounter (P) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.,,,,,,3,,,3,,,,,,,,, 3 3 Note: Additional information on the midrange instruction set is available in the PImicro MidRange MU Family Reference Manual (DS3303). DS357Bpage 36 0 Microchip Technology Inc.
PI6F84A 7. Instruction Descriptions ADDLW Add Literal and W [label] ADDLW 0 55 (W) + (W), D, The contents of the W register are added to the eightbit literal and the result is placed in the W register. BF Bit lear f [label] BF f,b 0 f 7 0 b 7 0 (f<b>) Bit 'b' in register 'f' is cleared. ADDWF Add W and f [label] ADDWF f,d 0 f 7 d [0,] (W) + (f) (destination), D, Add the contents of the W register with If d is 0, the result is stored in the W register. If d is, the result is stored bac in BSF Bit Set f [label] BSF f,b 0 f 7 0 b 7 (f<b>) Bit 'b' in register 'f' is set. ANDLW AND Literal with W [label] ANDLW 0 55 ANDWF (W).AND. () (W) The contents of W register are AND ed with the eightbit literal ''. The result is placed in the W register. AND W with f [label] ANDWF f,d 0 f 7 d [0,] (W).AND. (f) (destination) AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. BTFSS Bit Test f, Sip if Set [label] BTFSS f,b 0 f 7 0 b < 7 sip if (f<b>) = If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '', then the next instruction is discarded and a NOP is executed instead, maing this a TY instruction. 0 Microchip Technology Inc. DS357Bpage 37
PI6F84A BTFS Bit Test, Sip if lear [label] BTFS f,b 0 f 7 0 b 7 sip if (f<b>) = 0 If bit b in register f is, the next instruction is executed. If bit b in register f is 0, the next instruction is discarded, and a NOP is executed instead, maing this a TY instruction. LRWDT lear Watchdog Timer [ label ] LRWDT h WDT 0 WDT prescaler, TO PD TO, PD LRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. ALL all Subroutine [ label ] ALL 0 047 (P)+ TOS, P<0:0>, (PLATH<4:3>) P<:> all Subroutine. First, return address (P+) is pushed onto the stac. The elevenbit immediate address is loaded into P bits <0:0>. The upper bits of the P are loaded from PLATH. ALL is a twocycle instruction. OMF omplement f [ label ] OMF f,d 0 f 7 d [0,] (f) (destination) complemented. If d is 0, the result is stored in W. If d is, the result is stored bac in LRF lear f [label] LRF f 0 f 7 LRW h (f) cleared and the bit is set. lear W [ label ] LRW h (W) W register is cleared. ero bit () is set. DEF Decrement f [label] DEF f,d 0 f 7 d [0,] (f) (destination) Decrement If d is 0, the result is stored in the W register. If d is, the result is stored bac in DS357Bpage 38 0 Microchip Technology Inc.
PI6F84A DEFS Decrement f, Sip if 0 0 f 7 d [0,] [ label ] DEFS f,d (f) (destination); sip if result = 0 decremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in If the result is, the next instruction is executed. If the result is 0, then a NOP is executed instead, maing it a TY instruction. INFS Increment f, Sip if 0 0 f 7 d [0,] [ label ] INFS f,d (f) + (destination), sip if result = 0 incremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in If the result is, the next instruction is executed. If the result is 0, a NOP is executed instead, maing it a TY instruction. GOTO Unconditional Branch [ label ] GOTO 0 047 P<0:0> PLATH<4:3> P<:> GOTO is an unconditional branch. The elevenbit immediate value is loaded into P bits <0:0>. The upper bits of P are loaded from PLATH<4:3>. GOTO is a twocycle instruction. IORLW Inclusive OR Literal with W [ label ] IORLW 0 55 (W).OR. (W) The contents of the W register are OR ed with the eightbit literal ''. The result is placed in the W register. INF Increment f [ label ] INF f,d 0 f 7 d [0,] (f) + (destination) incremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in IORWF 0 f 7 d [0,] Inclusive OR W with f [ label ] IORWF f,d (W).OR. (f) (destination) Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is, the result is placed bac in register 'f'. 0 Microchip Technology Inc. DS357Bpage 39
PI6F84A MOVF Move f [ label ] MOVF f,d 0 f 7 d [0,] (f) (destination) The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d =, the destination is file register f itself. d = is useful to test a file register, since status flag is affected. RETFIE Return from Interrupt [ label ] RETFIE TOS P, GIE MOVLW Move Literal to W [ label ] MOVLW 0 55 (W) The eightbit literal is loaded into W register. The don t cares will assemble as 0 s. RETLW Return with Literal in W [ label ] RETLW 0 55 (W); TOS P The W register is loaded with the eightbit literal ''. The program counter is loaded from the top of the stac (the return address). This is a twocycle instruction. MOVWF Move W to f [ label ] MOVWF f 0 f 7 (W) (f) Move data from W register to register 'f'. RETURN Return from Subroutine [ label ] RETURN TOS P Return from subroutine. The stac is POPed and the top of the stac (TOS) is loaded into the program counter. This is a twocycle instruction. NOP No Operation [ label ] NOP No operation No operation. DS357Bpage 40 0 Microchip Technology Inc.
PI6F84A RLF Rotate Left f through arry [ label ] RLF f,d 0 f 7 d [0,] See description below rotated one bit to the left through the arry Flag. If d is 0, the result is placed in the W register. If d is, the result is stored bac in Register f SUBLW Subtract W from Literal [ label ] SUBLW 0 55 (W) (W), D, The W register is subtracted ( s complement method) from the eightbit literal ''. The result is placed in the W register. RRF Rotate Right f through arry [ label ] RRF f,d 0 f 7 d [0,] See description below rotated one bit to the right through the arry Flag. If d is 0, the result is placed in the W register. If d is, the result is placed bac in Register f SUBWF Subtract W from f [ label ] SUBWF f,d 0 f 7 d [0,], D, (f) (W) (destination) Subtract ( s complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. SLEEP [ label ] SLEEP h WDT, 0 WDT prescaler, TO, 0 PD TO, PD The powerdown status bit, PD is cleared. Timeout status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. SWAPF Swap Nibbles in f [ label ] SWAPF f,d 0 f 7 d [0,] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is, the result is placed in register 'f'. 0 Microchip Technology Inc. DS357Bpage 4
PI6F84A XORLW Exclusive OR Literal with W [label] XORLW 0 55 (W).XOR. (W) The contents of the W register are XOR ed with the eightbit literal ''. The result is placed in the W register. XORWF Exclusive OR W with f [label] XORWF f,d 0 f 7 d [0,] (W).XOR. (f) (destination) Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. DS357Bpage 4 0 Microchip Technology Inc.