From 3D Toolbox to 3D Integration: Examples of Successful 3D Applicative Demonstrators N.Sillon
Agenda Introduction 2,5D: Silicon Interposer 3DIC: Wide I/O Memory-On-Logic 3D Packaging: X-Ray sensor Conclusion TSV SUMMIT N.Sillon 2
What could be a silicon chip in 10 Years Stacked advanced logic + Memory Moving parts (MEMS) Stacked Memory Passives components Of course, it seems to be: Too expensive Optical I/O Not compatible with an efficient supply chain Not repairable Difficult to test Not reliable. Thermal management A silicon interposer TSV SUMMIT N.Sillon 3
Silicon interposer 5 years ago It seemed to be: Too expensive Not compatible with an efficient supply chain Not repairable Difficult to test Not reliable Flip Chip Avec TSV Si Interposer And Today: Commercially available in foundries and used by major fabless Source: Xilinx Source: Altera TSV SUMMIT N.Sillon 4
What could be a silicon chip in 10 Years Of course, it seems to be: Too expensive Not compatible with an efficient supply chain Not repairable Difficult to test Not reliable. A good target to drive 3D integration Toolbox developments TSV SUMMIT N.Sillon 5
A lot of intermediate stand alone products (and businesses ). Stacked DRAM or Flash Memory on Application Processor MEMS on its IC driver Multichip Interposer (2,5 D) for FPGA Focus 3 applications 3 ways of collaboration with Leti TSV SUMMIT N.Sillon 6
Agenda Introduction 2,5D: Silicon Interposer 3DIC: Wide I/O Memory-On-Logic 3D Packaging: Imaging Conclusion TSV SUMMIT N.Sillon 7
Silicon Interposer for supercomputers 3 years Common Lab, 3 assignes TSV SUMMIT N.Sillon 8
Process flow for interposer Example of Leti-Shinko High Density interposer <<< << Total size: 26x26mm, Thickness 100µm Micro Copper bumps: Pitch 50µm, 100000/interposer Damascene: 2 line and 1 via levels, CDmin 0.5µm TSV: 10x100µm RDL and passivation: CDmin 10µm High pillars: pitch 500µm, height TSV SUMMIT N.Sillon 9
Process flow description: front side TSV etching TSV insulation TSV and line 1 metallization Damascene levels Micro bumps Temporary bonding TSV SUMMIT N.Sillon 10
Process flow description: back side Back side thinning and TSV exposure Backside Redistribution Layer Backside passivation and High Pillars Debonding TSV SUMMIT N.Sillon 11
Physical characterisation: cross section Good integrity of the overall structure: no delamination No copper extrusion or residue between TSV and Line 1 No copper extrusion or residue between TSV and Backside RDL TSV SUMMIT N.Sillon 12
Process flow description: Assembly Silicon interposer After mounting (4chip, Si-IP, Organic substrate) Silicon interposer chip chip Organic substrate TSV SUMMIT N.Sillon 13
On Going Developments BOW/Constraint management Dev. of low stress BEOL Insertion of compensation layers TSV SUMMIT N.Sillon 14
On Going Developments BOW/Constraint management Underfill materials for high troughput CTE mismatch compensation between organic substrate and Silicon Interposer Evolution towards Silicon Package TSV SUMMIT N.Sillon 15
Agenda Introduction 2,5D: Silicon Interposer 3DIC: Wide I/O Memory-On-Logic 3D Packaging: X-Ray sensor Conclusion TSV SUMMIT N.Sillon 16
3D ST-Leti: from Lab to Fab Prototyping/Production Industrial maturity and stability Short Cycle time 2 complementary Lines Maturity Advanced Dev Advanced flows Advanced demonstrators Benchmark tools Design Teams STE/STM/Leti Advanced modules
3D Integration successes Leti-STMicro ST implement TSV for CMOS image sensors in 300mm (Process from Leti) Partitioning 45nm/130 nm Demonstrator (Set Top Box application) 300mm R&D Line for 3D Integration @ Leti Wide I/O Memory + Logic stack. Partitioning Analog/Logic Demonstrator. HDMI Product 2008 2010 2011 2012 18
Wide I/O DRAM stacking on Logic Objectives SoC in advanced CMOS node Quad-channel Wide I/O DRAM* Bandwidth >10GByte/s Reduced power consumption Face to back 3D integration Top die: μ-bumps Bottom die: Bumps, TSV & μ-pillars Die-to-die stacking on BGA * JEDEC standard JESD229 TSV SUMMIT N.Sillon 19
Wide I/O : Design Channel 0 Channel 1 Bank 0 Bank 1 Bank 0 Bank 1 Bank 2 Bank n Bank 2 Bank n Bank 0 Bank 1 Bank 0 Bank 1 Bank 2 Bank n Bank 2 Bank n Design STE/Leti Mag3D platform: Low power, NoC based architecture Channel 2 Channel 3 Commercial memory Wide-IO memory: Power efficient and high bandwidth TSV SUMMIT N.Sillon 20
3D ST-Leti: from Lab to Fab Temporary Bonding/debonding Back side TSV reveal Si Cu SiO 2 SiO 2 /Ta Advanced modules Micro pillar
3D ST-Leti: from Lab to Fab Wide I/O Daisy Chain Maturity Advanced Dev Advanced flows Advanced demonstrators Benchmark tools No TSV leakage Advanced modules > 98% yield on TSV chain
3D ST-Leti: from Lab to Fab Prototyping/Production Industrial maturity and stability Short Cycle time WIDE IO DRAM Maturity Advanced Dev Wide I/O demonstrator CuNiAu µ-pillar SoC TSV Advanced flows Advanced demonstrators Benchmark tools Bump Advanced modules BGA
Memory on Application Processor Wioming SoC [1], co-designed by CEA / ST-Ericsson 73 mm 2, 1250 TSV and ~1000 Bumps Bottom / BGA Wide I/O DRAM 1GB, 4x128 bits, 200MHz 3D Process and test performed in Grenoble Wioming SoC floorplan WIDE IO DRAM SoC WIDE IO DRAM CuNiAu µ-pillar SoC TSV Full functionality demonstrated with high final test yield Performances exceed JEDEC Wide IO standard Bandwidth Power consumption Bump BGA TSV SUMMIT N.Sillon 24 [1] A Three-Layers 3D-IC Stack including Wide IO and a 3D NoC - a Practical Design Perspective P. Vivet & al, RTI 2011
Agenda Introduction 2,5D: Silicon Interposer 3DIC: Wide I/O Memory-On-Logic 3D Packaging: : X-Ray sensor Conclusion TSV SUMMIT N.Sillon 25
Open 3D: starting point TSV / 3D can be a solution for a lot of devices, whatever the reason (compacity, heterogeneity, cost, performance ) A complete 3D development is long and costly (techno developement, specific design, ). Mature/flexible technologies can be used for low cost demonstrators TSV SUMMIT N.Sillon 26
Open 3D : Boost 3D diffusion in applications Our goal: facilitate access to 3D technology Need 3D on your wafers? Open 3D TechBox 3D Design & Layout 3D Technology 3D Packaging
First success story : Open 3D for CERN high spatial, high contrast resolving CMOS pixel read-out chip working in single photon counting mode It can be combined with different semiconductor sensors which convert the X- rays directly into detectable electric signals. This represents a new solution for various X- ray and gamma-ray imaging applications. Project started On June 2011 First wafers delivered on January 2012 TSV TSV SUMMIT N.Sillon 28
First success story : Open 3D for CERN Design Test structures Process Flow Wafer view Single chip Technology RDL Back side UBM Medipix wafer after front side UBM Accoustic image of the bonding interface TSV Thin wafer on tape TSV SUMMIT N.Sillon 29
% First success story : Open 3D for CERN Contact UBM Wafer level Electrical Tests Functionnal tests on ASICS P01-Résistance cumulée Chaine de 2 TSV (VSS) 100 90 80 70 60 TSV 2 TSV chain resistance 50 40 30 20 Test RDL Test Final 10 0 5.20E -01 5.40E -01 5.60E -01 5.80E -01 6.00E -01 6.20E -01 6.40E -01 Ohms Chip Delivery & test GELPAK of 16 diced chips Test Board & socket (Courtesy of Jerome ALOZY / CERN) TSV SUMMIT N.Sillon 30
1 1 First success story : Open 3D for CERN W24-H2 DAC dependency (Courtesy of Jerome ALOZY / CERN) Next step: Integration
Conclusion We have in mind complete 3D integrated systems with intermediate products. Concrete 3D integrations demonstrators have been achieved with partners, allowing low capex validation and anticipation of integration problems for manufacturing Silicon Interposer 3D IC memory on logic Xray Detector Toolbox development is still on going for next gen with tools/materials suppliers TSV SUMMIT N.Sillon 32
Warm Thanks to all 3D community TSV SUMMIT N.Sillon 33
Merci de votre attention TSV SUMMIT N.Sillon 34